* [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events
@ 2022-12-15 6:54 Ian Rogers
2022-12-15 6:54 ` [PATCH v1 10/32] perf vendor events intel: Refresh goldmont events Ian Rogers
` (22 more replies)
0 siblings, 23 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the elkhartlake events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/elkhartlake/cache.json | 252 ------------------
.../arch/x86/elkhartlake/floating-point.json | 11 -
.../arch/x86/elkhartlake/frontend.json | 36 ---
.../arch/x86/elkhartlake/memory.json | 84 ------
.../arch/x86/elkhartlake/other.json | 143 ----------
.../arch/x86/elkhartlake/pipeline.json | 213 ---------------
.../arch/x86/elkhartlake/virtual-memory.json | 117 --------
7 files changed, 856 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json b/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
index d674ee88c3a5..0ab90e3bf76b 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
@@ -1,1137 +1,885 @@
[
{
"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "DL1.DIRTY_EVICTION",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "L2_REJECT_XQ.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.REJECTS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x4f"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x38"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x7"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a store buffer being full.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of load uops retired that miss in the L1 data cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of load uops retired that miss in the L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of memory uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)",
"SampleAfterValue": "200003",
"UMask": "0x83"
},
{
"BriefDescription": "Counts the number of load uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of load uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x81"
},
{
"BriefDescription": "Counts the number of store uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of store uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x82"
},
{
"BriefDescription": "Counts the number of load uops retired that performed one or more locks.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x21"
},
{
"BriefDescription": "Counts the number of memory uops retired that were splits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x43"
},
{
"BriefDescription": "Counts the number of retired split load uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "Counts the number of retired split store uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x42"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3001F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x401F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x101F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x201F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ICACHE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x20"
}
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
index 2e1b80c714fd..88522244b760 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
@@ -1,36 +1,25 @@
[
{
"BriefDescription": "Counts the number of cycles the floating point divider is busy.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcd",
"EventName": "CYCLES_DIV_BUSY.FPDIV",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the floating point divider is busy. Does not imply a stall waiting for the divider.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
"SampleAfterValue": "20003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x8"
}
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json b/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
index 5d938a5dafcf..5ba998e06592 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
@@ -1,103 +1,67 @@
[
{
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.COND",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of BACLEARS due to an indirect branch.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.INDIRECT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of BACLEARS due to a return branch.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.RETURN",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.UNCOND",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe9",
"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts the number of instruction cache hits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of requests that hit in the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of instruction cache misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json b/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
index 15eba23796e4..18621909d1a9 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
@@ -1,441 +1,357 @@
[
{
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.OTHER.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.OTHER.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x402184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x402184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PREFETCHES.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000470",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x102184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x102184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x202184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x202184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
index 4a1b7cc5aa23..00ae180ded25 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
@@ -1,674 +1,531 @@
[
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EdgeDetect": "1",
"EventCode": "0x63",
"EventName": "BUS_LOCK.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.BLOCK_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.CYCLES_SELF_BLOCK",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.LOCK_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EdgeDetect": "1",
"EventCode": "0x63",
"EventName": "BUS_LOCK.SELF_LOCKS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "C0_STALLS.LOAD_DRAM_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "C0_STALLS.LOAD_L2_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "C0_STALLS.LOAD_LLC_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of core cycles during which interrupts are masked (disabled).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcb",
"EventName": "HW_INTERRUPTS.MASKED",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcb",
"EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of hardware interrupts received by the processor.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcb",
"EventName": "HW_INTERRUPTS.RECEIVED",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "203",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3000000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8003000000000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all hardware and software prefetches that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PREFETCHES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10470",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000100000000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
index 09919fdb9a38..9dd8c909facc 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
@@ -1,662 +1,449 @@
[
{
"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of near CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xf9"
},
{
"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xbf"
},
{
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.JCC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfd"
},
{
"BriefDescription": "Counts the number of near RET branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.RETURN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.JCC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Counts the total number of BTCLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe8",
"EventName": "BTCLEAR.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "34",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcd",
"EventName": "CYCLES_DIV_BUSY.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of cycles the integer divider is busy.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcd",
"EventName": "CYCLES_DIV_BUSY.IDIV",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the total number of instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.4K_ALIAS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003"
},
{
"BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.PAGE_FAULT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "This event is deprecated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.CISC",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.DECODE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ITLB",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.OTHER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the total number of consumed retirement slots.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "TOPDOWN_RETIRING.ALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of uops issued by the front end every cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the total number of uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of integer divide uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.IDIV",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.X87",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x2"
}
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
index b82f11591f13..cabe29e70e79 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
@@ -1,363 +1,246 @@
[
{
"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Entry hits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDE_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of Extended Page Directory Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Entry misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Pointer Entry hits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDPE_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number Extended Page Directory Pointer Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Pointer Entry misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDPE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number Extended Page Directory Pointer Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.WALK_PENDING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "ITLB.FILLS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.PDE_CACHE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk).",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DTLB_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x13"
},
{
"BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x11"
},
{
"BriefDescription": "Counts the number of store uops retired that miss in the second level TLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x12"
}
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 10/32] perf vendor events intel: Refresh goldmont events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 11/32] perf vendor events intel: Refresh goldmontplus events Ian Rogers
` (21 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the goldmont events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/goldmont/cache.json | 288 ------------------
.../arch/x86/goldmont/floating-point.json | 6 -
.../arch/x86/goldmont/frontend.json | 16 -
.../pmu-events/arch/x86/goldmont/memory.json | 6 -
.../pmu-events/arch/x86/goldmont/other.json | 10 -
.../arch/x86/goldmont/pipeline.json | 77 -----
.../arch/x86/goldmont/virtual-memory.json | 14 -
7 files changed, 417 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/cache.json b/tools/perf/pmu-events/arch/x86/goldmont/cache.json
index ed957d4f9c6d..ee47a09172a1 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/cache.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Requests rejected by the L2Q",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ALL",
"PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "L1 Cache evictions for dirty data",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "DL1.DIRTY_EVICTION",
"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback.",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.",
@@ -30,8 +24,6 @@
},
{
"BriefDescription": "Requests rejected by the XQ",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "L2_REJECT_XQ.ALL",
"PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.",
@@ -39,8 +31,6 @@
},
{
"BriefDescription": "L2 cache request misses",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
@@ -49,8 +39,6 @@
},
{
"BriefDescription": "L2 cache requests",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
@@ -59,8 +47,6 @@
},
{
"BriefDescription": "Loads retired that came from DRAM (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
@@ -83,8 +67,6 @@
},
{
"BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
@@ -95,8 +77,6 @@
},
{
"BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
@@ -107,8 +87,6 @@
},
{
"BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
@@ -119,8 +97,6 @@
},
{
"BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
@@ -131,8 +107,6 @@
},
{
"BriefDescription": "Loads retired that hit WCB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
@@ -143,8 +117,6 @@
},
{
"BriefDescription": "Memory uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL",
@@ -155,8 +127,6 @@
},
{
"BriefDescription": "Load uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@@ -167,8 +137,6 @@
},
{
"BriefDescription": "Store uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
@@ -179,8 +147,6 @@
},
{
"BriefDescription": "Locked load uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
@@ -191,8 +157,6 @@
},
{
"BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT",
@@ -203,8 +167,6 @@
},
{
"BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@@ -215,8 +177,6 @@
},
{
"BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
@@ -227,8 +187,6 @@
},
{
"BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100007",
@@ -236,1066 +194,820 @@
},
{
"BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000043091",
- "Offcore": "1",
"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600003091",
- "Offcore": "1",
"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000003091",
- "Offcore": "1",
"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400003091",
- "Offcore": "1",
"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200003091",
- "Offcore": "1",
"PublicDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000043010",
- "Offcore": "1",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600003010",
- "Offcore": "1",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000003010",
- "Offcore": "1",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400003010",
- "Offcore": "1",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200003010",
- "Offcore": "1",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00000432b7",
- "Offcore": "1",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x36000032b7",
- "Offcore": "1",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10000032b7",
- "Offcore": "1",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04000032b7",
- "Offcore": "1",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x02000032b7",
- "Offcore": "1",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000018000",
- "Offcore": "1",
"PublicDescription": "Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000048000",
- "Offcore": "1",
"PublicDescription": "Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000008000",
- "Offcore": "1",
"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400008000",
- "Offcore": "1",
"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200008000",
- "Offcore": "1",
"PublicDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000040022",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600000022",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000022",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000022",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000022",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010400",
- "Offcore": "1",
"PublicDescription": "Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT",
"MSRIndex": "0x1a6",
"MSRValue": "0x0000040008",
- "Offcore": "1",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY",
"MSRIndex": "0x1a6",
"MSRValue": "0x3600000008",
- "Offcore": "1",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6",
"MSRValue": "0x1000000008",
- "Offcore": "1",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6",
"MSRValue": "0x0400000008",
- "Offcore": "1",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6",
"MSRValue": "0x0200000008",
- "Offcore": "1",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000040004",
- "Offcore": "1",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600000004",
- "Offcore": "1",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000004",
- "Offcore": "1",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000004",
- "Offcore": "1",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000004",
- "Offcore": "1",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000040001",
- "Offcore": "1",
"PublicDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600000001",
- "Offcore": "1",
"PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000001",
- "Offcore": "1",
"PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000001",
- "Offcore": "1",
"PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000001",
- "Offcore": "1",
"PublicDescription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000001",
- "Offcore": "1",
"PublicDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000040002",
- "Offcore": "1",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600000002",
- "Offcore": "1",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000002",
- "Offcore": "1",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000002",
- "Offcore": "1",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000002",
- "Offcore": "1",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000002",
- "Offcore": "1",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000040800",
- "Offcore": "1",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600000800",
- "Offcore": "1",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000800",
- "Offcore": "1",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000800",
- "Offcore": "1",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000800",
- "Offcore": "1",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600000080",
- "Offcore": "1",
"PublicDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000044000",
- "Offcore": "1",
"PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600004000",
- "Offcore": "1",
"PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000004000",
- "Offcore": "1",
"PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400004000",
- "Offcore": "1",
"PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200004000",
- "Offcore": "1",
"PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600000100",
- "Offcore": "1",
"PublicDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000042000",
- "Offcore": "1",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600002000",
- "Offcore": "1",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000002000",
- "Offcore": "1",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400002000",
- "Offcore": "1",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200002000",
- "Offcore": "1",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000040010",
- "Offcore": "1",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600000010",
- "Offcore": "1",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000010",
- "Offcore": "1",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000010",
- "Offcore": "1",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000010",
- "Offcore": "1",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000040020",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600000020",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000020",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000020",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000020",
- "Offcore": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000044800",
- "Offcore": "1",
"PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600004800",
- "Offcore": "1",
"PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000041000",
- "Offcore": "1",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3600001000",
- "Offcore": "1",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000001000",
- "Offcore": "1",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400001000",
- "Offcore": "1",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200001000",
- "Offcore": "1",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
index 37174392a510..a3f03855ca05 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles the FP divide unit is busy",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.FPDIV",
"PublicDescription": "Counts core cycles the floating point divide unit is busy.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Machine clears due to FP assists",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Floating point divide uops retired. (Precise Event Capable)",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "2",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json
index 216da6e121c8..ace2a114b546 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "BACLEARs asserted for any branch type",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.ALL",
"PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "BACLEARs asserted for conditional branch",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.COND",
"PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "BACLEARs asserted for return branch",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.RETURN",
"PublicDescription": "Counts BACLEARS on return instructions.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Decode restrictions due to predicting wrong instruction length",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE9",
"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "MS decode starts",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE7",
"EventName": "MS_DECODED.MS_ENTRY",
"PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/memory.json b/tools/perf/pmu-events/arch/x86/goldmont/memory.json
index 9f6f0328249e..b97642a109ee 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Machine clears due to memory ordering issue",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Load uops that split a page (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
"PEBS": "2",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Store uops that split a page (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"PEBS": "2",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/other.json b/tools/perf/pmu-events/arch/x86/goldmont/other.json
index d888f67aa2ea..c4fd0acb15bc 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/other.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles code-fetch stalled due to any reason.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ALL",
"PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Cycles hardware interrupts are masked",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.MASKED",
"PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
@@ -30,8 +24,6 @@
},
{
"BriefDescription": "Cycles pending interrupts are masked",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
"PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
@@ -40,8 +32,6 @@
},
{
"BriefDescription": "Hardware interrupts received",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.RECEIVED",
"PublicDescription": "Counts hardware interrupts received by the processor.",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
index 42ff0b134aeb..acb897483a87 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Retired branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "2",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Retired taken branch instructions (Precise event capable)",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
"PEBS": "2",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Retired near call instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CALL",
"PEBS": "2",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Retired far branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "2",
@@ -44,8 +36,6 @@
},
{
"BriefDescription": "Retired near indirect call instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "2",
@@ -55,8 +45,6 @@
},
{
"BriefDescription": "Retired conditional branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.JCC",
"PEBS": "2",
@@ -66,8 +54,6 @@
},
{
"BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PEBS": "2",
@@ -77,8 +63,6 @@
},
{
"BriefDescription": "Retired near relative call instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "2",
@@ -88,8 +72,6 @@
},
{
"BriefDescription": "Retired near return instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.RETURN",
"PEBS": "2",
@@ -99,8 +81,6 @@
},
{
"BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PEBS": "2",
@@ -110,8 +90,6 @@
},
{
"BriefDescription": "Retired mispredicted branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "2",
@@ -120,8 +98,6 @@
},
{
"BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PEBS": "2",
@@ -131,8 +107,6 @@
},
{
"BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.JCC",
"PEBS": "2",
@@ -142,8 +116,6 @@
},
{
"BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS": "2",
@@ -153,8 +125,6 @@
},
{
"BriefDescription": "Retired mispredicted near return instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "2",
@@ -164,8 +134,6 @@
},
{
"BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PEBS": "2",
@@ -175,7 +143,6 @@
},
{
"BriefDescription": "Core cycles when core is not halted (Fixed event)",
- "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.",
"SampleAfterValue": "2000003",
@@ -183,8 +150,6 @@
},
{
"BriefDescription": "Core cycles when core is not halted",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
@@ -192,8 +157,6 @@
},
{
"BriefDescription": "Reference cycles when core is not halted",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF",
"PublicDescription": "Reference cycles when core is not halted. This event uses a programmable general purpose performance counter.",
@@ -202,7 +165,6 @@
},
{
"BriefDescription": "Reference cycles when core is not halted (Fixed event)",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.",
"SampleAfterValue": "2000003",
@@ -210,8 +172,6 @@
},
{
"BriefDescription": "Cycles a divider is busy",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.ALL",
"PublicDescription": "Counts core cycles if either divide unit is busy.",
@@ -219,8 +179,6 @@
},
{
"BriefDescription": "Cycles the integer divide unit is busy",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.IDIV",
"PublicDescription": "Counts core cycles the integer divide unit is busy.",
@@ -229,7 +187,6 @@
},
{
"BriefDescription": "Instructions retired (Fixed event)",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.",
"SampleAfterValue": "2000003",
@@ -237,8 +194,6 @@
},
{
"BriefDescription": "Instructions retired (Precise event capable)",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "2",
@@ -247,8 +202,6 @@
},
{
"BriefDescription": "Unfilled issue slots per cycle",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
@@ -256,8 +209,6 @@
},
{
"BriefDescription": "Unfilled issue slots per cycle to recover",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
@@ -266,8 +217,6 @@
},
{
"BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
@@ -276,8 +225,6 @@
},
{
"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.4K_ALIAS",
"PEBS": "2",
@@ -287,8 +234,6 @@
},
{
"BriefDescription": "Loads blocked (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"PEBS": "2",
@@ -298,8 +243,6 @@
},
{
"BriefDescription": "Loads blocked due to store data not ready (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PEBS": "2",
@@ -309,8 +252,6 @@
},
{
"BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PEBS": "2",
@@ -320,8 +261,6 @@
},
{
"BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.UTLB_MISS",
"PEBS": "2",
@@ -331,8 +270,6 @@
},
{
"BriefDescription": "All machine clears",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.ALL",
"PublicDescription": "Counts machine clears for any reason.",
@@ -340,8 +277,6 @@
},
{
"BriefDescription": "Machine clears due to memory disambiguation",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
"PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.",
@@ -350,8 +285,6 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.",
@@ -360,8 +293,6 @@
},
{
"BriefDescription": "Uops issued to the back end per cycle",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
@@ -369,8 +300,6 @@
},
{
"BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UOPS_NOT_DELIVERED.ANY",
"PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
@@ -378,8 +307,6 @@
},
{
"BriefDescription": "Uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "2",
@@ -388,8 +315,6 @@
},
{
"BriefDescription": "Integer divide uops retired. (Precise Event Capable)",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.IDIV",
"PEBS": "2",
@@ -399,8 +324,6 @@
},
{
"BriefDescription": "MS uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MS",
"PEBS": "2",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
index 2e17e02e1463..8c4929a517fa 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "ITLB misses",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "ITLB.MISS",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
@@ -23,8 +19,6 @@
},
{
"BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
@@ -35,8 +29,6 @@
},
{
"BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
@@ -47,8 +39,6 @@
},
{
"BriefDescription": "Duration of page-walks in cycles",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.CYCLES",
"PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.",
@@ -57,8 +47,6 @@
},
{
"BriefDescription": "Duration of D-side page-walks in cycles",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.",
@@ -67,8 +55,6 @@
},
{
"BriefDescription": "Duration of I-side pagewalks in cycles",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 11/32] perf vendor events intel: Refresh goldmontplus events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
2022-12-15 6:54 ` [PATCH v1 10/32] perf vendor events intel: Refresh goldmont events Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 12/32] perf vendor events intel: Refresh haswell metrics and events Ian Rogers
` (20 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the goldmontplus events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/goldmontplus/cache.json | 470 ------------------
.../arch/x86/goldmontplus/floating-point.json | 11 -
.../arch/x86/goldmontplus/frontend.json | 32 --
.../arch/x86/goldmontplus/memory.json | 10 -
.../arch/x86/goldmontplus/other.json | 20 -
.../arch/x86/goldmontplus/pipeline.json | 143 ------
.../arch/x86/goldmontplus/virtual-memory.json | 69 ---
7 files changed, 755 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
index 16e8913c0434..a7f80fd1b1df 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
@@ -1,1463 +1,993 @@
[
{
"BriefDescription": "Requests rejected by the L2Q",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ALL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "L1 Cache evictions for dirty data",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "DL1.REPLACEMENT",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Requests rejected by the XQ",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "L2_REJECT_XQ.ALL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "L2 cache request misses",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "L2 cache requests",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x4f"
},
{
"BriefDescription": "Loads retired that came from DRAM (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks.",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts load uops retired that hit the L1 data cache.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts load uops retired that miss the L1 data cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts load uops retired that hit in the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts load uops retired that miss in the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Loads retired that hit WCB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs.",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "Memory uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of memory uops retired that is either a loads or a store or both.",
"SampleAfterValue": "200003",
"UMask": "0x83"
},
{
"BriefDescription": "Load uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of load uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x81"
},
{
"BriefDescription": "Store uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of store uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x82"
},
{
"BriefDescription": "Locked load uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks.",
"SampleAfterValue": "200003",
"UMask": "0x21"
},
{
"BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.",
"SampleAfterValue": "200003",
"UMask": "0x43"
},
{
"BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.",
"SampleAfterValue": "200003",
"UMask": "0x42"
},
{
"BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000013091",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000043091",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000003091",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200003091",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000003091",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000013010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000043010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000003010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200003010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000003010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x00000132b7",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x00000432b7",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x10000032b7",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x02000032b7",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x40000032b7",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000018000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000048000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000008000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200008000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000008000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000010022",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000040022",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000000022",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200000022",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000022",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000010400",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts bus lock and split lock requests hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000040400",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000000400",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200000400",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000400",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000010008",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000040008",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000000008",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200000008",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000008",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000010004",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000040004",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000000004",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200000004",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000004",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000010001",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000040001",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000000001",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200000001",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000001",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000010002",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000040002",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000000002",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200000002",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000002",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000010800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000040800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000000800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200000800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000012000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000042000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000002000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200002000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000002000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000010010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000040010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000000010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200000010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000010",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000010020",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000040020",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000000020",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200000020",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000020",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000014800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000044800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000004800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200004800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000004800",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000011000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0000041000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x1000001000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6, 0x1a7",
"MSRValue": "0x0200001000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000001000",
- "Offcore": "1",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"SampleAfterValue": "100007",
"UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json
index 9c3d22439530..822a7a6bcaeb 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json
@@ -1,36 +1,25 @@
[
{
"BriefDescription": "Cycles the FP divide unit is busy",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.FPDIV",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts core cycles the floating point divide unit is busy.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Machine clears due to FP assists",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
"SampleAfterValue": "20003",
"UMask": "0x4"
},
{
"BriefDescription": "Floating point divide uops retired (Precise Event Capable)",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of floating point divide uops retired.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
index 4c2abfbac8f8..ace2a114b546 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
@@ -1,96 +1,64 @@
[
{
"BriefDescription": "BACLEARs asserted for any branch type",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.ALL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "BACLEARs asserted for conditional branch",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.COND",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "BACLEARs asserted for return branch",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.RETURN",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts BACLEARS on return instructions.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Decode restrictions due to predicting wrong instruction length",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE9",
"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
"SampleAfterValue": "200003",
"UMask": "0x3"
},
{
"BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "MS decode starts",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xE7",
"EventName": "MS_DECODED.MS_ENTRY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
"SampleAfterValue": "200003",
"UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
index ae0cb3451866..7038873a5c8d 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
@@ -1,36 +1,26 @@
[
{
"BriefDescription": "Machine clears due to memory ordering issue",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data.",
"SampleAfterValue": "20003",
"UMask": "0x2"
},
{
"BriefDescription": "Load uops that split a page (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Store uops that split a page (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.",
"SampleAfterValue": "200003",
"UMask": "0x4"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
index 92586fe4538a..ec0ce9078c98 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
@@ -1,59 +1,39 @@
[
{
"BriefDescription": "Cycles code-fetch stalled due to any reason.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ALL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Cycles the code-fetch stalls and an ITLB miss is outstanding.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles hardware interrupts are masked",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.MASKED",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles pending interrupts are masked",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Hardware interrupts received",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.RECEIVED",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts hardware interrupts received by the processor.",
"SampleAfterValue": "203",
"UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
index 2b712b12cc1f..33ef331e77e0 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
@@ -1,289 +1,208 @@
[
{
"BriefDescription": "Retired branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Retired taken branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of taken branch instructions retired.",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Retired near call instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CALL",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts near CALL branch instructions retired.",
"SampleAfterValue": "200003",
"UMask": "0xf9"
},
{
"BriefDescription": "Retired far branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.",
"SampleAfterValue": "200003",
"UMask": "0xbf"
},
{
"BriefDescription": "Retired near indirect call instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts near indirect CALL branch instructions retired.",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Retired conditional branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.JCC",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Retired near relative call instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts near relative CALL branch instructions retired.",
"SampleAfterValue": "200003",
"UMask": "0xfd"
},
{
"BriefDescription": "Retired near return instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.RETURN",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts near return branch instructions retired.",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Retired mispredicted branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts mispredicted branch instructions retired including all branch types.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.JCC",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Retired mispredicted near return instructions (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Core cycles when core is not halted (Fixed event)",
- "CollectPEBSRecord": "1",
- "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
- "PDIR_COUNTER": "na",
- "PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Core cycles when core is not halted",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Reference cycles when core is not halted",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Reference cycles when core is not halted (Fixed event)",
- "CollectPEBSRecord": "1",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PDIR_COUNTER": "na",
- "PEBScounters": "34",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Cycles a divider is busy",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.ALL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts core cycles if either divide unit is busy.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles the integer divide unit is busy",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.IDIV",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts core cycles the integer divide unit is busy.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Instructions retired (Fixed event)",
- "CollectPEBSRecord": "1",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
- "PDIR_COUNTER": "na",
"PEBS": "2",
- "PEBScounters": "32",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Instructions retired (Precise event capable)",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Instructions retired - using Reduced Skid PEBS feature",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "2",
@@ -292,201 +211,139 @@
},
{
"BriefDescription": "Unfilled issue slots per cycle",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Unfilled issue slots per cycle to recover",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.4K_ALIAS",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Loads blocked (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts anytime a load that retires is blocked for any reason.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Loads blocked due to store data not ready (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.UTLB_MISS",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "All machine clears",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.ALL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts machine clears for any reason.",
"SampleAfterValue": "20003"
},
{
"BriefDescription": "Machine clears due to memory disambiguation",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.",
"SampleAfterValue": "20003",
"UMask": "0x8"
},
{
"BriefDescription": "Machines clear due to a page fault",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.PAGE_FAULT",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation",
"SampleAfterValue": "20003",
"UMask": "0x20"
},
{
"BriefDescription": "Self-Modifying Code detected",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.",
"SampleAfterValue": "20003",
"UMask": "0x1"
},
{
"BriefDescription": "Uops issued to the back end per cycle",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UOPS_NOT_DELIVERED.ANY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
- "PDIR_COUNTER": "na",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts uops which retired.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Integer divide uops retired (Precise Event Capable)",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.IDIV",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of integer divide uops retired.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "MS uops retired (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MS",
- "PDIR_COUNTER": "na",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
index 1f7db22c15e6..3d6feb45a50b 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
@@ -1,219 +1,150 @@
[
{
"BriefDescription": "Page walk completed due to a demand load to a 1GB page",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Page walk completed due to a demand load to a 4K page",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Page walks outstanding due to a demand load every cycle.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 1GB page",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 4K page",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Page walks outstanding due to a demand data store every cycle.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Page walks outstanding due to walking the EPT every cycle",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "EPT.WALK_PENDING",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "ITLB misses",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "ITLB.MISS",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Page walk completed due to an instruction fetch in a 1GB page",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1GB",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Page walk completed due to an instruction fetch in a 4K page",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Page walks outstanding due to an instruction fetch every cycle.",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.",
"SampleAfterValue": "200003",
"UMask": "0x13"
},
{
"BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts load uops retired that caused a DTLB miss.",
"SampleAfterValue": "200003",
"UMask": "0x11"
},
{
"BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
"PEBS": "2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts store uops retired that caused a DTLB miss.",
"SampleAfterValue": "200003",
"UMask": "0x12"
},
{
"BriefDescription": "STLB flushes",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSHES.STLB_ANY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3.",
"SampleAfterValue": "20003",
"UMask": "0x20"
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 12/32] perf vendor events intel: Refresh haswell metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
2022-12-15 6:54 ` [PATCH v1 10/32] perf vendor events intel: Refresh goldmont events Ian Rogers
2022-12-15 6:54 ` [PATCH v1 11/32] perf vendor events intel: Refresh goldmontplus events Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 13/32] perf vendor events intel: Refresh haswellx " Ian Rogers
` (19 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the haswell metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/haswell/cache.json | 211 --------------
.../arch/x86/haswell/floating-point.json | 20 --
.../pmu-events/arch/x86/haswell/frontend.json | 58 ----
.../arch/x86/haswell/hsw-metrics.json | 117 ++++----
.../pmu-events/arch/x86/haswell/memory.json | 149 ----------
.../pmu-events/arch/x86/haswell/other.json | 8 -
.../pmu-events/arch/x86/haswell/pipeline.json | 258 ------------------
.../arch/x86/haswell/uncore-cache.json | 50 ----
.../arch/x86/haswell/uncore-other.json | 21 +-
.../arch/x86/haswell/virtual-memory.json | 98 -------
10 files changed, 73 insertions(+), 917 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf/pmu-events/arch/x86/haswell/cache.json
index 719b8e622f59..5a1489e79859 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/cache.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "L1D miss outstanding duration in cycles",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -42,8 +34,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
"SampleAfterValue": "2000003",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Not rejected writebacks that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_DEMAND_RQSTS.WB_HIT",
"PublicDescription": "Not rejected writebacks that hit L2 cache.",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
@@ -81,8 +65,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "L2 cache lines in E state filling L2.",
@@ -91,8 +73,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "L2 cache lines in I state filling L2.",
@@ -101,8 +81,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "L2 cache lines in S state filling L2.",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by demand.",
@@ -121,8 +97,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by demand.",
@@ -131,8 +105,6 @@
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts all L2 code requests.",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
@@ -152,8 +122,6 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
@@ -163,8 +131,6 @@
},
{
"BriefDescription": "Demand requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
@@ -174,8 +140,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts all L2 HW prefetcher requests.",
@@ -184,8 +148,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts all L2 store RFO requests.",
@@ -194,8 +156,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
@@ -204,8 +164,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
@@ -214,8 +172,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
@@ -225,8 +181,6 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
@@ -236,8 +190,6 @@
},
{
"BriefDescription": "L2 prefetch requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_HIT",
"PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
@@ -246,8 +198,6 @@
},
{
"BriefDescription": "L2 prefetch requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
@@ -256,8 +206,6 @@
},
{
"BriefDescription": "All requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
@@ -267,8 +215,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
@@ -278,8 +224,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
@@ -288,8 +232,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
@@ -298,8 +240,6 @@
},
{
"BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
@@ -308,8 +248,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "Transactions accessing L2 pipe.",
@@ -318,8 +256,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "L2 cache accesses when fetching instructions.",
@@ -328,8 +264,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "Demand data read requests that access L2 cache.",
@@ -338,8 +272,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "L1D writebacks that access L2 cache.",
@@ -348,8 +280,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "L2 fill requests that access L2 cache.",
@@ -358,8 +288,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "L2 writebacks that access L2 cache.",
@@ -368,8 +296,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "RFO requests that access L2 cache.",
@@ -378,8 +304,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D is locked.",
@@ -388,8 +312,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
@@ -398,8 +320,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
@@ -408,8 +328,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
@@ -420,8 +338,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
@@ -432,8 +348,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
@@ -444,8 +358,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
@@ -456,8 +368,6 @@
},
{
"BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM30",
"EventCode": "0xD3",
@@ -469,8 +379,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD1",
@@ -481,8 +389,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD1",
@@ -493,8 +399,6 @@
},
{
"BriefDescription": "Retired load uops misses in L1 cache as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD1",
@@ -506,8 +410,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD76, HSD29, HSM30",
"EventCode": "0xD1",
@@ -518,8 +420,6 @@
},
{
"BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD1",
@@ -531,8 +431,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD1",
@@ -544,8 +442,6 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD1",
@@ -557,8 +453,6 @@
},
{
"BriefDescription": "Retired load uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
@@ -570,13 +464,10 @@
},
{
"BriefDescription": "Retired store uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Counts all retired store uops.",
"SampleAfterValue": "2000003",
@@ -584,8 +475,6 @@
},
{
"BriefDescription": "Retired load uops with locked access.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD76, HSD29, HSM30",
"EventCode": "0xD0",
@@ -596,8 +485,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
@@ -608,21 +495,16 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "Retired load uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
@@ -633,21 +515,16 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x12"
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
@@ -656,8 +533,6 @@
},
{
"BriefDescription": "Cacheable and noncacheable code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Demand code read requests sent to uncore.",
@@ -666,8 +541,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
@@ -677,8 +550,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
@@ -687,8 +558,6 @@
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"SampleAfterValue": "2000003",
@@ -696,8 +565,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -707,8 +574,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
@@ -718,8 +583,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
"EventCode": "0x60",
@@ -729,8 +592,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
@@ -740,8 +601,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@@ -751,8 +610,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@@ -762,8 +619,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
"EventCode": "0x60",
@@ -773,8 +628,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@@ -784,8 +637,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
@@ -793,248 +644,186 @@
},
{
"BriefDescription": "Counts all demand & prefetch code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requestshit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C8FFF",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code readshit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data readshit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOshit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code readshit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data readshit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOshit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json
index 7cf203a90a74..8fcc10f74ad9 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC6",
"EventName": "AVX_INSTS.ALL",
"PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "Number of X87 FP assists due to input values.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "Number of X87 FP assists due to output values.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD56, HSM57",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD56, HSM57",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/frontend.json b/tools/perf/pmu-events/arch/x86/haswell/frontend.json
index 18a993297108..73d6d681dfa7 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"SampleAfterValue": "2000003",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFETCH_STALL",
"SampleAfterValue": "2000003",
@@ -47,8 +37,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",
@@ -57,8 +45,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -68,8 +54,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -79,8 +63,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -90,8 +72,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -101,8 +81,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -121,8 +97,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD135",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
@@ -132,8 +106,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -142,8 +114,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -152,8 +122,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -162,8 +130,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -173,8 +139,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -183,8 +147,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -194,8 +156,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -204,8 +164,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -214,8 +172,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -225,8 +181,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
@@ -235,8 +189,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD135",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
@@ -246,8 +198,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"Errata": "HSD135",
"EventCode": "0x9C",
@@ -258,8 +208,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD135",
"EventCode": "0x9C",
@@ -270,8 +218,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"Errata": "HSD135",
"EventCode": "0x9C",
@@ -281,8 +227,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"Errata": "HSD135",
"EventCode": "0x9C",
@@ -292,8 +236,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD135",
"EventCode": "0x9C",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json
index 6cb6603efbd8..2e032beee542 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json
@@ -88,7 +88,7 @@
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -96,7 +96,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -120,7 +120,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+ "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB))) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -152,7 +152,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+ "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
@@ -192,7 +192,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -200,7 +200,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
+ "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -208,7 +208,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+ "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -216,7 +216,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+ "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -224,7 +224,7 @@
},
{
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_sq_full",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -232,7 +232,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -264,7 +264,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -312,7 +312,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
+ "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -320,7 +320,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0",
"PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@@ -328,7 +328,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_1",
"PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
@@ -336,7 +336,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_2",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
@@ -344,14 +344,14 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
- "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m",
"ScaleUnit": "100%"
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_alu_op_utilization",
"ScaleUnit": "100%"
@@ -407,7 +407,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricExpr": "tma_port_4",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_store_op_utilization",
"ScaleUnit": "100%"
@@ -460,7 +460,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -526,13 +526,13 @@
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)) if #SMT_on else UOPS_EXECUTED.CORE / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)",
+ "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@))",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
@@ -586,7 +586,7 @@
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
@@ -598,7 +598,7 @@
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
"MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency"
},
@@ -610,19 +610,19 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
@@ -635,19 +635,19 @@
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
@@ -677,13 +677,13 @@
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
@@ -695,7 +695,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@@ -713,68 +713,87 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+ "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+ "MetricExpr": "MEM_Parallel_Requests",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Request_Latency"
},
{
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+ "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests"
},
+ {
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "UNC_CLOCK.SOCKET",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
+ },
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
+ {
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
+ },
{
"BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/haswell/memory.json b/tools/perf/pmu-events/arch/x86/haswell/memory.json
index 9e5a1e0966d9..9fb63e1dab08 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"SampleAfterValue": "2000003",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"SampleAfterValue": "2000003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD65",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
@@ -48,8 +38,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).",
@@ -58,8 +46,6 @@
},
{
"BriefDescription": "Number of times an HLE execution successfully committed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"SampleAfterValue": "2000003",
@@ -67,8 +53,6 @@
},
{
"BriefDescription": "Number of times an HLE execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.START",
"SampleAfterValue": "2000003",
@@ -76,8 +60,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -86,8 +68,6 @@
},
{
"BriefDescription": "Randomly selected loads with latency value being above 128.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -96,13 +76,10 @@
"MSRValue": "0x80",
"PEBS": "2",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 16.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -111,13 +88,10 @@
"MSRValue": "0x10",
"PEBS": "2",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 256.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -126,13 +100,10 @@
"MSRValue": "0x100",
"PEBS": "2",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 32.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -141,13 +112,10 @@
"MSRValue": "0x20",
"PEBS": "2",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 4.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -156,13 +124,10 @@
"MSRValue": "0x4",
"PEBS": "2",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 512.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -171,13 +136,10 @@
"MSRValue": "0x200",
"PEBS": "2",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 64.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -186,13 +148,10 @@
"MSRValue": "0x40",
"PEBS": "2",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 8.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -201,13 +160,10 @@
"MSRValue": "0x8",
"PEBS": "2",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
@@ -216,8 +172,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.",
@@ -226,260 +180,195 @@
},
{
"BriefDescription": "Counts all demand & prefetch code readsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch code readsmiss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data readsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data readsmiss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requestsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC08FFF",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOsmiss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code readsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code readsmiss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data readsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data readsmiss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code readsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data readsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code readsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data readsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOsmiss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -488,8 +377,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -498,8 +385,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"SampleAfterValue": "2000003",
@@ -507,8 +392,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"SampleAfterValue": "2000003",
@@ -516,8 +399,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD65",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
@@ -526,8 +407,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -536,8 +415,6 @@
},
{
"BriefDescription": "Number of times an RTM execution successfully committed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"SampleAfterValue": "2000003",
@@ -545,8 +422,6 @@
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.START",
"SampleAfterValue": "2000003",
@@ -554,8 +429,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@@ -563,8 +436,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"SampleAfterValue": "2000003",
@@ -572,8 +443,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"SampleAfterValue": "2000003",
@@ -581,8 +450,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"SampleAfterValue": "2000003",
@@ -590,8 +457,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003",
@@ -599,8 +464,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"SampleAfterValue": "2000003",
@@ -608,8 +471,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"SampleAfterValue": "2000003",
@@ -617,8 +478,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"SampleAfterValue": "2000003",
@@ -626,8 +485,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"SampleAfterValue": "2000003",
@@ -635,8 +492,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"SampleAfterValue": "2000003",
@@ -644,8 +499,6 @@
},
{
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"SampleAfterValue": "2000003",
@@ -653,8 +506,6 @@
},
{
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/other.json b/tools/perf/pmu-events/arch/x86/haswell/other.json
index 7ca34f09b185..2395ebf112db 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/other.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json
index 42f6a8100661..9ac36c1c24b6 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_UOPS",
"SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Speculative and retired branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"SampleAfterValue": "200003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -47,8 +37,6 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -56,8 +44,6 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -65,8 +51,6 @@
},
{
"BriefDescription": "Not taken macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -74,8 +58,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -83,8 +65,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"SampleAfterValue": "200003",
@@ -92,8 +72,6 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -101,8 +79,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -110,8 +86,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -119,8 +93,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -128,8 +100,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "Branch instructions at retirement.",
@@ -137,8 +107,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -147,8 +115,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -158,8 +124,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PublicDescription": "Number of far branches retired.",
@@ -168,8 +132,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -178,8 +140,6 @@
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
@@ -188,8 +148,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -199,8 +157,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -210,8 +166,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "Counts the number of not taken branch instructions retired.",
@@ -220,8 +174,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -230,8 +182,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -239,8 +189,6 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -248,8 +196,6 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -257,8 +203,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -266,8 +210,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -275,8 +217,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -284,8 +224,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"SampleAfterValue": "200003",
@@ -293,8 +231,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Mispredicted branch instructions at retirement.",
@@ -302,8 +238,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -313,8 +247,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -323,8 +255,6 @@
},
{
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -334,8 +264,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003",
@@ -343,8 +271,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
@@ -354,8 +280,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
@@ -364,8 +288,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003",
@@ -373,8 +295,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.",
"SampleAfterValue": "2000003",
@@ -382,8 +302,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
@@ -393,8 +311,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
@@ -403,8 +319,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
"SampleAfterValue": "2000003",
@@ -413,16 +327,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
@@ -431,16 +341,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles with pending L1 cache miss loads.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -450,8 +356,6 @@
},
{
"BriefDescription": "Cycles with pending L2 cache miss loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD78, HSM63, HSM80",
"EventCode": "0xa3",
@@ -462,8 +366,6 @@
},
{
"BriefDescription": "Cycles with pending memory loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -473,8 +375,6 @@
},
{
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -484,8 +384,6 @@
},
{
"BriefDescription": "Execution stalls due to L1 data cache misses",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -495,8 +393,6 @@
},
{
"BriefDescription": "Execution stalls due to L2 cache misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"Errata": "HSM63, HSM80",
"EventCode": "0xa3",
@@ -507,8 +403,6 @@
},
{
"BriefDescription": "Execution stalls due to memory subsystem.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -518,8 +412,6 @@
},
{
"BriefDescription": "Stall cycles because IQ is full",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"PublicDescription": "Stall cycles due to IQ is full.",
@@ -528,8 +420,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).",
@@ -538,8 +428,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"Errata": "HSD140, HSD143",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
@@ -548,8 +436,6 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD11, HSD140",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
@@ -558,8 +444,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"Errata": "HSD140",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
@@ -570,8 +454,6 @@
},
{
"BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
@@ -580,8 +462,6 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -592,8 +472,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -603,8 +481,6 @@
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -613,8 +489,6 @@
},
{
"BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.",
@@ -623,8 +497,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.",
@@ -633,8 +505,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
@@ -643,8 +513,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
@@ -653,8 +521,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -663,8 +529,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -673,8 +537,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
"PublicDescription": "Number of uops delivered by the LSD.",
@@ -683,8 +545,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -694,8 +554,6 @@
},
{
"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "2000003",
@@ -703,8 +561,6 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"SampleAfterValue": "100003",
@@ -712,8 +568,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -722,8 +576,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"PublicDescription": "Number of integer move elimination candidate uops that were eliminated.",
@@ -732,8 +584,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.",
@@ -742,8 +592,6 @@
},
{
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.",
@@ -752,8 +600,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD135",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
@@ -763,8 +609,6 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
@@ -772,8 +616,6 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
@@ -781,8 +623,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.",
@@ -791,8 +631,6 @@
},
{
"BriefDescription": "Count cases of saving new LBR",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Count cases of saving new LBR records by hardware.",
@@ -801,8 +639,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.",
@@ -811,8 +647,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -823,8 +657,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"SampleAfterValue": "2000003",
@@ -832,8 +664,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"SampleAfterValue": "2000003",
@@ -841,8 +671,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue": "2000003",
@@ -850,8 +678,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue": "2000003",
@@ -859,8 +685,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue": "2000003",
@@ -868,8 +692,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue": "2000003",
@@ -877,8 +699,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"SampleAfterValue": "2000003",
@@ -886,8 +706,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"SampleAfterValue": "2000003",
@@ -895,8 +713,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD30, HSM31",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
@@ -906,8 +722,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
@@ -917,8 +731,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
@@ -928,8 +740,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
@@ -939,8 +749,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
@@ -950,8 +758,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -961,8 +767,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -973,8 +777,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -985,8 +787,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -997,8 +797,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -1008,8 +806,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -1020,8 +816,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0",
"PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.",
@@ -1031,8 +825,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
@@ -1040,8 +832,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1",
"PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.",
@@ -1051,8 +841,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
@@ -1060,8 +848,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2",
"PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.",
@@ -1071,8 +857,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -1080,8 +864,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3",
"PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.",
@@ -1091,8 +873,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
@@ -1100,8 +880,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4",
"PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.",
@@ -1111,8 +889,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
@@ -1120,8 +896,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5",
"PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.",
@@ -1131,8 +905,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
@@ -1140,8 +912,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6",
"PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.",
@@ -1151,8 +921,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 6.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003",
@@ -1160,8 +928,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7",
"PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.",
@@ -1171,8 +937,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 7.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue": "2000003",
@@ -1180,8 +944,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.",
@@ -1191,8 +953,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1202,8 +962,6 @@
},
{
"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.",
@@ -1212,8 +970,6 @@
},
{
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL",
"PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
@@ -1222,8 +978,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.",
@@ -1232,8 +986,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1243,8 +995,6 @@
},
{
"BriefDescription": "Actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@@ -1255,8 +1005,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1266,8 +1014,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -1277,8 +1023,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1288,8 +1032,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json
index 6b0639944d78..c538557ba4c0 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json
@@ -1,251 +1,201 @@
[
{
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"UMask": "0x86",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"UMask": "0x8f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"UMask": "0x46",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"UMask": "0x41",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"UMask": "0x4f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"UMask": "0x16",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"UMask": "0x18",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
"UMask": "0x11",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"UMask": "0x1f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"UMask": "0x26",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"UMask": "0x2f",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"PerPkg": "1",
- "PublicDescription": "An external snoop hits a modified line in some processor core.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"UMask": "0x84",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"PerPkg": "1",
- "PublicDescription": "An external snoop hits a non-modified line in some processor core.",
"UMask": "0x24",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"UMask": "0x44",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"PerPkg": "1",
- "PublicDescription": "An external snoop misses in some processor core.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"UMask": "0x41",
"Unit": "CBO"
}
diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json
index 56c4b380dc95..84cc2536de69 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json
@@ -5,17 +5,15 @@
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All",
"PerPkg": "1",
"PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
- "Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
- "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
@@ -23,48 +21,39 @@
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "Counter": "0,",
"CounterMask": "1",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
- "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.\n",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
- "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
- "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"UMask": "0x20",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
- "Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",
- "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Unit": "CLOCK"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json
index 57d2a6452fec..87a4ec1ee7d7 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Number of cache load STLB hits. No page walk.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "2000003",
@@ -70,8 +56,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
@@ -80,8 +64,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
@@ -90,8 +72,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
@@ -100,8 +80,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
@@ -110,8 +88,6 @@
},
{
"BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
"PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
@@ -120,8 +96,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
@@ -130,8 +104,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -140,8 +112,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -150,8 +120,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
@@ -160,8 +128,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "100003",
@@ -169,8 +135,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
@@ -179,8 +143,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
@@ -189,8 +151,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
@@ -199,8 +159,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4f",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
@@ -208,8 +166,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xae",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
@@ -218,8 +174,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
@@ -228,8 +182,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "ITLB misses that hit STLB. No page walk.",
@@ -238,8 +190,6 @@
},
{
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"PublicDescription": "ITLB misses that hit STLB (2M).",
@@ -248,8 +198,6 @@
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"PublicDescription": "ITLB misses that hit STLB (4K).",
@@ -258,8 +206,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in ITLB of any page size.",
@@ -268,8 +214,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "100003",
@@ -277,8 +221,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
@@ -287,8 +229,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
@@ -297,8 +237,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.",
@@ -307,8 +245,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L1+FB",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
"PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
@@ -317,8 +253,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
"PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
@@ -327,8 +261,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@@ -338,8 +270,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in Memory",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@@ -349,8 +279,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
"SampleAfterValue": "2000003",
@@ -358,8 +286,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
"SampleAfterValue": "2000003",
@@ -367,8 +293,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
"SampleAfterValue": "2000003",
@@ -376,8 +300,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
"SampleAfterValue": "2000003",
@@ -385,8 +307,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
"SampleAfterValue": "2000003",
@@ -394,8 +314,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
"SampleAfterValue": "2000003",
@@ -403,8 +321,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
"SampleAfterValue": "2000003",
@@ -412,8 +328,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
"SampleAfterValue": "2000003",
@@ -421,8 +335,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L1+FB",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
"PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
@@ -431,8 +343,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
"PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
@@ -441,8 +351,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@@ -452,8 +360,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in Memory",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
@@ -463,8 +369,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "DTLB flush attempts of the thread-specific entries.",
@@ -473,8 +377,6 @@
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Count number of STLB flush attempts.",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 13/32] perf vendor events intel: Refresh haswellx metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (2 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 12/32] perf vendor events intel: Refresh haswell metrics and events Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 14/32] perf vendor events intel: Refresh icelake " Ian Rogers
` (18 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the haswellx metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. The formatting
changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/haswellx/cache.json | 217 --
.../arch/x86/haswellx/floating-point.json | 20 -
.../arch/x86/haswellx/frontend.json | 58 -
.../arch/x86/haswellx/hsx-metrics.json | 1467 +++++-----
.../pmu-events/arch/x86/haswellx/memory.json | 170 --
.../pmu-events/arch/x86/haswellx/other.json | 8 -
.../arch/x86/haswellx/pipeline.json | 258 --
.../arch/x86/haswellx/uncore-cache.json | 2448 ++++++++---------
.../x86/haswellx/uncore-interconnect.json | 722 ++---
.../arch/x86/haswellx/uncore-memory.json | 2037 +++++++-------
.../arch/x86/haswellx/uncore-other.json | 1834 ++++++------
.../arch/x86/haswellx/uncore-power.json | 150 +-
.../arch/x86/haswellx/virtual-memory.json | 98 -
13 files changed, 4206 insertions(+), 5281 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/cache.json b/tools/perf/pmu-events/arch/x86/haswellx/cache.json
index 427c949bed6e..1836ed62694e 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/cache.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "L1D miss outstanding duration in cycles",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -42,8 +34,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
"SampleAfterValue": "2000003",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Not rejected writebacks that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_DEMAND_RQSTS.WB_HIT",
"PublicDescription": "Not rejected writebacks that hit L2 cache.",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
@@ -81,8 +65,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "L2 cache lines in E state filling L2.",
@@ -91,8 +73,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "L2 cache lines in I state filling L2.",
@@ -101,8 +81,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "L2 cache lines in S state filling L2.",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by demand.",
@@ -121,8 +97,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by demand.",
@@ -131,8 +105,6 @@
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts all L2 code requests.",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
@@ -152,8 +122,6 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
@@ -163,8 +131,6 @@
},
{
"BriefDescription": "Demand requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
@@ -174,8 +140,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts all L2 HW prefetcher requests.",
@@ -184,8 +148,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts all L2 store RFO requests.",
@@ -194,8 +156,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
@@ -204,8 +164,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
@@ -214,8 +172,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
@@ -225,8 +181,6 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
@@ -236,8 +190,6 @@
},
{
"BriefDescription": "L2 prefetch requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_HIT",
"PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
@@ -246,8 +198,6 @@
},
{
"BriefDescription": "L2 prefetch requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
@@ -256,8 +206,6 @@
},
{
"BriefDescription": "All requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
@@ -267,8 +215,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
@@ -278,8 +224,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
@@ -288,8 +232,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
@@ -298,8 +240,6 @@
},
{
"BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
@@ -308,8 +248,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "Transactions accessing L2 pipe.",
@@ -318,8 +256,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "L2 cache accesses when fetching instructions.",
@@ -328,8 +264,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "Demand data read requests that access L2 cache.",
@@ -338,8 +272,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "L1D writebacks that access L2 cache.",
@@ -348,8 +280,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "L2 fill requests that access L2 cache.",
@@ -358,8 +288,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "L2 writebacks that access L2 cache.",
@@ -368,8 +296,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "RFO requests that access L2 cache.",
@@ -378,8 +304,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D is locked.",
@@ -388,8 +312,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
@@ -398,8 +320,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
@@ -408,8 +328,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
@@ -420,8 +338,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
@@ -432,8 +348,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
@@ -444,8 +358,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
@@ -456,8 +368,6 @@
},
{
"BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM30",
"EventCode": "0xD3",
@@ -469,8 +379,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD3",
@@ -481,8 +389,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD3",
@@ -493,8 +399,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD3",
@@ -505,8 +409,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD1",
@@ -517,8 +419,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD1",
@@ -529,8 +429,6 @@
},
{
"BriefDescription": "Retired load uops misses in L1 cache as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD1",
@@ -542,8 +440,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD76, HSD29, HSM30",
"EventCode": "0xD1",
@@ -554,8 +450,6 @@
},
{
"BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD1",
@@ -567,8 +461,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD1",
@@ -580,8 +472,6 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD1",
@@ -593,8 +483,6 @@
},
{
"BriefDescription": "Retired load uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
@@ -606,13 +494,10 @@
},
{
"BriefDescription": "Retired store uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Counts all retired store uops.",
"SampleAfterValue": "2000003",
@@ -620,8 +505,6 @@
},
{
"BriefDescription": "Retired load uops with locked access.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD76, HSD29, HSM30",
"EventCode": "0xD0",
@@ -632,8 +515,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
@@ -644,21 +525,16 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "Retired load uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
@@ -669,21 +545,16 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x12"
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
@@ -692,8 +563,6 @@
},
{
"BriefDescription": "Cacheable and noncacheable code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Demand code read requests sent to uncore.",
@@ -702,8 +571,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
@@ -713,8 +580,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
@@ -723,8 +588,6 @@
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"SampleAfterValue": "2000003",
@@ -732,8 +595,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -743,8 +604,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
@@ -754,8 +613,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
"EventCode": "0x60",
@@ -765,8 +622,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
@@ -776,8 +631,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@@ -787,8 +640,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@@ -798,8 +649,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
"EventCode": "0x60",
@@ -809,8 +658,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@@ -820,8 +667,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
@@ -829,248 +674,186 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requests hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C8FFF",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json
index 7cf203a90a74..8fcc10f74ad9 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC6",
"EventName": "AVX_INSTS.ALL",
"PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "Number of X87 FP assists due to input values.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "Number of X87 FP assists due to output values.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD56, HSM57",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD56, HSM57",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json
index 18a993297108..73d6d681dfa7 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"SampleAfterValue": "2000003",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFETCH_STALL",
"SampleAfterValue": "2000003",
@@ -47,8 +37,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",
@@ -57,8 +45,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -68,8 +54,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -79,8 +63,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -90,8 +72,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -101,8 +81,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -121,8 +97,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD135",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
@@ -132,8 +106,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -142,8 +114,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -152,8 +122,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -162,8 +130,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -173,8 +139,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -183,8 +147,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -194,8 +156,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -204,8 +164,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -214,8 +172,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -225,8 +181,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
@@ -235,8 +189,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD135",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
@@ -246,8 +198,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"Errata": "HSD135",
"EventCode": "0x9C",
@@ -258,8 +208,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD135",
"EventCode": "0x9C",
@@ -270,8 +218,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"Errata": "HSD135",
"EventCode": "0x9C",
@@ -281,8 +227,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"Errata": "HSD135",
"EventCode": "0x9C",
@@ -292,8 +236,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD135",
"EventCode": "0x9C",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
index 2cd86750986a..2e1fbc936d25 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
@@ -1,1040 +1,1023 @@
[
{
- "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
- "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
- "MetricGroup": "PGO;TopdownL1;tma_L1_group",
- "MetricName": "tma_frontend_bound",
- "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+ "MetricExpr": "INST_RETIRED.ANY / CLKS",
+ "MetricGroup": "Ret;Summary",
+ "MetricName": "IPC"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
- "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS",
- "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_latency",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uops Per Instruction",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "UPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
- "MetricExpr": "ICACHE.IFDATA_STALL / CLKS",
- "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_icache_misses",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW",
+ "MetricName": "UpTB"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
- "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CLKS",
- "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_itlb_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+ "MetricExpr": "1 / IPC",
+ "MetricGroup": "Mem;Pipeline",
+ "MetricName": "CPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
- "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_branch_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "Pipeline",
+ "MetricName": "CLKS"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
- "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_dsb_switches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+ "MetricExpr": "4 * CORE_CLKS",
+ "MetricGroup": "tma_L1_group",
+ "MetricName": "SLOTS"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
- "MetricExpr": "ILD_STALL.LCP / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_lcp",
- "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+ "MetricGroup": "Ret;SMT;tma_L1_group",
+ "MetricName": "CoreIPC"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
- "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS",
- "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_ms_switches",
- "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+ "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@))",
+ "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+ "MetricName": "ILP"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
- "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
- "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_bandwidth",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
+ "MetricGroup": "SMT",
+ "MetricName": "CORE_CLKS"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
- "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_mite",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
+ "MetricGroup": "InsType",
+ "MetricName": "IpLoad"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
- "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_dsb",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
+ "MetricGroup": "InsType",
+ "MetricName": "IpStore"
},
{
- "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_bad_speculation",
- "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Fed;InsType",
+ "MetricName": "IpBranch"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_branch_mispredicts",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "IpCall"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
- "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
- "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_machine_clears",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+ "MetricName": "IpTB"
},
{
- "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_backend_bound",
- "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch instructions per taken branch. ",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "BpTkBranch"
},
{
- "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
- "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_memory_bound",
- "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+ "MetricExpr": "INST_RETIRED.ANY",
+ "MetricGroup": "Summary;tma_L1_group",
+ "MetricName": "Instructions"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
- "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CLKS, 0)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l1_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "Retire"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
- "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_dtlb_load",
- "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+ "MetricGroup": "DSB;Fed;FetchBW",
+ "MetricName": "DSB_Coverage"
},
{
- "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
- "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_store_fwd_blk",
- "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "IpMispredict"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
- "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_lock_latency",
- "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
+ "MetricGroup": "Mem;MemoryBound;MemoryLat",
+ "MetricName": "Load_Miss_Real_Latency"
},
{
- "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
- "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_split_loads",
- "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+ "MetricGroup": "Mem;MemoryBW;MemoryBound",
+ "MetricName": "MLP"
},
{
- "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
- "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_4k_aliasing",
- "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI"
},
{
- "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
- "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=1@ / CLKS",
- "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_fb_full",
- "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Backend;CacheMisses;Mem",
+ "MetricName": "L2MPKI"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l2_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L3MPKI"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l3_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+ "MetricConstraint": "NO_NMI_WATCHDOG",
+ "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "Page_Walks_Utilization"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_contested_accesses",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_data_sharing",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_l3_hit_latency",
- "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_sq_full",
- "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "L1D_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_dram_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "L2_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_bandwidth",
- "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_latency",
- "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "0",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW_1T"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
- "MetricExpr": "200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_local_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average CPU Utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricGroup": "HPC;Summary",
+ "MetricName": "CPU_Utilization"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
- "MetricExpr": "310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+ "MetricGroup": "Power;Summary",
+ "MetricName": "Average_Frequency"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
- "MetricExpr": "(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
- "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_cache",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+ "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricGroup": "Power",
+ "MetricName": "Turbo_Utilization"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
- "MetricExpr": "RESOURCE_STALLS.SB / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_store_bound",
- "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
+ "MetricGroup": "SMT",
+ "MetricName": "SMT_2T_Utilization"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_store_latency",
- "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_Utilization"
},
{
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_CPI"
},
{
- "BriefDescription": "This metric represents rate of split store accesses",
- "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
- "MetricGroup": "TopdownL4;tma_store_bound_group",
- "MetricName": "tma_split_stores",
- "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "DRAM_BW_Use"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
- "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_dtlb_store",
- "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
},
{
- "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
- "MetricExpr": "tma_backend_bound - tma_memory_bound",
- "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_core_bound",
- "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
- "MetricExpr": "10 * ARITH.DIVIDER_UOPS / CORE_CLKS",
- "MetricGroup": "TopdownL3;tma_core_bound_group",
- "MetricName": "tma_divider",
- "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "cbox_0@event\\=0x0@",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
- "MetricName": "tma_ports_utilization",
- "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+ "MetricGroup": "Branches;OS",
+ "MetricName": "IpFarBranch"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_0",
- "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_1",
- "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
- "ScaleUnit": "100%"
+ "BriefDescription": "CPU operating frequency (in GHz)",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+ "MetricName": "cpu_operating_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_2",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+ "MetricName": "cpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
- "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_3m",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+ "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+ "MetricName": "loads_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_alu_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+ "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+ "MetricName": "stores_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
- "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_0",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+ "MetricName": "l1d_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_1",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
+ "MetricName": "l1d_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_5",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+ "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_6",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_load_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+ "MetricName": "l2_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_2",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_3",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_code_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_store_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
+ "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_4",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
+ "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_7",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
+ "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_retiring",
- "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "itlb_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
- "MetricExpr": "tma_retiring - tma_heavy_operations",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_light_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "itlb_large_page_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
- "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_x87_use",
- "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
- "MetricExpr": "tma_microcode_sequencer",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_heavy_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_store_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
- "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_microcode_sequencer",
- "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uncore operating frequency in GHz",
+ "MetricExpr": "UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time",
+ "MetricName": "uncore_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
- "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_assists",
- "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
+ "MetricExpr": "UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time",
+ "MetricName": "qpi_data_transmit_bw",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
- "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_cisc",
- "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
- "ScaleUnit": "100%"
+ "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
- "MetricExpr": "INST_RETIRED.ANY / CLKS",
- "MetricGroup": "Ret;Summary",
- "MetricName": "IPC"
+ "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Uops Per Instruction",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;Ret;Retire",
- "MetricName": "UPI"
+ "BriefDescription": "DDR memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW",
- "MetricName": "UpTB"
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_writes",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
- "MetricExpr": "1 / IPC",
- "MetricGroup": "Mem;Pipeline",
- "MetricName": "CPI"
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_reads",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "Pipeline",
- "MetricName": "CLKS"
+ "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_decoded_icache",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
- "MetricExpr": "4 * CORE_CLKS",
- "MetricGroup": "tma_L1_group",
- "MetricName": "SLOTS"
+ "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
- "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
- "MetricGroup": "Ret;SMT;tma_L1_group",
- "MetricName": "CoreIPC"
+ "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)) if #SMT_on else UOPS_EXECUTED.CORE / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)",
- "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
- "MetricName": "ILP"
+ "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "(UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS) / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_loop_stream_detector",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
- "MetricGroup": "SMT",
- "MetricName": "CORE_CLKS"
+ "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@) / INST_RETIRED.ANY",
+ "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
- "MetricGroup": "InsType",
- "MetricName": "IpLoad"
+ "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@) / INST_RETIRED.ANY",
+ "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
- "MetricGroup": "InsType",
- "MetricName": "IpStore"
+ "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+ "MetricName": "numa_reads_addressed_to_local_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Branches;Fed;InsType",
- "MetricName": "IpBranch"
+ "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+ "MetricName": "numa_reads_addressed_to_remote_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "IpCall"
+ "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+ "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
+ "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_frontend_bound",
+ "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
- "MetricName": "IpTB"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+ "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS",
+ "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_latency",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Branch instructions per taken branch. ",
- "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "BpTkBranch"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+ "MetricExpr": "ICACHE.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_icache_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
- "MetricExpr": "INST_RETIRED.ANY",
- "MetricGroup": "Summary;tma_L1_group",
- "MetricName": "Instructions"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+ "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_itlb_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
- "MetricGroup": "Pipeline;Ret",
- "MetricName": "Retire"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+ "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_branch_resteers",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
- "MetricGroup": "DSB;Fed;FetchBW",
- "MetricName": "DSB_Coverage"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_dsb_switches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "IpMispredict"
+ "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+ "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_lcp",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
- "MetricGroup": "Mem;MemoryBound;MemoryLat",
- "MetricName": "Load_Miss_Real_Latency"
+ "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+ "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_ms_switches",
+ "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
- "MetricGroup": "Mem;MemoryBW;MemoryBound",
- "MetricName": "MLP"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+ "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
+ "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_bandwidth",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+ "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_mite",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "Backend;CacheMisses;Mem",
- "MetricName": "L2MPKI"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+ "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_dsb",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L3MPKI"
+ "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_bad_speculation",
+ "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
- "MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "Page_Walks_Utilization"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_branch_mispredicts",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+ "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_machine_clears",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW"
+ "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+ "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + UOPS_RETIRED.RETIRE_SLOTS / SLOTS)",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_backend_bound",
+ "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+ "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound",
+ "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_memory_bound",
+ "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "L1D_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+ "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CPU_CLK_UNHALTED.THREAD, 0)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l1_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "L2_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+ "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_dtlb_load",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+ "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_store_fwd_blk",
+ "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "0",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW_1T"
+ "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+ "MetricExpr": "min(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_lock_latency",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
- "MetricGroup": "HPC;Summary",
- "MetricName": "CPU_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+ "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_split_loads",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
- "MetricGroup": "Power;Summary",
- "MetricName": "Average_Frequency"
+ "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+ "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_4k_aliasing",
+ "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average Frequency Utilization relative nominal frequency",
- "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
- "MetricGroup": "Power",
- "MetricName": "Turbo_Utilization"
+ "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+ "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_fb_full",
+ "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
- "MetricGroup": "SMT",
- "MetricName": "SMT_2T_Utilization"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l2_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "OS",
- "MetricName": "Kernel_Utilization"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l3_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
- "MetricGroup": "OS",
- "MetricName": "Kernel_CPI"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+ "MetricExpr": "min((60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_contested_accesses",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC",
- "MetricName": "DRAM_BW_Use"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+ "MetricExpr": "min(43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_data_sharing",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "1000000000 * (cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
- "MetricGroup": "Mem;MemoryLat;SoC",
- "MetricName": "MEM_Read_Latency"
+ "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+ "MetricExpr": "min(41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_l3_hit_latency",
+ "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@",
- "MetricGroup": "Mem;MemoryBW;SoC",
- "MetricName": "MEM_Parallel_Reads"
+ "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_sq_full",
+ "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Socket actual clocks when any core is active on that socket",
- "MetricExpr": "cbox_0@event\\=0x0@",
- "MetricGroup": "SoC",
- "MetricName": "Socket_CLKS"
+ "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+ "MetricExpr": "min((1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_dram_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
- "MetricGroup": "Branches;OS",
- "MetricName": "IpFarBranch"
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x6@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_bandwidth",
+ "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_latency",
+ "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+ "MetricExpr": "min(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_local_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+ "MetricExpr": "min(310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+ "MetricExpr": "min((200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_cache",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+ "MetricExpr": "RESOURCE_STALLS.SB / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_store_bound",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_store_latency",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+ "MetricExpr": "min((200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_false_sharing",
+ "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "BriefDescription": "This metric represents rate of split store accesses",
+ "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_split_stores",
+ "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "CPU operating frequency (in GHz)",
- "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "cpu_operating_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+ "MetricExpr": "min((8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_dtlb_store",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
- "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "loads_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+ "MetricExpr": "tma_backend_bound - tma_memory_bound",
+ "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_core_bound",
+ "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
- "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "stores_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+ "MetricExpr": "10 * ARITH.DIVIDER_UOPS / CORE_CLKS",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_divider",
+ "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+ "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_ports_utilization",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ / 2 if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_0",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_1",
+ "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_2",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_3m",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_alu_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_code_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
+ "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_0",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
- "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_1",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_5",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_6",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_load_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_large_page_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_2",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_3",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_store_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_store_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore operating frequency in GHz",
- "MetricExpr": "( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "uncore_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
+ "MetricExpr": "tma_store_op_utilization",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_4",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
- "MetricExpr": "( UNC_Q_TxL_FLITS_G0.DATA * 8 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "qpi_data_transmit_bw",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_7",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_retiring",
+ "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+ "MetricExpr": "tma_retiring - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_light_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+ "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_x87_use",
+ "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_writes",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_heavy_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_reads",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+ "MetricExpr": "tma_heavy_operations",
+ "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_microcode_sequencer",
+ "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_decoded_icache",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+ "MetricExpr": "min(100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_assists",
+ "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+ "MetricExpr": "max(0, tma_heavy_operations - tma_assists)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_cisc",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_microcode_sequencer",
- "ScaleUnit": "1%"
+ "BriefDescription": "C3 residency percent per core",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS ) / UOPS_ISSUED.ANY",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_loop_stream_detector",
- "ScaleUnit": "1%"
+ "BriefDescription": "C6 residency percent per core",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@ ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "C7 residency percent per core",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@ ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "C2 residency percent per package",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_local_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "C3 residency percent per package",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_remote_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "C6 residency percent per package",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "C7 residency percent per package",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/memory.json b/tools/perf/pmu-events/arch/x86/haswellx/memory.json
index fdabc9fe12a5..2d212cf59e92 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"SampleAfterValue": "2000003",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"SampleAfterValue": "2000003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD65",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
@@ -48,8 +38,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).",
@@ -58,8 +46,6 @@
},
{
"BriefDescription": "Number of times an HLE execution successfully committed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"SampleAfterValue": "2000003",
@@ -67,8 +53,6 @@
},
{
"BriefDescription": "Number of times an HLE execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.START",
"SampleAfterValue": "2000003",
@@ -76,8 +60,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -86,8 +68,6 @@
},
{
"BriefDescription": "Randomly selected loads with latency value being above 128.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -96,13 +76,10 @@
"MSRValue": "0x80",
"PEBS": "2",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 16.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -111,13 +88,10 @@
"MSRValue": "0x10",
"PEBS": "2",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 256.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -126,13 +100,10 @@
"MSRValue": "0x100",
"PEBS": "2",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 32.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -141,13 +112,10 @@
"MSRValue": "0x20",
"PEBS": "2",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 4.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -156,13 +124,10 @@
"MSRValue": "0x4",
"PEBS": "2",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 512.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -171,13 +136,10 @@
"MSRValue": "0x200",
"PEBS": "2",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 64.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -186,13 +148,10 @@
"MSRValue": "0x40",
"PEBS": "2",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 8.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
@@ -201,13 +160,10 @@
"MSRValue": "0x8",
"PEBS": "2",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
@@ -216,8 +172,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.",
@@ -226,344 +180,258 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63F800091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6004007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63F8007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requests miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08FFF",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -572,8 +440,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -582,8 +448,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"SampleAfterValue": "2000003",
@@ -591,8 +455,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"SampleAfterValue": "2000003",
@@ -600,8 +462,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD65",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
@@ -610,8 +470,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -620,8 +478,6 @@
},
{
"BriefDescription": "Number of times an RTM execution successfully committed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"SampleAfterValue": "2000003",
@@ -629,8 +485,6 @@
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.START",
"SampleAfterValue": "2000003",
@@ -638,8 +492,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@@ -647,8 +499,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"SampleAfterValue": "2000003",
@@ -656,8 +506,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"SampleAfterValue": "2000003",
@@ -665,8 +513,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"SampleAfterValue": "2000003",
@@ -674,8 +520,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003",
@@ -683,8 +527,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"SampleAfterValue": "2000003",
@@ -692,8 +534,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"SampleAfterValue": "2000003",
@@ -701,8 +541,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"SampleAfterValue": "2000003",
@@ -710,8 +548,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"SampleAfterValue": "2000003",
@@ -719,8 +555,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"SampleAfterValue": "2000003",
@@ -728,8 +562,6 @@
},
{
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"SampleAfterValue": "2000003",
@@ -737,8 +569,6 @@
},
{
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/other.json b/tools/perf/pmu-events/arch/x86/haswellx/other.json
index 7ca34f09b185..2395ebf112db 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/other.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json
index 42f6a8100661..9ac36c1c24b6 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_UOPS",
"SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Speculative and retired branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"SampleAfterValue": "200003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -47,8 +37,6 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -56,8 +44,6 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -65,8 +51,6 @@
},
{
"BriefDescription": "Not taken macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -74,8 +58,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -83,8 +65,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"SampleAfterValue": "200003",
@@ -92,8 +72,6 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -101,8 +79,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -110,8 +86,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -119,8 +93,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -128,8 +100,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "Branch instructions at retirement.",
@@ -137,8 +107,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -147,8 +115,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -158,8 +124,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PublicDescription": "Number of far branches retired.",
@@ -168,8 +132,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -178,8 +140,6 @@
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
@@ -188,8 +148,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -199,8 +157,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -210,8 +166,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "Counts the number of not taken branch instructions retired.",
@@ -220,8 +174,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -230,8 +182,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -239,8 +189,6 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -248,8 +196,6 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -257,8 +203,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -266,8 +210,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -275,8 +217,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -284,8 +224,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"SampleAfterValue": "200003",
@@ -293,8 +231,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Mispredicted branch instructions at retirement.",
@@ -302,8 +238,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -313,8 +247,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -323,8 +255,6 @@
},
{
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -334,8 +264,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003",
@@ -343,8 +271,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
@@ -354,8 +280,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
@@ -364,8 +288,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003",
@@ -373,8 +295,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.",
"SampleAfterValue": "2000003",
@@ -382,8 +302,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
@@ -393,8 +311,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
@@ -403,8 +319,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
"SampleAfterValue": "2000003",
@@ -413,16 +327,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
@@ -431,16 +341,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles with pending L1 cache miss loads.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -450,8 +356,6 @@
},
{
"BriefDescription": "Cycles with pending L2 cache miss loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD78, HSM63, HSM80",
"EventCode": "0xa3",
@@ -462,8 +366,6 @@
},
{
"BriefDescription": "Cycles with pending memory loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -473,8 +375,6 @@
},
{
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -484,8 +384,6 @@
},
{
"BriefDescription": "Execution stalls due to L1 data cache misses",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -495,8 +393,6 @@
},
{
"BriefDescription": "Execution stalls due to L2 cache misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"Errata": "HSM63, HSM80",
"EventCode": "0xa3",
@@ -507,8 +403,6 @@
},
{
"BriefDescription": "Execution stalls due to memory subsystem.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -518,8 +412,6 @@
},
{
"BriefDescription": "Stall cycles because IQ is full",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"PublicDescription": "Stall cycles due to IQ is full.",
@@ -528,8 +420,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).",
@@ -538,8 +428,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"Errata": "HSD140, HSD143",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
@@ -548,8 +436,6 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD11, HSD140",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
@@ -558,8 +444,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"Errata": "HSD140",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
@@ -570,8 +454,6 @@
},
{
"BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
@@ -580,8 +462,6 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -592,8 +472,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -603,8 +481,6 @@
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -613,8 +489,6 @@
},
{
"BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.",
@@ -623,8 +497,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.",
@@ -633,8 +505,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
@@ -643,8 +513,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
@@ -653,8 +521,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -663,8 +529,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -673,8 +537,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
"PublicDescription": "Number of uops delivered by the LSD.",
@@ -683,8 +545,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -694,8 +554,6 @@
},
{
"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "2000003",
@@ -703,8 +561,6 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"SampleAfterValue": "100003",
@@ -712,8 +568,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -722,8 +576,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"PublicDescription": "Number of integer move elimination candidate uops that were eliminated.",
@@ -732,8 +584,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.",
@@ -742,8 +592,6 @@
},
{
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.",
@@ -752,8 +600,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD135",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
@@ -763,8 +609,6 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
@@ -772,8 +616,6 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
@@ -781,8 +623,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.",
@@ -791,8 +631,6 @@
},
{
"BriefDescription": "Count cases of saving new LBR",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Count cases of saving new LBR records by hardware.",
@@ -801,8 +639,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.",
@@ -811,8 +647,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -823,8 +657,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"SampleAfterValue": "2000003",
@@ -832,8 +664,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"SampleAfterValue": "2000003",
@@ -841,8 +671,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue": "2000003",
@@ -850,8 +678,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue": "2000003",
@@ -859,8 +685,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue": "2000003",
@@ -868,8 +692,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue": "2000003",
@@ -877,8 +699,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"SampleAfterValue": "2000003",
@@ -886,8 +706,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"SampleAfterValue": "2000003",
@@ -895,8 +713,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD30, HSM31",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
@@ -906,8 +722,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
@@ -917,8 +731,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
@@ -928,8 +740,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
@@ -939,8 +749,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
@@ -950,8 +758,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -961,8 +767,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -973,8 +777,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -985,8 +787,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -997,8 +797,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -1008,8 +806,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
@@ -1020,8 +816,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0",
"PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.",
@@ -1031,8 +825,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
@@ -1040,8 +832,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1",
"PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.",
@@ -1051,8 +841,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
@@ -1060,8 +848,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2",
"PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.",
@@ -1071,8 +857,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -1080,8 +864,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3",
"PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.",
@@ -1091,8 +873,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
@@ -1100,8 +880,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4",
"PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.",
@@ -1111,8 +889,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
@@ -1120,8 +896,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5",
"PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.",
@@ -1131,8 +905,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
@@ -1140,8 +912,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6",
"PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.",
@@ -1151,8 +921,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 6.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003",
@@ -1160,8 +928,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7",
"PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.",
@@ -1171,8 +937,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 7.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue": "2000003",
@@ -1180,8 +944,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.",
@@ -1191,8 +953,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1202,8 +962,6 @@
},
{
"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.",
@@ -1212,8 +970,6 @@
},
{
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL",
"PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
@@ -1222,8 +978,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.",
@@ -1232,8 +986,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1243,8 +995,6 @@
},
{
"BriefDescription": "Actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@@ -1255,8 +1005,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1266,8 +1014,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -1277,8 +1023,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1288,8 +1032,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json
index 56047f9c6f20..183bcac99642 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json
@@ -1,446 +1,627 @@
[
{
- "BriefDescription": "Bounce Control",
- "Counter": "0,1,2,3",
- "EventCode": "0xA",
- "EventName": "UNC_C_BOUNCE_CONTROL",
+ "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
+ "Filter": "filter_opc=0x191",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_C_CLOCKTICKS",
+ "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
+ "Filter": "filter_opc=0x192",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x1F",
- "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+ "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.DATA_READ",
+ "Filter": "filter_opc=0x182",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "FaST wire asserted",
- "Counter": "0,1",
- "EventCode": "0x9",
- "EventName": "UNC_C_FAST_ASSERTED",
+ "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_READ",
+ "Filter": "filter_opc=0x187,filter_nc=1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; Data Read Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+ "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_WRITE",
+ "Filter": "filter_opc=0x18f,filter_nc=1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; Write Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+ "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
+ "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; External Snoop Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+ "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.PCIE_READ",
+ "Filter": "filter_opc=0x19e",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.PCIE_WRITE",
+ "Filter": "filter_opc=0x1c8",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
+ "Filter": "filter_opc=0x190",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.UNCACHEABLE",
+ "Filter": "filter_opc=0x187",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
+ "Filter": "filter_opc=0x181",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
+ "Filter": "filter_opc=0x180,filter_tid=0x3e",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.PCIE_READ",
+ "Filter": "filter_opc=0x19e",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.PCIE_WRITE",
+ "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_FULL",
+ "Filter": "filter_opc=0x18c",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
+ "Filter": "filter_opc=0x18d",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Bounce Control",
+ "EventCode": "0xA",
+ "EventName": "UNC_C_BOUNCE_CONTROL",
+ "PerPkg": "1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Uncore Clocks",
+ "EventName": "UNC_C_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Counter 0 Occupancy",
+ "EventCode": "0x1F",
+ "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+ "PerPkg": "1",
+ "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "FaST wire asserted",
+ "EventCode": "0x9",
+ "EventName": "UNC_C_FAST_ASSERTED",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn.",
"Unit": "CBO"
},
{
"BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.ANY",
"Filter": "filter_state=0x1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
"ScaleUnit": "64Bytes",
"UMask": "0x11",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Cache Lookups; Data Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Cache Lookups; Lookups that Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.NID",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
"UMask": "0x41",
"Unit": "CBO"
},
{
"BriefDescription": "Cache Lookups; Any Read Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.READ",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
"UMask": "0x21",
"Unit": "CBO"
},
{
- "BriefDescription": "M line evictions from LLC (writebacks to memory)",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+ "BriefDescription": "Cache Lookups; External Snoop Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+ "UMask": "0x9",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized; Lines in E state",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+ "BriefDescription": "Cache Lookups; Write Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.",
+ "UMask": "0x5",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines in S State",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Lines Victimized; Lines in E state",
"EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+ "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.F_STATE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Lines Victimized; Lines in S State",
"EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.NID",
+ "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.MISS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+ "BriefDescription": "M line evictions from LLC (writebacks to memory)",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; Write Combining Aliasing",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.NID",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+ "UMask": "0x40",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
"EventCode": "0x39",
- "EventName": "UNC_C_MISC.WC_ALIASING",
+ "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
"EventCode": "0x39",
- "EventName": "UNC_C_MISC.STARTED",
+ "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Cbo Misc; RFO HitS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RFO_HIT_S",
"PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.",
"UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
"EventCode": "0x39",
- "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
+ "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cbo Misc",
"EventCode": "0x39",
- "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
+ "EventName": "UNC_C_MISC.STARTED",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+ "EventCode": "0x39",
+ "EventName": "UNC_C_MISC.WC_ALIASING",
+ "PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Age 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE0",
"PerPkg": "1",
+ "PublicDescription": "How often age was set to 0",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Age 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE1",
"PerPkg": "1",
+ "PublicDescription": "How often age was set to 1",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Age 2",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE2",
"PerPkg": "1",
+ "PublicDescription": "How often age was set to 2",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Age 3",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE3",
"PerPkg": "1",
+ "PublicDescription": "How often age was set to 3",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Bits Decremented",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.LRU_DECREMENT",
"PerPkg": "1",
+ "PublicDescription": "How often all LRU bits were decremented by 1",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; Non-0 Aged Victim",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
"PerPkg": "1",
+ "PublicDescription": "How often we picked a victim that had a non-zero age",
"UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; All",
"EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+ "EventName": "UNC_C_RING_AD_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Down",
"EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.UP_ODD",
+ "EventName": "UNC_C_RING_AD_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Up and Even",
"EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.DOWN",
+ "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; All",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Up and Odd",
"EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.ALL",
+ "EventName": "UNC_C_RING_AD_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; All",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
+ "EventName": "UNC_C_RING_AK_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Down",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.UP_ODD",
+ "EventName": "UNC_C_RING_AK_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Even",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.DOWN",
+ "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; All",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Odd",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.ALL",
+ "EventName": "UNC_C_RING_AK_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Down",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
+ "EventName": "UNC_C_RING_BL_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Down",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.UP_ODD",
+ "EventName": "UNC_C_RING_BL_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Up and Even",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.DOWN",
+ "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Up and Odd",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.ALL",
+ "EventName": "UNC_C_RING_BL_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AD",
"PerPkg": "1",
@@ -449,7 +630,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AK",
"PerPkg": "1",
@@ -458,7 +638,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.BL",
"PerPkg": "1",
@@ -466,8 +645,7 @@
"Unit": "CBO"
},
{
- "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.IV",
"PerPkg": "1",
@@ -476,43 +654,42 @@
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.ANY",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_C_RING_IV_USED.UP",
+ "EventName": "UNC_C_RING_IV_USED.DN",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.DOWN",
"PerPkg": "1",
- "UMask": "0xCC",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
+ "UMask": "0xcc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_C_RING_IV_USED.DN",
+ "EventName": "UNC_C_RING_IV_USED.UP",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
"BriefDescription": "UNC_C_RING_SINK_STARVED.AD",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AD",
"PerPkg": "1",
@@ -521,7 +698,6 @@
},
{
"BriefDescription": "UNC_C_RING_SINK_STARVED.AK",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AK",
"PerPkg": "1",
@@ -529,396 +705,404 @@
"Unit": "CBO"
},
{
- "BriefDescription": "UNC_C_RING_SINK_STARVED.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "UNC_C_RING_SINK_STARVED.BL",
"EventCode": "0x6",
- "EventName": "UNC_C_RING_SINK_STARVED.IV",
+ "EventName": "UNC_C_RING_SINK_STARVED.BL",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "UNC_C_RING_SINK_STARVED.BL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "UNC_C_RING_SINK_STARVED.IV",
"EventCode": "0x6",
- "EventName": "UNC_C_RING_SINK_STARVED.BL",
+ "EventName": "UNC_C_RING_SINK_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
"EventCode": "0x7",
"EventName": "UNC_C_RING_SRC_THRTL",
"PerPkg": "1",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+ "EventCode": "0x12",
+ "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.",
+ "UMask": "0x2",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
"EventCode": "0x12",
- "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+ "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.",
"UMask": "0x4",
"Unit": "CBO"
},
- {
- "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+ {
+ "BriefDescription": "Ingress Allocations; IPQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_C_RxR_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Allocations; IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Allocations; IRQ Rejected",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x2",
"Unit": "CBO"
},
- {
- "BriefDescription": "Ingress Allocations; IPQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_C_RxR_INSERTS.IPQ",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
"EventCode": "0x14",
- "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
+ "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
"EventCode": "0x14",
- "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+ "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.PRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
"UMask": "0x10",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Probe Queue Retries; Address Conflict",
+ "EventCode": "0x31",
+ "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Probe Queue Retries; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Probe Queue Retries; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.",
"UMask": "0x2",
"Unit": "CBO"
},
- {
- "BriefDescription": "Probe Queue Retries; Address Conflict",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
{
"BriefDescription": "Probe Queue Retries; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Probe Queue Retries; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
"UMask": "0x40",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+ "EventCode": "0x32",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Request Queue Rejects; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried.",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
"EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+ "UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Request Queue Rejects",
"EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+ "UMask": "0x40",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
+ "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information.",
"UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
"EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
"UMask": "0x40",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Retries; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Retries; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried.",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries; No RTIDs",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries; No IIO Credits",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+ "UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries; No QPI Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+ "UMask": "0x40",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries; No IIO Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries; No QPI Credits",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries; No RTIDs",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+ "UMask": "0x80",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
"UMask": "0x40",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Ingress Occupancy; IPQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Occupancy; IRQ",
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Occupancy; IPQ",
+ "BriefDescription": "Ingress Occupancy; IRQ Rejected",
"EventCode": "0x11",
- "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+ "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
@@ -926,24 +1110,25 @@
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x20",
"Unit": "CBO"
},
{
"BriefDescription": "SBo Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "SBo Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x2",
"Unit": "CBO"
},
@@ -952,6 +1137,7 @@
"EventCode": "0x3E",
"EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x1",
"Unit": "CBO"
},
@@ -960,361 +1146,188 @@
"EventCode": "0x3E",
"EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x2",
"Unit": "CBO"
},
- {
- "BriefDescription": "TOR Inserts; Opcode Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.OPCODE",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
- "Filter": "filter_opc=0x180,filter_tid=0x3e",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
- "Filter": "filter_opc=0x181",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_FULL",
- "Filter": "filter_opc=0x18c",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
- "Filter": "filter_opc=0x18d",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.PCIE_READ",
- "Filter": "filter_opc=0x19e",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.PCIE_WRITE",
- "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Inserts; Evictions",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.EVICTION",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
{
"BriefDescription": "TOR Inserts; All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
"UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Writebacks",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.WB",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Inserts; Miss Opcode Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.DATA_READ",
- "Filter": "filter_opc=0x182",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.UNCACHEABLE",
- "Filter": "filter_opc=0x187",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_READ",
- "Filter": "filter_opc=0x187,filter_nc=1",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_WRITE",
- "Filter": "filter_opc=0x18f,filter_nc=1",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Evictions",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
- "Filter": "filter_opc=0x190",
+ "EventName": "UNC_C_TOR_INSERTS.EVICTION",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Local Memory",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
- "Filter": "filter_opc=0x191",
+ "EventName": "UNC_C_TOR_INSERTS.LOCAL",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x28",
"Unit": "CBO"
},
{
- "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
- "Filter": "filter_opc=0x192",
+ "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x21",
"Unit": "CBO"
},
{
- "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Local Memory",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.PCIE_READ",
- "Filter": "filter_opc=0x19e",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
- "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.PCIE_WRITE",
- "Filter": "filter_opc=0x1c8",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x23",
"Unit": "CBO"
},
{
- "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Miss Opcode Match",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
- "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID and Opcode Matched",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Remote Memory",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID Matched Evictions",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.",
+ "UMask": "0x83",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; NID Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
"UMask": "0x48",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID Matched Writebacks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID Matched Evictions",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_WB",
+ "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
"PerPkg": "1",
- "UMask": "0x50",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.",
+ "UMask": "0x44",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID Matched Miss All",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
"PerPkg": "1",
- "UMask": "0x43",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID Matched Miss All",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
+ "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
"PerPkg": "1",
- "UMask": "0x4A",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.",
+ "UMask": "0x43",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Local Memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID and Opcode Matched",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
+ "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
"PerPkg": "1",
- "UMask": "0x2A",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.",
+ "UMask": "0x41",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Remote Memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID Matched Writebacks",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
+ "EventName": "UNC_C_TOR_INSERTS.NID_WB",
"PerPkg": "1",
- "UMask": "0x8A",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.",
+ "UMask": "0x50",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Local Memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Opcode Match",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOCAL",
+ "EventName": "UNC_C_TOR_INSERTS.OPCODE",
"PerPkg": "1",
- "UMask": "0x28",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; Remote Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory.",
"UMask": "0x88",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
- "PerPkg": "1",
- "UMask": "0x23",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
- "PerPkg": "1",
- "UMask": "0x83",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.",
+ "UMask": "0x81",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Writebacks",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.WB",
"PerPkg": "1",
- "UMask": "0x81",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Opcode Match",
+ "BriefDescription": "TOR Occupancy; Any",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
@@ -1322,33 +1335,36 @@
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
"UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Any",
+ "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
+ "Filter": "filter_opc=0x182",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
- "Filter": "filter_opc=0x182",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x28",
"Unit": "CBO"
},
{
- "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch)",
+ "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
- "Filter": "filter_opc=0x182",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x21",
"Unit": "CBO"
},
{
@@ -1356,103 +1372,125 @@
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.",
+ "UMask": "0xa",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID Matched Evictions",
+ "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x23",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID Matched",
+ "BriefDescription": "TOR Occupancy; Miss Opcode Match",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
"PerPkg": "1",
- "UMask": "0x48",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
"PerPkg": "1",
- "UMask": "0x43",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x8a",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
+ "PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.",
+ "UMask": "0x83",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Occupancy; NID Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
"PerPkg": "1",
- "UMask": "0x4A",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+ "UMask": "0x48",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID Matched Evictions",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
"PerPkg": "1",
- "UMask": "0x2A",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .",
+ "UMask": "0x44",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
"PerPkg": "1",
- "UMask": "0x8A",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
"PerPkg": "1",
- "UMask": "0x28",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.",
+ "UMask": "0x43",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
"PerPkg": "1",
- "UMask": "0x88",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.",
+ "UMask": "0x41",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
+ "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
"PerPkg": "1",
- "UMask": "0x23",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.",
+ "UMask": "0x50",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
+ "BriefDescription": "TOR Occupancy; Opcode Match",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
"PerPkg": "1",
- "UMask": "0x83",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x88",
"Unit": "CBO"
},
{
@@ -1460,6 +1498,7 @@
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.",
"UMask": "0x81",
"Unit": "CBO"
},
@@ -1468,20 +1507,12 @@
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.WB",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include RFO, but actual operations that contain data being sent from the core.",
"UMask": "0x10",
"Unit": "CBO"
},
- {
- "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
- "PerPkg": "1",
- "UMask": "0x50",
- "Unit": "CBO"
- },
{
"BriefDescription": "Onto AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AD",
"PerPkg": "1",
@@ -1490,7 +1521,6 @@
},
{
"BriefDescription": "Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AK",
"PerPkg": "1",
@@ -1499,7 +1529,6 @@
},
{
"BriefDescription": "Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.BL",
"PerPkg": "1",
@@ -1508,386 +1537,307 @@
},
{
"BriefDescription": "Egress Allocations; AD - Cachebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Egress Allocations; AK - Cachebo",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Egress Allocations; BL - Cacheno",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Egress Allocations; IV - Cachebo",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AD - Corebo",
"EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
+ "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Egress Allocations; AD - Corebo",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AK - Cachebo",
"EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
+ "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Egress Allocations; AK - Corebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CORE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo.",
"UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Egress Allocations; BL - Corebo",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; BL - Cacheno",
"EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
+ "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "Injection Starvation; Onto BL Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
+ "BriefDescription": "Egress Allocations; BL - Corebo",
+ "EventCode": "0x2",
+ "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CBO"
},
{
- "BriefDescription": "Injection Starvation; Onto IV Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_C_TxR_STARVED.IV",
+ "BriefDescription": "Egress Allocations; IV - Cachebo",
+ "EventCode": "0x2",
+ "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AD_CORE",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation",
"UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Occupancy; IRQ Rejected",
- "EventCode": "0x11",
- "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
+ "BriefDescription": "Injection Starvation; Onto AK Ring",
+ "EventCode": "0x3",
+ "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized; Lines in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
+ "BriefDescription": "Injection Starvation; Onto BL Ring",
+ "EventCode": "0x3",
+ "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation",
"UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; Address",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.OPC",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; AD Opcodes",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.AD",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; BL Opcodes",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.BL",
+ "BriefDescription": "Injection Starvation; Onto IV Ring",
+ "EventCode": "0x3",
+ "EventName": "UNC_C_TxR_STARVED.IV",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation",
"UMask": "0x8",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; AK Opcodes",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.AK",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "HA"
+ "Unit": "CBO"
},
{
"BriefDescription": "BT Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_H_BT_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
"Unit": "HA"
},
{
- "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
"EventCode": "0x51",
- "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
+ "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
"EventCode": "0x51",
- "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
+ "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
"UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Bypass; Not Taken",
"EventCode": "0x14",
- "EventName": "UNC_H_BYPASS_IMC.TAKEN",
+ "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Bypass; Taken",
"EventCode": "0x14",
- "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
+ "EventName": "UNC_H_BYPASS_IMC.TAKEN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "uclks",
- "Counter": "0,1,2,3",
"EventName": "UNC_H_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
"Unit": "HA"
},
{
"BriefDescription": "Direct2Core Messages Sent",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_H_DIRECT2CORE_COUNT",
"PerPkg": "1",
+ "PublicDescription": "Number of Direct2Core messages sent",
"Unit": "HA"
},
{
"BriefDescription": "Cycles when Direct2Core was Disabled",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles in which Direct2Core was disabled",
"Unit": "HA"
},
{
"BriefDescription": "Number of Reads that had Direct2Core Overridden",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
+ "PublicDescription": "Number of Reads where Direct2Core overridden",
"Unit": "HA"
},
{
"BriefDescription": "Directory Lat Opt Return",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_H_DIRECTORY_LAT_OPT",
"PerPkg": "1",
+ "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
"Unit": "HA"
},
{
- "BriefDescription": "Directory Lookups; Snoop Needed",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Directory Lookups; Snoop Not Needed",
"EventCode": "0xC",
- "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
+ "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Directory Lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Directory Lookups; Snoop Needed",
"EventCode": "0xC",
- "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
+ "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Directory Updates; Directory Set",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Directory Updates; Any Directory Update",
"EventCode": "0xD",
- "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
+ "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.",
+ "UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "Directory Updates; Directory Clear",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory clears. This occurs when snoops were sent and all returned with RspI.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Directory Updates; Any Directory Update",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Directory Updates; Directory Set",
"EventCode": "0xD",
- "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
+ "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory sets. This occurs when a remote read transaction requests memory, bringing it to a remote cache.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
+ "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.WBMTOI",
+ "EventName": "UNC_H_HITME_HIT.ALL",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0xff",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
+ "EventName": "UNC_H_HITME_HIT.ALLOCS",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x70",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
+ "EventName": "UNC_H_HITME_HIT.EVICTS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x42",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
+ "EventName": "UNC_H_HITME_HIT.HOM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
+ "EventName": "UNC_H_HITME_HIT.INVALS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x26",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSPFWDS",
+ "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSP",
"PerPkg": "1",
@@ -1895,98 +1845,87 @@
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.ALLOCS",
+ "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
"PerPkg": "1",
- "UMask": "0x70",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.EVICTS",
+ "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
"PerPkg": "1",
- "UMask": "0x42",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.INVALS",
+ "EventName": "UNC_H_HITME_HIT.RSPFWDS",
"PerPkg": "1",
- "UMask": "0x26",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.ALL",
+ "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.HOM",
+ "EventName": "UNC_H_HITME_HIT.WBMTOI",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0xff",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x80",
"Unit": "HA"
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
"PerPkg": "1",
@@ -1994,107 +1933,87 @@
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
+ "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
+ "EventName": "UNC_H_HITME_LOOKUP.ALL",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xff",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+ "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x70",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+ "EventName": "UNC_H_HITME_LOOKUP.HOM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
+ "EventName": "UNC_H_HITME_LOOKUP.INVALS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x26",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
+ "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSP",
"PerPkg": "1",
@@ -2102,1536 +2021,1537 @@
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
+ "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
"PerPkg": "1",
- "UMask": "0x70",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.INVALS",
+ "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
"PerPkg": "1",
- "UMask": "0x26",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.ALL",
+ "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.HOM",
+ "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
"EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
"EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
"UMask": "0x20",
"Unit": "HA"
},
{
"BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_H_IMC_READS.NORMAL",
"PerPkg": "1",
+ "PublicDescription": "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Retry Events",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_H_IMC_RETRY",
"PerPkg": "1",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
"EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.FULL",
+ "EventName": "UNC_H_IMC_WRITES.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
"EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.PARTIAL",
+ "EventName": "UNC_H_IMC_WRITES.FULL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
"UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
"EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
+ "EventName": "UNC_H_IMC_WRITES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
"EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.ALL",
+ "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0x61",
- "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
+ "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0x61",
- "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
+ "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x64",
"EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x64",
"EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0x65",
"EventName": "UNC_H_IOT_CTS_HI.CTS2",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0x65",
"EventName": "UNC_H_IOT_CTS_HI.CTS3",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x62",
"EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x62",
"EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Local Reads",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Snoop Broadcast; Cancelled",
"EventCode": "0x53",
- "EventName": "UNC_H_OSB.READS_LOCAL",
+ "EventName": "UNC_H_OSB.CANCELLED",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
"BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.INVITOE_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Remote",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Snoop Broadcast; Local Reads",
"EventCode": "0x53",
- "EventName": "UNC_H_OSB.REMOTE",
+ "EventName": "UNC_H_OSB.READS_LOCAL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Cancelled",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful",
"EventCode": "0x53",
- "EventName": "UNC_H_OSB.CANCELLED",
+ "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Snoop Broadcast; Remote",
"EventCode": "0x53",
- "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
+ "EventName": "UNC_H_OSB.REMOTE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.REMOTE_USEFUL",
"PerPkg": "1",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x40",
"Unit": "HA"
},
{
"BriefDescription": "OSB Early Data Return; All",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "OSB Early Data Return; Reads to Local I",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Early Data Return; Reads to Remote I",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Early Data Return; Reads to Local S",
"EventCode": "0x54",
- "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
+ "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Early Data Return; Reads to Local S",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Early Data Return; Reads to Remote I",
"EventCode": "0x54",
- "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
+ "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+ "UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "OSB Early Data Return; Reads to Remote S",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
"UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Reads",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Read and Write Requests; Local InvItoEs",
"EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.READS",
+ "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Writes",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Read and Write Requests; Remote InvItoEs",
"EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.WRITES",
+ "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.",
+ "UMask": "0x20",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Read and Write Requests; Reads",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests. This is a good proxy for LLC Read Misses (including RFOs).",
+ "UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "Read and Write Requests; Local Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket. This is a good proxy for LLC Read Misses (including RFOs) from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Read and Write Requests; Remote Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket. This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.",
"UMask": "0x2",
"Unit": "HA"
},
+ {
+ "BriefDescription": "Read and Write Requests; Writes",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.WRITES",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
+ "UMask": "0xc",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Read and Write Requests; Local Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "Read and Write Requests; Remote Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.",
"UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Local InvItoEs",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Read and Write Requests; Remote InvItoEs",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "HA"
- },
- {
- "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA AD Ring in Use; Counterclockwise",
"EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CW_ODD",
+ "EventName": "UNC_H_RING_AD_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "HA AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
"EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CCW",
+ "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
+ "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
+ "EventCode": "0x3E",
+ "EventName": "UNC_H_RING_AD_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA AK Ring in Use; Counterclockwise",
"EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CW_ODD",
+ "EventName": "UNC_H_RING_AK_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
"EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CCW",
+ "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+ "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
+ "EventCode": "0x3F",
+ "EventName": "UNC_H_RING_AK_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA BL Ring in Use; Counterclockwise",
"EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CW_ODD",
+ "EventName": "UNC_H_RING_BL_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
"EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CCW",
+ "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
+ "EventCode": "0x40",
+ "EventName": "UNC_H_RING_BL_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "SBo1 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "SBo1 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Data beat the Snoop Responses; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Data beat the Snoop Responses; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
+ {
+ "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
+ "EventCode": "0x8",
+ "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets.",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
- {
- "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
{
"BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
+ {
+ "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
+ "UMask": "0x40",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Snoop Responses Received; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPI",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
"UMask": "0x1",
"Unit": "HA"
},
+ {
+ "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x4",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Shared line response from remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPS",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
"ScaleUnit": "64Bytes",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Shared line forwarded from remote cache",
"EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+ "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.",
"ScaleUnit": "64Bytes",
- "UMask": "0x4",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Shared line forwarded from remote cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
"EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+ "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
"ScaleUnit": "64Bytes",
- "UMask": "0x8",
+ "UMask": "0x20",
"Unit": "HA"
},
{
"BriefDescription": "Snoop Responses Received; Rsp*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSP_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
"UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+ "BriefDescription": "Snoop Responses Received Local; Other",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x20",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for all other snoop responses.",
+ "UMask": "0x80",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+ "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
"Unit": "HA"
},
{
"BriefDescription": "Snoop Responses Received Local; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
"UMask": "0x1",
"Unit": "HA"
},
- {
- "BriefDescription": "Snoop Responses Received Local; RspS",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
{
"BriefDescription": "Snoop Responses Received Local; RspIFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
"UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspSFwd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Snoop Responses Received Local; RspS",
"EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Snoop Responses Received Local; RspSFwd",
"EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
"UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspCnflct",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Snoop Responses Received Local; Other",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
"EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
"EventCode": "0x6C",
- "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
"EventCode": "0x6C",
- "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
+ "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4",
"UMask": "0x10",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5",
"UMask": "0x20",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6",
"UMask": "0x40",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7",
"UMask": "0x80",
"Unit": "HA"
},
+ {
+ "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+ "EventCode": "0x1C",
+ "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10",
+ "UMask": "0x4",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+ "EventCode": "0x1C",
+ "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11",
+ "UMask": "0x8",
+ "Unit": "HA"
+ },
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+ "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
+ "EventCode": "0x2",
+ "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries. It will not return valid count when BT is disabled.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+ "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
+ "EventCode": "0x2",
+ "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used. It will not return valid count when BT is disabled.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
+ "BriefDescription": "Tracker Cycles Not Empty; All Requests",
+ "EventCode": "0x3",
+ "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
+ "EventCode": "0x3",
+ "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
+ "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
+ "EventCode": "0x3",
+ "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
+ {
+ "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x40",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x80",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
"UMask": "0x10",
"Unit": "HA"
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
"UMask": "0x20",
"Unit": "HA"
},
- {
- "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "HA"
- },
{
"BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_H_TxR_AD.HOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring. NDR stands for non-data response and is generally used for completions that do not include data. AD NDR is used for transactions to remote sockets.",
"UMask": "0x4",
"Unit": "HA"
},
+ {
+ "BriefDescription": "AD Egress Full; All",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "AD Egress Full; Cycles full from both schedulers",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
{
"BriefDescription": "AD Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Full; Filter for cycles full from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Full; Filter for cycles full from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+ "BriefDescription": "AD Egress Not Empty; All",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Not Empty; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
+ "BriefDescription": "AD Egress Allocations; All",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Allocations; Allocations from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
+ "BriefDescription": "AK Egress Full; All",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Full; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Full; Filter for cycles full from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Full; Filter for cycles full from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AK Egress Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+ "BriefDescription": "AK Egress Not Empty; All",
+ "EventCode": "0x31",
+ "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Not Empty; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AK Egress Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
+ "BriefDescription": "AK Egress Allocations; All",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Allocations; Allocations from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
- {
- "BriefDescription": "AK Egress Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to the cache.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CORE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent directly to the requesting core.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_QPI",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.",
"UMask": "0x4",
"Unit": "HA"
},
+ {
+ "BriefDescription": "BL Egress Full; All",
+ "EventCode": "0x36",
+ "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "BL Egress Full; Cycles full from both schedulers",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
{
"BriefDescription": "BL Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Full; Filter for cycles full from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Full; Filter for cycles full from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "BL Egress Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x36",
- "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+ "BriefDescription": "BL Egress Not Empty; All",
+ "EventCode": "0x35",
+ "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Not Empty; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "BL Egress Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
+ "BriefDescription": "BL Egress Allocations; All",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Allocations; Allocations from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
- {
- "BriefDescription": "BL Egress Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
{
"BriefDescription": "Injection Starvation; For AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_H_TxR_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Injection Starvation; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_H_TxR_STARVED.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
- },
- {
- "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Tracker Cycles Not Empty; All Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json
index eb0a05fbb704..15059b17cd19 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json
@@ -1,1452 +1,1332 @@
[
+ {
+ "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
+ "EventName": "QPI_CTL_BANDWIDTH_TX",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.",
+ "ScaleUnit": "8Bytes",
+ "UMask": "0x4",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
+ "EventName": "QPI_DATA_BANDWIDTH_TX",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.",
+ "ScaleUnit": "8Bytes",
+ "UMask": "0x2",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Number of qfclks",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. HSX does not support dynamic link speeds, so this frequency is fixed.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Count of CTO Events",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_Q_CTO_COUNT",
- "ExtSel": "1",
"PerPkg": "1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
- "PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
"EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
+ "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.",
"UMask": "0x8",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
+ "EventCode": "0x13",
+ "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.",
+ "UMask": "0x80",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
"EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
+ "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.",
+ "UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.",
"UMask": "0x40",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
"EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+ "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L1",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_L1_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL0P_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL0_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_BYPASSED",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"Unit": "QPI LL"
},
{
"BriefDescription": "CRC Errors Detected; LinkInit",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
"PerPkg": "1",
+ "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "CRC Errors Detected; Normal Operations",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
"PerPkg": "1",
+ "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.",
"UMask": "0x1",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "VN0 Credit Consumed; HOM",
+ "EventCode": "0x1E",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "VN0 Credit Consumed; NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN0 Credit Consumed; HOM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VN0 Credit Consumed; NDR",
"EventCode": "0x1E",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN0 Credit Consumed; NDR",
- "Counter": "0,1,2,3",
- "EventCode": "0x1E",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
- "ExtSel": "1",
+ "BriefDescription": "VN1 Credit Consumed; DRS",
+ "EventCode": "0x39",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN1 Credit Consumed; DRS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VN1 Credit Consumed; HOM",
"EventCode": "0x39",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.",
+ "UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN1 Credit Consumed; HOM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VN1 Credit Consumed; NDR",
"EventCode": "0x39",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.",
"UMask": "0x10",
"Unit": "QPI LL"
},
- {
- "BriefDescription": "VN1 Credit Consumed; NDR",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "QPI LL"
- },
{
"BriefDescription": "VNA Credit Consumed",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.",
+ "UMask": "0x18",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).",
+ "UMask": "0x8",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.",
"UMask": "0x6",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.",
+ "UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; SNP Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x18",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
"EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.",
+ "UMask": "0xc",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
"EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
"EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_Q_RxL_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - All Packets",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x1",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
"EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x10",
"Unit": "QPI LL"
},
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "QPI LL"
- },
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events.",
"UMask": "0x40",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.GV",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.",
"UMask": "0x80",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x1",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
+ "EventCode": "0x3A",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
"EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x10",
"Unit": "QPI LL"
},
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "QPI LL"
- },
{
"BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_TxL0P_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_TxL0_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_Q_TxL_BYPASSED",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
"EventCode": "0x2",
- "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
+ "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
"EventCode": "0x2",
- "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
+ "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Cycles not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_Q_TxL_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.DATA",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
- "Counter": "0,1,2,3",
- "EventName": "QPI_DATA_BANDWIDTH_TX",
- "PerPkg": "1",
- "ScaleUnit": "8Bytes",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
- "Counter": "0,1,2,3",
- "EventName": "QPI_CTL_BANDWIDTH_TX",
- "PerPkg": "1",
- "ScaleUnit": "8Bytes",
- "UMask": "0x4",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
+ "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.",
+ "UMask": "0x18",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).",
+ "UMask": "0x8",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.",
"UMask": "0x6",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.",
+ "UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
"PerPkg": "1",
- "UMask": "0x18",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.",
+ "UMask": "0xc",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
+ "EventCode": "0x1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_Q_TxL_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_Q_TxL_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Returned",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_Q_VNA_CREDIT_RETURNS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of VNA credits returned.",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
"Unit": "QPI LL"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json
index c003daa9ed8c..c005f5115722 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json
@@ -1,34 +1,53 @@
[
{
- "BriefDescription": "DRAM Activate Count; Activate due to Read",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.RD",
+ "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
+ "EventCode": "0x4",
+ "EventName": "LLC_MISSES.MEM_READ",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.WR",
+ "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
+ "EventCode": "0x4",
+ "EventName": "LLC_MISSES.MEM_WRITE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x8",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "DRAM Activate Count; Activate due to Read",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.RD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "DRAM Activate Count; Activate due to Write",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.WR",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "ACT command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.ACT",
"PerPkg": "1",
@@ -37,7 +56,6 @@
},
{
"BriefDescription": "CAS command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.CAS",
"PerPkg": "1",
@@ -46,7 +64,6 @@
},
{
"BriefDescription": "PRE command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.PRE",
"PerPkg": "1",
@@ -54,282 +71,264 @@
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_REG",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
"UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
"EventCode": "0x4",
- "EventName": "LLC_MISSES.MEM_READ",
+ "EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+ "EventName": "UNC_M_CAS_COUNT.RD_RMM",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+ "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller. This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ. While it is possible for underfills to be issed in both WMM and RMM, this event counts both.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR",
+ "EventName": "UNC_M_CAS_COUNT.RD_WMM",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
"EventCode": "0x4",
- "EventName": "LLC_MISSES.MEM_WRITE",
+ "EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0xC",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.ALL",
+ "EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+ "EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+ "BriefDescription": "DRAM Clockticks",
+ "EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Clockticks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_M_CLOCKTICKS",
+ "EventName": "UNC_M_DCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that the precharge all command was sent.",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
- "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+ "EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of refreshes issued.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
- "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+ "EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of refreshes issued.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "ECC Correctable Errors",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.READ",
+ "EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.WRITE",
+ "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+ "EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+ "EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Channel DLLOFF Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
"Unit": "iMC"
},
{
"BriefDescription": "Channel PPD Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Critical Throttle Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M_POWER_PCU_THROTTLING",
"PerPkg": "1",
@@ -337,150 +336,157 @@
},
{
"BriefDescription": "Clock-Enabled Self-Refresh",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
"UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
"EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "EventName": "UNC_M_PRE_COUNT.BYP",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring. This does not include implicit precharge commands sent in auto-precharge mode.",
"UMask": "0x2",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+ "EventCode": "0x2",
+ "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses. This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include PRE commands sent as a result of the page close counter expiration.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to read",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to write",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.BYP",
+ "BriefDescription": "Read CAS issued with HIGH priority",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with LOW priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.LOW",
"PerPkg": "1",
@@ -489,25 +495,14 @@
},
{
"BriefDescription": "Read CAS issued with MEDIUM priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.MED",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
- {
- "BriefDescription": "Read CAS issued with HIGH priority",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "iMC"
- },
{
"BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.PANIC",
"PerPkg": "1",
@@ -515,1186 +510,1182 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
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- "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
"Unit": "iMC"
},
{
"BriefDescription": "VMSE MXB write buffer occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
"EventCode": "0x90",
- "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
+ "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
"EventCode": "0x90",
- "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
+ "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"PerPkg": "1",
@@ -1703,7 +1694,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.STARVE",
"PerPkg": "1",
@@ -1712,7 +1702,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"PerPkg": "1",
@@ -1721,1177 +1710,1169 @@
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Not getting the requested Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_M_WRONG_MM",
"PerPkg": "1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+ "PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+ "PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
"UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
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- "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
- },
- {
- "BriefDescription": "DRAM Clockticks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_M_DCLOCKTICKS",
- "PerPkg": "1",
- "Unit": "iMC"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json
index 135b59f34f37..4c3e2a794117 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json
@@ -1,829 +1,816 @@
[
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Clocks in the IRP",
- "Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Number of clocks in the IRP.",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; PCIRdCur",
- "Counter": "0,1",
+ "BriefDescription": "Coherent Ops; CLFlush",
"EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+ "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; CRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CRD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; DRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.DRD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; RFO",
- "Counter": "0,1",
+ "BriefDescription": "Coherent Ops; PCIDCAHin5t",
"EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.RFO",
+ "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x20",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; PCIRdCur",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; PCIItoM",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; PCIDCAHin5t",
- "Counter": "0,1",
+ "BriefDescription": "Coherent Ops; RFO",
"EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+ "EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; WbMtoI",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; CLFlush",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_I_MISC0.FAST_REQ",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
"EventCode": "0x14",
- "EventName": "UNC_I_MISC0.FAST_REJ",
+ "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
"UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
"EventCode": "0x14",
- "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_MISC0.FAST_REQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
"UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_MISC0.PF_TIMEOUT",
+ "PerPkg": "1",
+ "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut",
+ "UMask": "0x80",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 1; Data Throttled",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_I",
+ "EventName": "UNC_I_MISC1.DATA_THROTTLE",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "IRP throttled switch data",
+ "UMask": "0x80",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_S",
+ "EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Received Invalid",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_E",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x20",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Received Valid",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_M",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.LOST_FWD",
+ "EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Invalid",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Valid",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Data Throttled",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.DATA_THROTTLE",
+ "EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "AK Ingress Occupancy",
- "Counter": "0,1",
"EventCode": "0xA",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
- "Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY",
- "Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY",
- "Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
- "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY",
- "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Miss",
- "Counter": "0,1",
+ "BriefDescription": "Snoop Responses; Hit E or S",
"EventCode": "0x17",
- "EventName": "UNC_I_SNOOP_RESP.MISS",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Snoop Responses : Hit E or S",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; Hit I",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses : Hit I",
"UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Hit E or S",
- "Counter": "0,1",
+ "BriefDescription": "Snoop Responses; Hit M",
"EventCode": "0x17",
- "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Snoop Responses : Hit M",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Hit M",
- "Counter": "0,1",
+ "BriefDescription": "Snoop Responses; Miss",
"EventCode": "0x17",
- "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Snoop Responses : Miss",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpCode",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses : SnpCode",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpData",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses : SnpData",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpInv",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses : SnpInv",
"UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Reads",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Atomic",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.READS",
+ "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Writes",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Other",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
+ "UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.RD_PREF",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
"UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Write Prefetches",
- "Counter": "0,1",
- "EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Inbound Transaction Count; Atomic",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Reads",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+ "EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Other",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Writes",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+ "UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Select Source",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Write Prefetches",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "No AD Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xE",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xF",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_I_MISC0.PF_TIMEOUT",
- "PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
"Unit": "IRP"
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
- "Counter": "0,1",
+ "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
"EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x4",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
- "Counter": "0,1",
+ "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
"EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x8",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
- "Counter": "0,1",
+ "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+ "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
- "Counter": "0,1",
+ "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+ "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; DRS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCB",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
"EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
+ "EventName": "UNC_R2_RING_AD_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
"EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.CCW",
+ "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "AK Ingress Bounced; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
+ "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
+ "EventCode": "0x7",
+ "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "AK Ingress Bounced; Dn",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.DN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+ "BriefDescription": "AK Ingress Bounced; Up",
+ "EventCode": "0x12",
+ "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
"EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
+ "EventName": "UNC_R2_RING_AK_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
"EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.CCW",
+ "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
+ "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
+ "EventCode": "0x8",
+ "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
"EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+ "EventName": "UNC_R2_RING_BL_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
"EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.CCW",
+ "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 IV Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
+ "EventCode": "0x9",
+ "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "R2 IV Ring in Use; Any",
"EventCode": "0xA",
- "EventName": "UNC_R2_RING_IV_USED.CW",
+ "EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CCW",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 IV Ring in Use; Any",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 IV Ring in Use; Clockwise",
"EventCode": "0xA",
- "EventName": "UNC_R2_RING_IV_USED.ANY",
+ "EventName": "UNC_R2_RING_IV_USED.CW",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0x3",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R2PCIe"
},
@@ -832,24 +819,25 @@
"EventCode": "0x13",
"EventName": "UNC_R2_RxR_OCCUPANCY.DRS",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R2PCIe"
},
@@ -858,6 +846,7 @@
"EventCode": "0x2A",
"EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
@@ -866,42 +855,43 @@
"EventCode": "0x2A",
"EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
"EventCode": "0x2C",
- "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x4",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
"EventCode": "0x2C",
- "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
+ "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
@@ -910,6 +900,7 @@
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue",
"UMask": "0x1",
"Unit": "R2PCIe"
},
@@ -918,6 +909,7 @@
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue",
"UMask": "0x2",
"Unit": "R2PCIe"
},
@@ -926,6 +918,7 @@
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue",
"UMask": "0x4",
"Unit": "R2PCIe"
},
@@ -934,6 +927,7 @@
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue",
"UMask": "0x1",
"Unit": "R2PCIe"
},
@@ -942,6 +936,7 @@
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue",
"UMask": "0x2",
"Unit": "R2PCIe"
},
@@ -950,911 +945,896 @@
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
"PerPkg": "1",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; AK CCW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
+ "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "AK CounterClockwise Egress Queue",
+ "UMask": "0x4",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
+ "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
"PerPkg": "1",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
+ "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "AD Clockwise Egress Queue",
+ "UMask": "0x20",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; BL CW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
+ "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
+ "UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2",
"EventCode": "0x1",
"EventName": "UNC_R3_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13",
+ "UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17",
"UMask": "0x80",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7",
"UMask": "0x80",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0xB",
- "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
+ "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0xB",
- "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
+ "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0xD",
"EventName": "UNC_R3_IOT_CTS_HI.CTS2",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0xD",
"EventName": "UNC_R3_IOT_CTS_HI.CTS3",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0xC",
"EventName": "UNC_R3_IOT_CTS_LO.CTS0",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0xC",
"EventName": "UNC_R3_IOT_CTS_LO.CTS1",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
- "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
- "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
- "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
+ "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
- "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
- "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
- "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
+ "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
- "EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
"EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
+ "EventName": "UNC_R3_RING_AD_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
"EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.CCW",
+ "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
- "EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
+ "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
+ "EventCode": "0x7",
+ "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
"EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
+ "EventName": "UNC_R3_RING_AK_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
"EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.CCW",
+ "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
- "EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
+ "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
+ "EventCode": "0x8",
+ "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
"EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
+ "EventName": "UNC_R3_RING_BL_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
"EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.CCW",
+ "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 IV Ring in Use; Clockwise",
- "Counter": "0,1,2",
- "EventCode": "0xA",
- "EventName": "UNC_R3_RING_IV_USED.CW",
+ "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
+ "EventCode": "0x9",
+ "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 IV Ring in Use; Any",
- "Counter": "0,1,2",
"EventCode": "0xA",
"EventName": "UNC_R3_RING_IV_USED.ANY",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0xf",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "R3 IV Ring in Use; Clockwise",
+ "EventCode": "0xA",
+ "EventName": "UNC_R3_RING_IV_USED.CW",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0x3",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ring Stop Starved; AK",
- "Counter": "0,1,2",
"EventCode": "0xE",
"EventName": "UNC_R3_RING_SINK_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Cycles Not Empty; HOM",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "Ingress Cycles Not Empty; NDR",
+ "EventCode": "0x10",
+ "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "Ingress Cycles Not Empty; SNP",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Ingress Cycles Not Empty; NDR",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
+ "EventCode": "0x14",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; HOM",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+ "UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
+ "BriefDescription": "Ingress Allocations; DRS",
+ "EventCode": "0x11",
+ "EventName": "UNC_R3_RxR_INSERTS.DRS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; HOM",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.HOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
- {
- "BriefDescription": "Ingress Allocations; SNP",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.SNP",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "Ingress Allocations; NDR",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.NDR",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "Ingress Allocations; DRS",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.DRS",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "R3QPI"
- },
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; HOM",
- "Counter": "0,1",
- "EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
+ "BriefDescription": "Ingress Allocations; NDR",
+ "EventCode": "0x11",
+ "EventName": "UNC_R3_RxR_INSERTS.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; SNP",
- "Counter": "0,1",
- "EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
+ "BriefDescription": "Ingress Allocations; SNP",
+ "EventCode": "0x11",
+ "EventName": "UNC_R3_RxR_INSERTS.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; NDR",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Allocations; DRS",
"EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; DRS",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Allocations; HOM",
"EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
- "EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
+ "BriefDescription": "VN1 Ingress Allocations; NDR",
+ "EventCode": "0x15",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
- "EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+ "BriefDescription": "VN1 Ingress Allocations; SNP",
+ "EventCode": "0x15",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
"EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
"EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
@@ -1862,6 +1842,7 @@
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
@@ -1870,24 +1851,43 @@
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+ "EventCode": "0x13",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue",
+ "UMask": "0x4",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
+ "EventCode": "0x13",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
@@ -1896,6 +1896,7 @@
"EventCode": "0x2A",
"EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
@@ -1904,24 +1905,25 @@
"EventCode": "0x2A",
"EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
@@ -1930,6 +1932,7 @@
"EventCode": "0x2B",
"EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
@@ -1938,390 +1941,390 @@
"EventCode": "0x2B",
"EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
"EventCode": "0x2C",
- "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
"EventCode": "0x2C",
- "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
+ "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.DN_AD",
"PerPkg": "1",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
- {
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
- "EventCode": "0x26",
- "EventName": "UNC_R3_TxR_NACK.DN_BL",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.DN_AK",
"PerPkg": "1",
+ "PublicDescription": "AK CounterClockwise Egress Queue",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
"EventCode": "0x26",
- "EventName": "UNC_R3_TxR_NACK.UP_AD",
+ "EventName": "UNC_R3_TxR_NACK.DN_BL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; AK CCW",
"EventCode": "0x26",
- "EventName": "UNC_R3_TxR_NACK.UP_BL",
+ "EventName": "UNC_R3_TxR_NACK.UP_AD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; BL CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.UP_AK",
"PerPkg": "1",
+ "PublicDescription": "AD Clockwise Egress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
+ "EventCode": "0x26",
+ "EventName": "UNC_R3_TxR_NACK.UP_BL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
"EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
"EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
+ "EventCode": "0x37",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
+ "EventCode": "0x37",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Used; DRS Message Class",
"EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Used; HOM Message Class",
"EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
+ "BriefDescription": "VN0 Credit Used; NDR Message Class",
+ "EventCode": "0x36",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
+ "BriefDescription": "VN0 Credit Used; SNP Message Class",
+ "EventCode": "0x36",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
"EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
"EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
+ "EventCode": "0x39",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
+ "EventCode": "0x39",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Used; DRS Message Class",
"EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Used; HOM Message Class",
"EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "VN1 Credit Used; NDR Message Class",
+ "EventCode": "0x38",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "VN1 Credit Used; SNP Message Class",
+ "EventCode": "0x38",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; HOM Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; DRS Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; SNP Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; HOM Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; NCB Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; NCS Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).",
+ "UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; NCB Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; NDR Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; NCS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; SNP Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Bounce Control",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_S_BOUNCE_CONTROL",
"PerPkg": "1",
@@ -2329,184 +2332,182 @@
},
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventName": "UNC_S_CLOCKTICKS",
"PerPkg": "1",
"Unit": "SBO"
},
{
"BriefDescription": "FaST wire asserted",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_S_FAST_ASSERTED",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
"Unit": "SBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "SBO"
- },
- {
- "BriefDescription": "AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Down",
"EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.UP_ODD",
+ "EventName": "UNC_S_RING_AD_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Event",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "SBO"
},
{
- "BriefDescription": "AD Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Up and Even",
"EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.DOWN",
+ "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
+ "BriefDescription": "AD Ring In Use; Up and Odd",
+ "EventCode": "0x1B",
+ "EventName": "UNC_S_RING_AD_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Down",
"EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.UP_ODD",
+ "EventName": "UNC_S_RING_AK_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Event",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "SBO"
},
{
- "BriefDescription": "AK Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Even",
"EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.DOWN",
+ "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
+ "BriefDescription": "AK Ring In Use; Up and Odd",
+ "EventCode": "0x1C",
+ "EventName": "UNC_S_RING_AK_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Down",
"EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.UP_ODD",
+ "EventName": "UNC_S_RING_BL_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Event",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.UP",
+ "EventName": "UNC_S_RING_BL_USED.UP",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x3",
+ "Unit": "SBO"
+ },
+ {
+ "BriefDescription": "BL Ring in Use; Up and Even",
+ "EventCode": "0x1D",
+ "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Up and Odd",
"EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.DOWN",
+ "EventName": "UNC_S_RING_BL_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Number of LLC responses that bounced on the Ring",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of LLC responses that bounced on the Ring.",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.AD_CACHE",
"PerPkg": "1",
@@ -2515,7 +2516,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.AK_CORE",
"PerPkg": "1",
@@ -2524,7 +2524,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.BL_CORE",
"PerPkg": "1",
@@ -2532,8 +2531,7 @@
"Unit": "SBO"
},
{
- "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.IV_CORE",
"PerPkg": "1",
@@ -2542,25 +2540,24 @@
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_S_RING_IV_USED.UP",
+ "EventName": "UNC_S_RING_IV_USED.DN",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_S_RING_IV_USED.DN",
+ "EventName": "UNC_S_RING_IV_USED.UP",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0x3",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE",
"PerPkg": "1",
@@ -2569,7 +2566,6 @@
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.AK_CORE",
"PerPkg": "1",
@@ -2578,7 +2574,6 @@
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.BL_CORE",
"PerPkg": "1",
@@ -2587,277 +2582,275 @@
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.IV_CORE",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
- {
- "BriefDescription": "Injection Starvation; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "SBO"
- },
{
"BriefDescription": "Injection Starvation; AD - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; AD - Credits",
"EventCode": "0x15",
- "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
+ "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "Injection Starvation; BL - Credits",
+ "EventCode": "0x15",
+ "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; AD - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Bypass; AD - Credits",
"EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
+ "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x1",
+ "Unit": "SBO"
+ },
+ {
+ "BriefDescription": "Bypass; AK",
+ "EventCode": "0x12",
+ "EventName": "UNC_S_RxR_BYPASS.AK",
+ "PerPkg": "1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Bypass; BL - Credits",
"EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.AK",
+ "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.IV",
"PerPkg": "1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
"UMask": "0x20",
"Unit": "SBO"
},
- {
- "BriefDescription": "Injection Starvation; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "SBO"
- },
{
"BriefDescription": "Injection Starvation; AD - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; AD - Credits",
"EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
+ "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Bounces",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; AK",
"EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
+ "EventName": "UNC_S_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; BL - Bounces",
"EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.AK",
+ "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; BL - Credits",
"EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.IV",
+ "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; IVF Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
"UMask": "0x40",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "Injection Starvation; IV",
+ "EventCode": "0x14",
+ "EventName": "UNC_S_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; AD - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Allocations; AD - Credits",
"EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
+ "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x1",
+ "Unit": "SBO"
+ },
+ {
+ "BriefDescription": "Ingress Allocations; AK",
+ "EventCode": "0x13",
+ "EventName": "UNC_S_RxR_INSERTS.AK",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Allocations; BL - Credits",
"EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.AK",
+ "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.IV",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; AD - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Occupancy; AD - Bounces",
"EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; AD - Bounces",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Occupancy; AD - Credits",
"EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
+ "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Occupancy; AK",
"EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
+ "EventName": "UNC_S_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Occupancy; BL - Credits",
"EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.AK",
+ "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.IV",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_TxR_ADS_USED.AD",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_S_TxR_ADS_USED.AD",
"PerPkg": "1",
@@ -2866,7 +2859,6 @@
},
{
"BriefDescription": "UNC_S_TxR_ADS_USED.AK",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_S_TxR_ADS_USED.AK",
"PerPkg": "1",
@@ -2875,7 +2867,6 @@
},
{
"BriefDescription": "UNC_S_TxR_ADS_USED.BL",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_S_TxR_ADS_USED.BL",
"PerPkg": "1",
@@ -2883,288 +2874,287 @@
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; AD - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AD - Bounces",
"EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
+ "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; AD - Bounces",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AD - Credits",
"EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
+ "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AK",
"EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
+ "EventName": "UNC_S_TxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; BL - Credits",
"EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.AK",
+ "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.IV",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; AD - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Occupancy; AD - Bounces",
"EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; AD - Bounces",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Occupancy; AD - Credits",
"EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
+ "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Occupancy; AK",
"EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
+ "EventName": "UNC_S_TxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Occupancy; BL - Credits",
"EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.AK",
+ "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.IV",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.AD",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto IV Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.IV",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x8",
"Unit": "SBO"
},
+ {
+ "BriefDescription": "UNC_U_CLOCKTICKS",
+ "EventName": "UNC_U_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "UBOX"
+ },
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.ENABLE",
+ "EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.DISABLE",
+ "EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
+ "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
+ "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
- "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
+ "PublicDescription": "PHOLD cycles. Filter from source CoreID.",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "RACU Request",
- "Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
+ "PublicDescription": "Number outstanding register requests within message channel tracker",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Monitor T0",
- "Counter": "0,1",
- "EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UBOX"
- },
- {
- "BriefDescription": "Monitor Sent to T0; Monitor T1",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
+ "EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+ "UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
"UMask": "0x8",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Monitor T0",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.CMC",
+ "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Monitor T1",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.UMC",
+ "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Trap",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Other",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.TRAP",
+ "EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI",
+ "UMask": "0x80",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Other",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Trap",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.OTHER",
+ "EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+ "UMask": "0x40",
"Unit": "UBOX"
},
{
- "BriefDescription": "UNC_U_CLOCKTICKS",
- "Counter": "0,1",
- "EventName": "UNC_U_CLOCKTICKS",
+ "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+ "EventCode": "0x43",
+ "EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+ "UMask": "0x20",
"Unit": "UBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json
index 86b7c22af96b..daebf1050acb 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json
@@ -1,497 +1,497 @@
[
{
"BriefDescription": "pclk Cycles",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3B",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_P_DEMOTIONS_CORE15",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE16",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE17",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_P_FREQ_BAND0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_P_FREQ_BAND1_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_P_FREQ_BAND2_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_P_FREQ_BAND3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
"Unit": "PCU"
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Package C State Residency - C1E",
+ "EventCode": "0x4E",
+ "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C1E. This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C7 State Residency",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C7. This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C3",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
"PerPkg": "1",
+ "PublicDescription": "Ring GV with same final and initial frequency",
"Unit": "PCU"
},
{
- "BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
- "EventCode": "0x42",
- "EventName": "UNC_P_VR_HOT_CYCLES",
- "PerPkg": "1",
- "Unit": "PCU"
- },
- {
- "BriefDescription": "Package C State Residency - C1E",
- "Counter": "0,1,2,3",
- "EventCode": "0x4E",
- "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+ "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
+ "EventCode": "0x79",
+ "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
+ "PublicDescription": "Ring GV with same final and initial frequency",
"Unit": "PCU"
},
{
- "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
- "Counter": "0,1,2,3",
- "EventCode": "0x79",
- "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
+ "BriefDescription": "VR Hot",
+ "EventCode": "0x42",
+ "EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
"Unit": "PCU"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json
index 57d2a6452fec..87a4ec1ee7d7 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Number of cache load STLB hits. No page walk.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "2000003",
@@ -70,8 +56,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
@@ -80,8 +64,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
@@ -90,8 +72,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
@@ -100,8 +80,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
@@ -110,8 +88,6 @@
},
{
"BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
"PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
@@ -120,8 +96,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
@@ -130,8 +104,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -140,8 +112,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -150,8 +120,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
@@ -160,8 +128,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "100003",
@@ -169,8 +135,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
@@ -179,8 +143,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
@@ -189,8 +151,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
@@ -199,8 +159,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4f",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
@@ -208,8 +166,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xae",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
@@ -218,8 +174,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
@@ -228,8 +182,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "ITLB misses that hit STLB. No page walk.",
@@ -238,8 +190,6 @@
},
{
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"PublicDescription": "ITLB misses that hit STLB (2M).",
@@ -248,8 +198,6 @@
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"PublicDescription": "ITLB misses that hit STLB (4K).",
@@ -258,8 +206,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in ITLB of any page size.",
@@ -268,8 +214,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "100003",
@@ -277,8 +221,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
@@ -287,8 +229,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
@@ -297,8 +237,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.",
@@ -307,8 +245,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L1+FB",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
"PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
@@ -317,8 +253,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
"PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
@@ -327,8 +261,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@@ -338,8 +270,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in Memory",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@@ -349,8 +279,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
"SampleAfterValue": "2000003",
@@ -358,8 +286,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
"SampleAfterValue": "2000003",
@@ -367,8 +293,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
"SampleAfterValue": "2000003",
@@ -376,8 +300,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
"SampleAfterValue": "2000003",
@@ -385,8 +307,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
"SampleAfterValue": "2000003",
@@ -394,8 +314,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
"SampleAfterValue": "2000003",
@@ -403,8 +321,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
"SampleAfterValue": "2000003",
@@ -412,8 +328,6 @@
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
"SampleAfterValue": "2000003",
@@ -421,8 +335,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L1+FB",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
"PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
@@ -431,8 +343,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
"PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
@@ -441,8 +351,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@@ -452,8 +360,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in Memory",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
@@ -463,8 +369,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "DTLB flush attempts of the thread-specific entries.",
@@ -473,8 +377,6 @@
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Count number of STLB flush attempts.",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 14/32] perf vendor events intel: Refresh icelake metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (3 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 13/32] perf vendor events intel: Refresh haswellx " Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 15/32] perf vendor events intel: Refresh icelakex " Ian Rogers
` (17 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the icelake metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/icelake/cache.json | 412 ------------------
.../arch/x86/icelake/floating-point.json | 28 --
.../pmu-events/arch/x86/icelake/frontend.json | 144 ------
.../arch/x86/icelake/icl-metrics.json | 151 ++++---
.../pmu-events/arch/x86/icelake/memory.json | 171 --------
.../pmu-events/arch/x86/icelake/other.json | 132 ------
.../pmu-events/arch/x86/icelake/pipeline.json | 349 +--------------
.../arch/x86/icelake/uncore-other.json | 10 +-
.../arch/x86/icelake/virtual-memory.json | 80 ----
9 files changed, 89 insertions(+), 1388 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json
index 0f6b918484d5..bc6587391760 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json
@@ -1,1272 +1,860 @@
[
{
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of L1D misses that are outstanding",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "L2 cache lines filling L2",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1f"
},
{
"BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.NON_SILENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.SILENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xf2",
"EventName": "L2_LINES_OUT.USELESS_HWPF",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "L2 code requests",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of L2 code requests.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe4"
},
{
"BriefDescription": "Demand Data Read requests",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe1"
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand requests that miss L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x27"
},
{
"BriefDescription": "Demand requests to L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand requests to L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe7"
},
{
"BriefDescription": "RFO requests to L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe2"
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc4"
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x24"
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc1"
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x21"
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc2"
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x22"
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc8"
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x28"
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x41"
},
{
"BriefDescription": "Retired load instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
"SampleAfterValue": "1000003",
"UMask": "0x81"
},
{
"BriefDescription": "Retired store instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired store instructions.",
"SampleAfterValue": "1000003",
"UMask": "0x82"
},
{
"BriefDescription": "All retired memory instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ANY",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired memory instructions - loads and stores.",
"SampleAfterValue": "1000003",
"UMask": "0x83"
},
{
"BriefDescription": "Retired load instructions with locked access.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with locked access.",
"SampleAfterValue": "100007",
"UMask": "0x21"
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x41"
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x11"
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x12"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
"SampleAfterValue": "20011",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
"SampleAfterValue": "100021",
"UMask": "0x10"
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
"SampleAfterValue": "100021",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
"SampleAfterValue": "50021",
"UMask": "0x20"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0400",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0400",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0400",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C2380",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C8000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C8000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C8000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C8000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0800",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Demand and prefetch data reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts memory transactions sent to the uncore.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles where at least 1 outstanding data read request is pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles the queue waiting for offcore responses is full.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SQ_FULL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json
index 1925388969bb..655342dadac6 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json
@@ -1,100 +1,72 @@
[
{
"BriefDescription": "Counts all microcode FP assists.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.FP",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all microcode Floating Point assists.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/icelake/frontend.json b/tools/perf/pmu-events/arch/x86/icelake/frontend.json
index 739361d3f52f..3e3d2b002170 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/frontend.json
@@ -1,497 +1,353 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.COUNT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x11",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x14",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x500106",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
"MSRValue": "0x508006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
"MSRValue": "0x501006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x500206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
"MSRValue": "0x510006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x100206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
"MSRValue": "0x502006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
"MSRValue": "0x500406",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
"MSRValue": "0x520006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x504006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
"MSRValue": "0x500806",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x15",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles DSB is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x30"
},
{
"BriefDescription": "Number of switches from DSB or MITE to the MS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x30"
},
{
"BriefDescription": "Uops delivered to IDQ while MS is busy",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x30"
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
index 3b5ef09eb8ef..2ad36e00d289 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
@@ -41,7 +41,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
"MetricName": "tma_mispredicts_resteers",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -49,7 +49,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
- "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+ "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
"MetricName": "tma_clears_resteers",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -143,7 +143,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -159,7 +159,7 @@
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + (5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@) / SLOTS",
+ "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_backend_bound",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
@@ -167,7 +167,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -213,7 +213,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
+ "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -245,7 +245,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + L1D_PEND_MISS.FB_FULL_PERIODS)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l2_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
@@ -261,7 +261,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "((29 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + (23.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+ "MetricExpr": "(29 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 23.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -269,7 +269,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "(23.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+ "MetricExpr": "23.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -277,7 +277,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "(9 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+ "MetricExpr": "9 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -293,7 +293,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)",
+ "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -325,7 +325,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -333,7 +333,7 @@
},
{
"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "(32.5 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
+ "MetricExpr": "32.5 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
"MetricName": "tma_false_sharing",
"PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
@@ -395,7 +395,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
+ "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS)",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -508,7 +508,7 @@
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_retiring",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS",
@@ -625,7 +625,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "((tma_retiring * SLOTS) / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "tma_retiring * SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -655,19 +655,19 @@
},
{
"BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "Memory_Bandwidth"
},
{
"BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
"MetricGroup": "Mem;MemoryLat;Offcore",
"MetricName": "Memory_Latency"
},
{
"BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
+ "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
"MetricGroup": "Mem;MemoryTLB;Offcore",
"MetricName": "Memory_Data_TLBs"
},
@@ -697,13 +697,13 @@
},
{
"BriefDescription": "Uops Per Instruction",
- "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
+ "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Ret;Retire",
"MetricName": "UPI"
},
{
"BriefDescription": "Instruction per taken branch",
- "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW",
"MetricName": "UpTB"
},
@@ -727,7 +727,7 @@
},
{
"BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
- "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
+ "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
"MetricGroup": "SMT;tma_L1_group",
"MetricName": "Slots_Utilization"
},
@@ -746,26 +746,26 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "FP_Arith_Utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
- "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
+ "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
"MetricGroup": "Cor;SMT",
"MetricName": "Core_Bound_Likely"
},
@@ -813,13 +813,13 @@
},
{
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
"MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP"
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
"MetricGroup": "Flops;InsType",
"MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@@ -873,7 +873,7 @@
},
{
"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "(tma_retiring * SLOTS) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+ "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
"MetricGroup": "Pipeline;Ret",
"MetricName": "Retire"
},
@@ -927,7 +927,7 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts",
"MetricName": "Branch_Misprediction_Cost"
},
@@ -975,49 +975,49 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI_Load"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * ((OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
+ "MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
"MetricGroup": "CacheMisses;Mem;Offcore",
"MetricName": "L2MPKI_All"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2MPKI_Load"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_Load"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "FB_HPKI"
},
@@ -1030,25 +1030,25 @@
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "L3_Cache_Access_BW"
},
@@ -1078,19 +1078,19 @@
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -1124,7 +1124,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@@ -1142,68 +1142,89 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+ "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
+ {
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "UNC_CLOCK.SOCKET",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
+ },
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
+ {
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
+ },
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C8 residency percent per package",
- "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C8_Pkg_Residency"
+ "MetricName": "C8_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C9 residency percent per package",
- "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C9_Pkg_Residency"
+ "MetricName": "C9_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C10 residency percent per package",
- "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C10_Pkg_Residency"
+ "MetricName": "C10_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/memory.json b/tools/perf/pmu-events/arch/x86/icelake/memory.json
index a6f43cbc2d0a..e8d2ec1c029b 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/memory.json
@@ -1,565 +1,394 @@
[
{
"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x6"
},
{
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times HLE abort was triggered.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_EVENTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MEM",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of times an HLE execution successfully committed",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times HLE commit succeeded.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an HLE execution started.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.START",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00400",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC08000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00800",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data read requests that miss the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Number of times an RTM execution aborted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM abort was triggered.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM commit succeeded.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_READ",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times we could not allocate Lock Buffer.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x40"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf/pmu-events/arch/x86/icelake/other.json
index 3055710595c4..cfb590632918 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/other.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/other.json
@@ -1,374 +1,242 @@
[
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x18"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000400",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000400",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000010",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184008000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184008000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000800",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000800",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
index c74a7369cff3..3b31a842a0b1 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
@@ -1,703 +1,490 @@
[
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x9"
},
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "All branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all branch instructions retired.",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x11"
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts not taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x10"
},
{
"BriefDescription": "Taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x1"
},
{
"BriefDescription": "Far branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts far branch instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Indirect near branch instructions retired (excluding returns)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts both direct and indirect near call instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"BriefDescription": "Return instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts return instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"BriefDescription": "Taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x20"
},
{
"BriefDescription": "All mispredicted branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
"SampleAfterValue": "50021"
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts mispredicted conditional branch instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x11"
},
{
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
"SampleAfterValue": "50021",
"UMask": "0x10"
},
{
"BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x1"
},
{
"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
"SampleAfterValue": "50021",
"UMask": "0x80"
},
{
"BriefDescription": "Mispredicted indirect CALL instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
"SampleAfterValue": "50021",
"UMask": "0x2"
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
"SampleAfterValue": "50021",
"UMask": "0x20"
},
{
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"SampleAfterValue": "25003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PEBScounters": "34",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x3"
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
"SampleAfterValue": "25003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
- "SampleAfterValue": "2000003",
- "Speculative": "1"
+ "SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0xc"
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x5"
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "20",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x14"
},
{
"BriefDescription": "Total execution stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Number of all retired NOP instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.NOP",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles without actually retired instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts cycles without actually retired instructions.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x3"
},
{
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots where uops got dropped",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.UOP_DROPPING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "False dependencies due to partial compare on address.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.COUNT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of machine clears (nukes) of any type.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.LBR_INSERTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.PAUSE_INST",
"PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
@@ -706,422 +493,288 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SB",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SCOREBOARD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5e",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_END",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 3",
"EventName": "TOPDOWN.SLOTS",
- "PEBScounters": "35",
"PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.SLOTS_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UOPS_DECODED.DEC0",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Uops exclusively fetched by decoder 0",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_0",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 1",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of uops executed on port 2 and 3",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_2_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of uops executed on port 4 and 9",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_4_9",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Number of uops executed on port 5",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_5",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Number of uops executed on port 6",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_6",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Number of uops executed on port 7 and 8",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_7_8",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Number of uops executed on the core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops executed from any thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.THREAD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of x87 uops executed.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Uops that RAT issues to RS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Retirement slots used.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the retirement slots used each cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts cycles without actually retired uops.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "10",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json
index e007b976547d..f7aff8818f46 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json
@@ -1,31 +1,25 @@
[
{
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.",
- "Counter": "1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
- "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
- "Counter": "1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
- "PublicDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "UNC_CLOCK.SOCKET",
- "Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",
- "PublicDescription": "UNC_CLOCK.SOCKET",
"Unit": "CLOCK"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json
index 58809e16bf98..b28f62ce1f39 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json
@@ -1,245 +1,165 @@
[
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
"SampleAfterValue": "100007",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "STLB flush attempts",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
"SampleAfterValue": "100007",
- "Speculative": "1",
"UMask": "0x20"
}
]
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 15/32] perf vendor events intel: Refresh icelakex metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (4 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 14/32] perf vendor events intel: Refresh icelake " Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 16/32] perf vendor events intel: Refresh ivybridge " Ian Rogers
` (16 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the icelakex metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated to 1.17,
in particular uncore, with fixes to uncore events and improved
descriptions. The formatting changes increase consistency across the
json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/icelakex/cache.json | 316 +-
.../arch/x86/icelakex/floating-point.json | 28 -
.../arch/x86/icelakex/frontend.json | 140 -
.../arch/x86/icelakex/icx-metrics.json | 2192 +-
.../pmu-events/arch/x86/icelakex/memory.json | 139 +-
.../pmu-events/arch/x86/icelakex/other.json | 117 -
.../arch/x86/icelakex/pipeline.json | 344 +-
.../arch/x86/icelakex/uncore-memory.json | 1878 +-
.../arch/x86/icelakex/uncore-other.json | 45144 +++++++---------
.../arch/x86/icelakex/uncore-power.json | 115 +-
.../arch/x86/icelakex/virtual-memory.json | 88 -
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
12 files changed, 22074 insertions(+), 28429 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
index e4035b3e55ca..d6463c8d9462 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
@@ -1,1172 +1,868 @@
[
{
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of L1D misses that are outstanding",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "L2 cache lines filling L2",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1f"
},
{
"BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.NON_SILENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.SILENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "L2 code requests",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of L2 code requests.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe4"
},
{
"BriefDescription": "Demand Data Read requests",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe1"
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand requests that miss L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x27"
},
{
"BriefDescription": "RFO requests to L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe2"
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc4"
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x24"
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc1"
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x21"
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc2"
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x22"
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc8"
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x28"
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x41"
},
{
"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4f"
},
{
"BriefDescription": "Retired load instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
"SampleAfterValue": "1000003",
"UMask": "0x81"
},
{
"BriefDescription": "Retired store instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired store instructions.",
"SampleAfterValue": "1000003",
"UMask": "0x82"
},
{
"BriefDescription": "All retired memory instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ANY",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired memory instructions - loads and stores.",
"SampleAfterValue": "1000003",
"UMask": "0x83"
},
{
"BriefDescription": "Retired load instructions with locked access.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with locked access.",
"SampleAfterValue": "100007",
"UMask": "0x21"
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x41"
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x11"
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x12"
},
{
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
"SampleAfterValue": "20011",
"UMask": "0x4"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
+ "Deprecated": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
+ "Deprecated": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20011",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions whose data sources was remote HITM",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Retired load instructions whose data sources was remote HITM.",
"SampleAfterValue": "100007",
"UMask": "0x4"
},
{
- "BriefDescription": "Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
+ "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
"SampleAfterValue": "100007",
"UMask": "0x10"
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).",
"SampleAfterValue": "100007",
"UMask": "0x4"
},
{
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
"SampleAfterValue": "100021",
"UMask": "0x10"
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
"SampleAfterValue": "100021",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
"SampleAfterValue": "50021",
"UMask": "0x20"
},
{
- "BriefDescription": "Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
+ "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80082380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PREFETCHES.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C27F0",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1830000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Demand and prefetch data reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts memory transactions sent to the uncore.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Counts cacheable and non-cacheable code reads to the core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts both cacheable and non-cacheable code reads to the core.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles where at least 1 outstanding data read request is pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles with outstanding code read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding code read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles the queue waiting for offcore responses is full.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SQ_FULL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
index 1925388969bb..655342dadac6 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
@@ -1,100 +1,72 @@
[
{
"BriefDescription": "Counts all microcode FP assists.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.FP",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all microcode Floating Point assists.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
index eb27d9d9c8be..71498044f1cb 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
@@ -1,484 +1,344 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.COUNT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x11",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x14",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x500106",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
"MSRValue": "0x508006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
"MSRValue": "0x501006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x500206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
"MSRValue": "0x510006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x100206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
"MSRValue": "0x502006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
"MSRValue": "0x500406",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
"MSRValue": "0x520006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x504006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
"MSRValue": "0x500806",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x15",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles DSB is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of switches from DSB or MITE to the MS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x30"
},
{
"BriefDescription": "Uops delivered to IDQ while MS is busy",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x30"
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
index b52afc34a169..22b2a97d0ff8 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
@@ -1,1563 +1,1529 @@
[
{
- "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
- "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS",
- "MetricGroup": "PGO;TopdownL1;tma_L1_group",
- "MetricName": "tma_frontend_bound",
- "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+ "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "Mispredictions"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
- "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLOTS",
- "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_latency",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "Memory_Bandwidth"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
- "MetricExpr": "ICACHE_16B.IFDATA_STALL / CLKS",
- "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_icache_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))",
+ "MetricGroup": "Mem;MemoryLat;Offcore",
+ "MetricName": "Memory_Latency"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
- "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS",
- "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_itlb_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
+ "MetricGroup": "Mem;MemoryTLB;Offcore",
+ "MetricName": "Memory_Data_TLBs"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
- "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_branch_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
+ "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
+ "MetricGroup": "Ret",
+ "MetricName": "Branching_Overhead"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_mispredicts_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+ "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+ "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
+ "MetricName": "Big_Code"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
- "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_clears_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+ "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
+ "MetricGroup": "Fed;FetchBW;Frontend",
+ "MetricName": "Instruction_Fetch_BW"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
- "MetricExpr": "10 * BACLEARS.ANY / CLKS",
- "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_unknown_branches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+ "MetricExpr": "INST_RETIRED.ANY / CLKS",
+ "MetricGroup": "Ret;Summary",
+ "MetricName": "IPC"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
- "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_dsb_switches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uops Per Instruction",
+ "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "UPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
- "MetricExpr": "ILD_STALL.LCP / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_lcp",
- "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW",
+ "MetricName": "UpTB"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
- "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS",
- "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_ms_switches",
- "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+ "MetricExpr": "1 / IPC",
+ "MetricGroup": "Mem;Pipeline",
+ "MetricName": "CPI"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
- "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
- "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_bandwidth",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "Pipeline",
+ "MetricName": "CLKS"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
- "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_mite",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+ "MetricExpr": "TOPDOWN.SLOTS",
+ "MetricGroup": "tma_L1_group",
+ "MetricName": "SLOTS"
},
{
- "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
- "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
- "MetricName": "tma_decoder0_alone",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
+ "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
+ "MetricGroup": "SMT;tma_L1_group",
+ "MetricName": "Slots_Utilization"
},
{
- "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline",
- "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / CLKS",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
- "MetricName": "tma_mite_4wide",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of Executed- by Issued-Uops",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+ "MetricGroup": "Cor;Pipeline",
+ "MetricName": "Execute_per_Issue",
+ "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
- "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2",
- "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_dsb",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+ "MetricGroup": "Ret;SMT;tma_L1_group",
+ "MetricName": "CoreIPC"
},
{
- "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_bad_speculation",
- "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Floating Point Operations Per Cycle",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricGroup": "Flops;Ret",
+ "MetricName": "FLOPc"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_branch_mispredicts",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "FP_Arith_Utilization",
+ "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
- "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
- "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_machine_clears",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+ "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+ "MetricName": "ILP"
},
{
- "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + (5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@) / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_backend_bound",
- "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+ "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "Core_Bound_Likely"
},
{
- "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
- "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_memory_bound",
- "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+ "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "SMT",
+ "MetricName": "CORE_CLKS"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
- "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l1_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+ "MetricGroup": "InsType",
+ "MetricName": "IpLoad"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
- "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_dtlb_load",
- "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+ "MetricGroup": "InsType",
+ "MetricName": "IpStore"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Fed;InsType",
+ "MetricName": "IpBranch"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "IpCall"
},
{
- "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
- "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_store_fwd_blk",
- "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+ "MetricName": "IpTB"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
- "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_lock_latency",
- "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch instructions per taken branch. ",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "BpTkBranch"
},
{
- "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
- "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_split_loads",
- "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpFLOP"
},
{
- "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
- "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_4k_aliasing",
- "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpArith",
+ "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
},
{
- "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
- "MetricExpr": "L1D_PEND_MISS.FB_FULL / CLKS",
- "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_fb_full",
- "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_SP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + L1D_PEND_MISS.FB_FULL_PERIODS)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l2_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_DP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l3_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX128",
+ "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "((44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (43.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_contested_accesses",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX256",
+ "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "(43.5 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_data_sharing",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX512",
+ "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "(19 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_l3_hit_latency",
- "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+ "MetricGroup": "Prefetches",
+ "MetricName": "IpSWPF"
},
{
- "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "L1D_PEND_MISS.L2_STALL / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_sq_full",
- "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+ "MetricExpr": "INST_RETIRED.ANY",
+ "MetricGroup": "Summary;tma_L1_group",
+ "MetricName": "Instructions"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound) - tma_pmm_bound)",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_dram_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
- "ScaleUnit": "100%"
- },
- {
- "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_bandwidth",
- "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+ "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "Retire"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_latency",
- "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+ "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+ "MetricName": "Execute"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
- "MetricExpr": "(43.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_local_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+ "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "Fetch_UpC"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
- "MetricExpr": "(108 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+ "MetricGroup": "DSB;Fed;FetchBW",
+ "MetricName": "DSB_Coverage"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
- "MetricExpr": "((97 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (97 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_cache",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
+ "MetricGroup": "DSBmiss",
+ "MetricName": "DSB_Switch_Cost"
},
{
- "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
- "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) / ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)) if (1000000 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS) else 0)",
- "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_pmm_bound",
- "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
+ "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "DSB_Misses"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
- "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_store_bound",
- "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "IpDSB_Miss_Ret"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_store_latency",
- "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "IpMispredict"
},
{
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "(48 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "Branch_Misprediction_Cost"
},
{
- "BriefDescription": "This metric represents rate of split store accesses",
- "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
- "MetricGroup": "TopdownL4;tma_store_bound_group",
- "MetricName": "tma_split_stores",
- "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are non-taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_NT"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
- "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_streaming_stores",
- "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_TK"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
- "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_dtlb_store",
- "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are CALL or RET",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "CallRet"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "Jump"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
+ "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "Other_Branches"
},
{
- "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
- "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
- "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_core_bound",
- "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
+ "MetricGroup": "Mem;MemoryBound;MemoryLat",
+ "MetricName": "Load_Miss_Real_Latency"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
- "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS",
- "MetricGroup": "TopdownL3;tma_core_bound_group",
- "MetricName": "tma_divider",
- "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
- "ScaleUnit": "100%"
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+ "MetricGroup": "Mem;MemoryBW;MemoryBound",
+ "MetricName": "MLP"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
- "MetricName": "tma_ports_utilization",
- "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_0",
- "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
- "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_serializing_operation",
- "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Backend;CacheMisses;Mem",
+ "MetricName": "L2MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions",
- "MetricExpr": "37 * MISC_RETIRED.PAUSE_INST / CLKS",
- "MetricGroup": "TopdownL6;tma_serializing_operation_group",
- "MetricName": "tma_slow_pause",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
+ "MetricGroup": "CacheMisses;Mem;Offcore",
+ "MetricName": "L2MPKI_All"
},
{
- "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
- "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_mixing_vectors",
- "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2MPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_1",
- "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_2",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL",
- "ScaleUnit": "100%"
+ "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L3MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_3m",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "FB_HPKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_alu_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+ "MetricConstraint": "NO_NMI_WATCHDOG",
+ "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * CORE_CLKS)",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "Page_Walks_Utilization"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED.PORT_0",
- "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CORE_CLKS",
- "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_0",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED.PORT_1",
- "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_1",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
- "MetricExpr": "UOPS_DISPATCHED.PORT_5 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_5",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED.PORT_6",
- "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_6",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
- "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_load_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+ "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_Silent_PKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8",
- "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_store_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+ "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_NonSilent_PKI"
},
{
- "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_retiring",
- "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "L1D_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
- "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_light_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "L2_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
- "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
- "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_fp_arith",
- "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
- "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
- "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_x87_use",
- "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Access_BW",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW_1T"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_scalar",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average CPU Utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricGroup": "HPC;Summary",
+ "MetricName": "CPU_Utilization"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_vector",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+ "MetricGroup": "Power;Summary",
+ "MetricName": "Average_Frequency"
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_128b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Giga Floating Point Operations Per Second",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "GFLOPs",
+ "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_256b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+ "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricGroup": "Power",
+ "MetricName": "Turbo_Utilization"
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_512b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
+ "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License0_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
- "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_memory_operations",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
+ "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License1_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.",
- "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * SLOTS)",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_branch_instructions",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
+ "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License2_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions."
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
- "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * SLOTS)",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_nop_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
+ "MetricGroup": "SMT",
+ "MetricName": "SMT_2T_Utilization"
},
{
- "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
- "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_other_light_ops",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_Utilization"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
- "MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=1@) / IDQ.MITE_UOPS",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_heavy_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_CPI"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
- "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
- "MetricGroup": "TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_few_uops_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "DRAM_BW_Use"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "((tma_retiring * SLOTS) / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
- "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_microcode_sequencer",
- "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
},
{
- "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
- "MetricExpr": "100 * ASSISTS.ANY / SLOTS",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_assists",
- "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
- "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_cisc",
- "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=0x0@",
+ "MetricGroup": "Mem;MemoryLat;Server;SoC",
+ "MetricName": "MEM_PMM_Read_Latency"
},
{
- "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
- "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "Mispredictions"
+ "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@event\\=0x0@",
+ "MetricGroup": "Mem;MemoryLat;Server;SoC",
+ "MetricName": "MEM_DRAM_Read_Latency"
},
{
- "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "Memory_Bandwidth"
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
+ "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Server;SoC",
+ "MetricName": "PMM_Read_BW"
},
{
- "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)))",
- "MetricGroup": "Mem;MemoryLat;Offcore",
- "MetricName": "Memory_Latency"
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Server;SoC",
+ "MetricName": "PMM_Write_BW"
},
{
- "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
- "MetricGroup": "Mem;MemoryTLB;Offcore",
- "MetricName": "Memory_Data_TLBs"
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;Mem;Server;SoC",
+ "MetricName": "IO_Write_BW"
},
{
- "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
- "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
- "MetricGroup": "Ret",
- "MetricName": "Branching_Overhead"
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;Mem;Server;SoC",
+ "MetricName": "IO_Read_BW"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
- "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
- "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
- "MetricName": "Big_Code"
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "cha_0@event\\=0x0@",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
- "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
- "MetricGroup": "Fed;FetchBW;Frontend",
- "MetricName": "Instruction_Fetch_BW"
+ "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+ "MetricGroup": "Branches;OS",
+ "MetricName": "IpFarBranch"
},
{
- "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
- "MetricExpr": "INST_RETIRED.ANY / CLKS",
- "MetricGroup": "Ret;Summary",
- "MetricName": "IPC"
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
},
{
- "BriefDescription": "Uops Per Instruction",
- "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;Ret;Retire",
- "MetricName": "UPI"
+ "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricName": "cpu_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW",
- "MetricName": "UpTB"
+ "BriefDescription": "CPU operating frequency (in GHz)",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+ "MetricName": "cpu_operating_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
- "MetricExpr": "1 / IPC",
- "MetricGroup": "Mem;Pipeline",
- "MetricName": "CPI"
+ "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+ "MetricName": "cpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "Pipeline",
- "MetricName": "CLKS"
+ "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+ "MetricName": "loads_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
- "MetricExpr": "TOPDOWN.SLOTS",
- "MetricGroup": "tma_L1_group",
- "MetricName": "SLOTS"
+ "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+ "MetricName": "stores_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
- "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
- "MetricGroup": "SMT;tma_L1_group",
- "MetricName": "Slots_Utilization"
+ "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+ "MetricName": "l1d_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "The ratio of Executed- by Issued-Uops",
- "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
- "MetricGroup": "Cor;Pipeline",
- "MetricName": "Execute_per_Issue",
- "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+ "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+ "MetricName": "l1d_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
- "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
- "MetricGroup": "Ret;SMT;tma_L1_group",
- "MetricName": "CoreIPC"
+ "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+ "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
- "MetricGroup": "Flops;Ret",
- "MetricName": "FLOPc"
+ "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "FP_Arith_Utilization",
- "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+ "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+ "MetricName": "l2_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
- "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
- "MetricName": "ILP"
+ "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
- "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
- "MetricGroup": "Cor;SMT",
- "MetricName": "Core_Bound_Likely"
+ "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_code_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
- "MetricGroup": "SMT",
- "MetricName": "CORE_CLKS"
+ "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY",
+ "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
- "MetricGroup": "InsType",
- "MetricName": "IpLoad"
+ "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY",
+ "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
- "MetricGroup": "InsType",
- "MetricName": "IpStore"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Branches;Fed;InsType",
- "MetricName": "IpBranch"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "IpCall"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
- "MetricName": "IpTB"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Branch instructions per taken branch. ",
- "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "BpTkBranch"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_to_dram_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpFLOP"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "itlb_2nd_level_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpArith",
- "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "itlb_2nd_level_large_page_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_SP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_DP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX128",
- "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_store_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX256",
- "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+ "MetricName": "numa_reads_addressed_to_local_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX512",
- "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+ "MetricName": "numa_reads_addressed_to_remote_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
- "MetricGroup": "Prefetches",
- "MetricName": "IpSWPF"
+ "BriefDescription": "Uncore operating frequency in GHz",
+ "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
+ "MetricName": "uncore_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
- "MetricExpr": "INST_RETIRED.ANY",
- "MetricGroup": "Summary;tma_L1_group",
- "MetricName": "Instructions"
+ "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+ "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+ "MetricName": "upi_data_transmit_bw",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "(tma_retiring * SLOTS) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
- "MetricGroup": "Pipeline;Ret",
- "MetricName": "Retire"
+ "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "",
- "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
- "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
- "MetricName": "Execute"
+ "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Average number of Uops issued by front-end when it issued something",
- "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
- "MetricGroup": "Fed;FetchBW",
- "MetricName": "Fetch_UpC"
+ "BriefDescription": "DDR memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
- "MetricGroup": "DSB;Fed;FetchBW",
- "MetricName": "DSB_Coverage"
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
- "MetricGroup": "DSBmiss",
- "MetricName": "DSB_Switch_Cost"
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
- "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "DSB_Misses"
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "IpDSB_Miss_Ret"
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR + UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_writes",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "IpMispredict"
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_reads",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BrMispredicts",
- "MetricName": "Branch_Misprediction_Cost"
+ "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_decoded_icache",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are non-taken conditionals",
- "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_NT"
+ "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are taken conditionals",
- "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_TK"
+ "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are CALL or RET",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "CallRet"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "Jump"
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
- "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
- "MetricGroup": "Bad;Branches",
- "MetricName": "Other_Branches"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
- "MetricGroup": "Mem;MemoryBound;MemoryLat",
- "MetricName": "Load_Miss_Real_Latency"
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
- "MetricGroup": "Mem;MemoryBW;MemoryBound",
- "MetricName": "MLP"
+ "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+ "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots",
+ "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_frontend_bound",
+ "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+ "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots",
+ "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_latency",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI_Load"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+ "MetricExpr": "ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_icache_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "Backend;CacheMisses;Mem",
- "MetricName": "L2MPKI"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+ "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_itlb_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * ((OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
- "MetricGroup": "CacheMisses;Mem;Offcore",
- "MetricName": "L2MPKI_All"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+ "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_branch_resteers",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2MPKI_Load"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_mispredicts_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_Load"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+ "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_clears_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L3MPKI"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+ "MetricExpr": "10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_unknown_branches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "FB_HPKI"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_dsb_switches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
- "MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * CORE_CLKS)",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "Page_Walks_Utilization"
+ "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+ "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_lcp",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+ "MetricExpr": "3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_ms_switches",
+ "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+ "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
+ "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_bandwidth",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+ "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_mite",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+ "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+ "MetricName": "tma_decoder0_alone",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW"
+ "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline",
+ "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=0x4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=0x5@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+ "MetricName": "tma_mite_4wide",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
- "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_Silent_PKI"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+ "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_dsb",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
- "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_NonSilent_PKI"
+ "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+ "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_bad_speculation",
+ "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "L1D_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_branch_mispredicts",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "L2_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+ "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_machine_clears",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW_1T"
+ "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+ "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ / slots",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_backend_bound",
+ "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Access_BW",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW_1T"
+ "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
+ "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_memory_bound",
+ "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
- "MetricGroup": "HPC;Summary",
- "MetricName": "CPU_Utilization"
+ "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+ "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l1_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
- "MetricGroup": "Power;Summary",
- "MetricName": "Average_Frequency"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+ "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_dtlb_load",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "GFLOPs",
- "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average Frequency Utilization relative nominal frequency",
- "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
- "MetricGroup": "Power",
- "MetricName": "Turbo_Utilization"
+ "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
- "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License0_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
+ "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+ "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_store_fwd_blk",
+ "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
- "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License1_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
+ "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+ "MetricExpr": "min((16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_lock_latency",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
- "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License2_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions."
+ "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+ "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_split_loads",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
- "MetricGroup": "SMT",
- "MetricName": "SMT_2T_Utilization"
+ "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+ "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_4k_aliasing",
+ "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "OS",
- "MetricName": "Kernel_Utilization"
+ "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+ "MetricExpr": "L1D_PEND_MISS.FB_FULL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_fb_full",
+ "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
- "MetricGroup": "OS",
- "MetricName": "Kernel_CPI"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l2_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC",
- "MetricName": "DRAM_BW_Use"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l3_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
- "MetricGroup": "Mem;MemoryLat;SoC",
- "MetricName": "MEM_Read_Latency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+ "MetricExpr": "min(((48 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_contested_accesses",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@event\\=0x36\\,umask\\=0xC817FE01\\,thresh\\=1@",
- "MetricGroup": "Mem;MemoryBW;SoC",
- "MetricName": "MEM_Parallel_Reads"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+ "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_data_sharing",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
- "MetricExpr": "(1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=0x0@)",
- "MetricGroup": "Mem;MemoryLat;Server;SoC",
- "MetricName": "MEM_PMM_Read_Latency"
+ "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+ "MetricExpr": "min((23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_l3_hit_latency",
+ "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
- "MetricExpr": " 1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@event\\=0x0@",
- "MetricGroup": "Mem;MemoryLat;Server;SoC",
- "MetricName": "MEM_DRAM_Read_Latency"
+ "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+ "MetricExpr": "L1D_PEND_MISS.L2_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_sq_full",
+ "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
- "MetricExpr": "((64 * imc@event\\=0xe3@ / 1000000000) / duration_time)",
- "MetricGroup": "Mem;MemoryBW;Server;SoC",
- "MetricName": "PMM_Read_BW"
+ "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+ "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound - min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1), 1)",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_dram_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
- "MetricExpr": "((64 * imc@event\\=0xe7@ / 1000000000) / duration_time)",
- "MetricGroup": "Mem;MemoryBW;Server;SoC",
- "MetricName": "PMM_Write_BW"
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_bandwidth",
+ "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
- "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000000 / duration_time",
- "MetricGroup": "IoBW;Mem;Server;SoC",
- "MetricName": "IO_Write_BW"
+ "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_latency",
+ "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
- "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1000000000 / duration_time",
- "MetricGroup": "IoBW;Mem;Server;SoC",
- "MetricName": "IO_Read_BW"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+ "MetricExpr": "min((66.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_local_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Socket actual clocks when any core is active on that socket",
- "MetricExpr": "cha_0@event\\=0x0@",
- "MetricGroup": "SoC",
- "MetricName": "Socket_CLKS"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+ "MetricExpr": "min((131 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
- "MetricGroup": "Branches;OS",
- "MetricName": "IpFarBranch"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+ "MetricExpr": "min(((120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_cache",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C1 residency percent per core",
- "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C1_Core_Residency"
+ "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
+ "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)",
+ "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_pmm_bound",
+ "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+ "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_store_bound",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_store_latency",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+ "MetricExpr": "min(48 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_false_sharing",
+ "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "BriefDescription": "This metric represents rate of split store accesses",
+ "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_split_stores",
+ "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "CPU operating frequency (in GHz)",
- "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "cpu_operating_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
+ "MetricExpr": "min(9 * OCR.STREAMING_WR.ANY_RESPONSE / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_streaming_stores",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "loads_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+ "MetricExpr": "min((7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CPU_CLK_UNHALTED.DISTRIBUTED, 1)",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_dtlb_store",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "stores_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+ "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
+ "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_core_bound",
+ "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+ "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_divider",
+ "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+ "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) + 0 * slots",
+ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_ports_utilization",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CPU_CLK_UNHALTED.THREAD + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_0",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+ "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_serializing_operation",
+ "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.",
+ "MetricExpr": "37 * MISC_RETIRED.PAUSE_INST / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group",
+ "MetricName": "tma_slow_pause",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_code_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_mixing_vectors",
+ "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_1",
+ "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_2",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+ "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_3m",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+ "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_alu_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_0",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_1",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_to_dram_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_5 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_5",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_2nd_level_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_6",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_2nd_level_large_page_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_load_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2nd_level_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+ "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_store_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_retiring",
+ "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2nd_level_store_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+ "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - tma_heavy_operations)",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_light_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_local_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector",
+ "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fp_arith",
+ "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_remote_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + 0 * slots",
+ "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_x87_use",
+ "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore operating frequency in GHz",
- "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "uncore_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_scalar",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
- "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "upi_data_transmit_bw",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_vector",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_128b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_256b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_512b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+ "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_memory_operations",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.",
+ "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_branch_instructions",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+ "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_nop_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
- "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR + UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_writes",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+ "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_other_light_ops",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
- "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_reads",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+ "MetricExpr": "tma_microcode_sequencer + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@) / IDQ.MITE_UOPS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_heavy_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_decoded_icache",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+ "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_few_uops_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots / UOPS_ISSUED.ANY * IDQ.MS_UOPS / slots",
+ "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_microcode_sequencer",
+ "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_microcode_sequencer",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+ "MetricExpr": "min(100 * ASSISTS.ANY / slots, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_assists",
+ "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+ "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_cisc",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C1 residency percent per core",
+ "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C1_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_remote_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C6 residency percent per core",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_remote_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C2 residency percent per package",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "%",
- "MetricExpr": "100 * ( ( LSD.CYCLES_ACTIVE - LSD.CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )",
- "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
- "MetricName": "tma_lsd",
- "ScaleUnit": "1%"
+ "BriefDescription": "C6 residency percent per package",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
index 48e8d1102b9d..f36ac04f8d76 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
@@ -1,549 +1,414 @@
[
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x6"
},
{
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F04400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94002380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84002380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ITOM.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PREFETCHES.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F844027F0",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC00477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F04400477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70CC00477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data read requests that miss the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
- "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Number of times an RTM execution aborted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM abort was triggered.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM commit succeeded.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_READ",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json
index 919e620e7db8..63d5faf2fc43 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json
@@ -1,576 +1,459 @@
[
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x18"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Hit snoop reply with data, line invalidated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.I_FWD_FE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x20"
},
{
"BriefDescription": "HitM snoop reply with data, line invalidated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.I_FWD_M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Hit snoop reply without sending the data, line invalidated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.I_HIT_FSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Line not found snoop reply",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Hit snoop reply with data, line kept in Shared state.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.S_FWD_FE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "HitM snoop reply with data, line kept in Shared state",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.S_FWD_M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Hit snoop reply without sending the data, line kept in Shared state.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.S_HIT_FSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703C00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703C00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch (which bring data to L2) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10070",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x12380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90002380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ITOM.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70C000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700C00477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F33000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x731800477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.WRITE_ESTIMATE.MEMORY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFBFF80822",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
index 52fba238bf1f..4cf16a1fcad4 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
@@ -1,701 +1,489 @@
[
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x9"
},
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "All branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all branch instructions retired.",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x11"
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts not taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x10"
},
{
"BriefDescription": "Taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x1"
},
{
"BriefDescription": "Far branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts far branch instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Indirect near branch instructions retired (excluding returns)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts both direct and indirect near call instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"BriefDescription": "Return instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts return instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"BriefDescription": "Taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x20"
},
{
"BriefDescription": "All mispredicted branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
"SampleAfterValue": "50021"
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts mispredicted conditional branch instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x11"
},
{
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
"SampleAfterValue": "50021",
"UMask": "0x10"
},
{
"BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x1"
},
{
"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
"SampleAfterValue": "50021",
"UMask": "0x80"
},
{
"BriefDescription": "Mispredicted indirect CALL instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect.",
"SampleAfterValue": "50021",
"UMask": "0x2"
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
"SampleAfterValue": "50021",
"UMask": "0x20"
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x8"
},
{
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"SampleAfterValue": "25003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PEBScounters": "34",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x3"
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
"SampleAfterValue": "25003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
- "SampleAfterValue": "2000003",
- "Speculative": "1"
+ "SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0xc"
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x5"
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "20",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x14"
},
{
"BriefDescription": "Total execution stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Number of all retired NOP instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.NOP",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x3"
},
{
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots where uops got dropped",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.UOP_DROPPING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "False dependencies due to partial compare on address.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.COUNT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of machine clears (nukes) of any type.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.LBR_INSERTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.PAUSE_INST",
"PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
@@ -704,399 +492,273 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SB",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SCOREBOARD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5e",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_END",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 3",
"EventName": "TOPDOWN.SLOTS",
- "PEBScounters": "35",
"PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.SLOTS_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UOPS_DECODED.DEC0",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Uops exclusively fetched by decoder 0",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_0",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 1",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of uops executed on port 2 and 3",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_2_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of uops executed on port 4 and 9",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_4_9",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Number of uops executed on port 5",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_5",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Number of uops executed on port 6",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_6",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Number of uops executed on port 7 and 8",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_7_8",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.THREAD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of x87 uops executed.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Uops that RAT issues to RS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
+ "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Retirement slots used.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the retirement slots used each cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts cycles without actually retired uops.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "10",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.",
+ "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
}
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
index 6872ae4b29d9..0d495ae53f3d 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
@@ -1,1856 +1,1546 @@
[
{
- "BriefDescription": "2LM Tag Check : Hit in Near Memory Cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.HIT",
+ "BriefDescription": "DRAM Activate Count : All Activates",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_ACT_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "2LM Tag Check : Miss, no data in this line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
+ "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
+ "BriefDescription": "All DRAM CAS commands issued",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
+ "UMask": "0x3f",
"Unit": "iMC"
},
{
- "BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.NM_RD_HIT",
+ "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills.",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.NM_WR_HIT",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with explicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to read",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.RD",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.WR",
+ "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the total number of DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM underfill read CAS commands issued",
"EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD",
+ "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x0f",
+ "PublicDescription": "Counts the total of DRAM Read CAS commands issued due to an underfill",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "All DRAM write CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
"UMask": "0x30",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
"EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.ALL",
- "PerPkg": "1",
- "UMask": "0x3f",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+ "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.WR_PRE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS.PCH0",
+ "BriefDescription": "DRAM Clockticks",
+ "EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS.PCH1",
+ "BriefDescription": "Free running counter that increments for the Memory Controller",
+ "EventName": "UNC_M_CLOCKTICKS_FREERUN",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS.PCH0",
+ "BriefDescription": "DRAM Precharge All Commands",
+ "EventCode": "0x44",
+ "EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent.",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS.PCH1",
+ "BriefDescription": "Number of DRAM Refreshes Issued",
+ "EventCode": "0x45",
+ "EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.PGT",
+ "BriefDescription": "Number of DRAM Refreshes Issued",
+ "EventCode": "0x45",
+ "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventName": "UNC_M_CLOCKTICKS",
+ "BriefDescription": "Number of DRAM Refreshes Issued",
+ "EventCode": "0x45",
+ "EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
+ "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Half clockticks for IMC",
- "Counter": "FIXED",
- "CounterType": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_M_HCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
+ "BriefDescription": "UNC_M_PARITY_ERRORS",
+ "EventCode": "0x2c",
+ "EventName": "UNC_M_PARITY_ERRORS",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
+ "BriefDescription": "UNC_M_PCLS.RD",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_PCLS.RD",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
+ "BriefDescription": "UNC_M_PCLS.TOTAL",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_PCLS.TOTAL",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
+ "BriefDescription": "UNC_M_PCLS.WR",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_PCLS.WR",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count : All Activates",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M_ACT_COUNT.ALL",
+ "BriefDescription": "PMM Commands : All",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.ALL",
"PerPkg": "1",
- "UMask": "0x0B",
+ "PublicDescription": "PMM Commands : All : Counts all commands issued to PMM",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.ALL",
+ "BriefDescription": "PMM Commands : Misc Commands (error, flow ACKs)",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.MISC",
"PerPkg": "1",
- "UMask": "0x1C",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
+ "BriefDescription": "PMM Commands : Misc GNTs",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M_PMM_RPQ_INSERTS",
+ "BriefDescription": "PMM Commands : Reads - RPQ",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.RD",
"PerPkg": "1",
+ "PublicDescription": "PMM Commands : Reads - RPQ : Counts read requests issued to the PMM RPQ",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE7",
- "EventName": "UNC_M_PMM_WPQ_INSERTS",
+ "BriefDescription": "PMM Commands : RPQ GNTs",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
"PerPkg": "1",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "PMM Commands : Underfill reads",
"EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.ALL",
+ "EventName": "UNC_M_PMM_CMD1.UFILL_RD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PMM Commands : Underfill reads : Counts underfill read commands, due to a partial write, issued to PMM",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Reads - RPQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "PMM Commands : Underfill GNTs",
"EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.RD",
+ "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands : Writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.WR",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "PMM Commands : Writes : Counts write commands issued to PMM",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Underfill reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.UFILL_RD",
+ "BriefDescription": "PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding)",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
+ "BriefDescription": "PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP)",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M_RDB_INSERTS",
+ "BriefDescription": "PMM Commands - Part 2 : Opportunistic Reads",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.OPP_RD",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Accepted",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.ACCEPTS",
+ "BriefDescription": "PMM Commands - Part 2 : ECC Errors",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
"PerPkg": "1",
- "UMask": "0x05",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Rejected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.REJECTS",
+ "BriefDescription": "PMM Commands - Part 2 : ERID detectable parity error",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
"PerPkg": "1",
- "UMask": "0x0A",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_REG",
+ "BriefDescription": "PMM Commands - Part 2",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.PMM_ERID_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM underfill read CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 0",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M_ACT_COUNT.BYP",
+ "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 1",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
+ "BriefDescription": "PMM Read Queue Cycles Full",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
+ "BriefDescription": "PMM Read Queue Cycles Not Empty",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.WR_PRE",
+ "BriefDescription": "PMM Read Queue Inserts",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M_PMM_RPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "PMM Read Queue Inserts : Counts number of read requests allocated in the PMM Read Pending Queue. This includes both ISOCH and non-ISOCH requests.",
"Unit": "iMC"
},
{
- "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
+ "BriefDescription": "PMM Write Queue Cycles Full",
+ "EventCode": "0xE6",
+ "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "iMC"
},
{
- "BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
+ "BriefDescription": "PMM Write Queue Cycles Not Empty",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
+ "BriefDescription": "UNC_M_PMM_WPQ_FLUSH",
+ "EventCode": "0xe8",
+ "EventName": "UNC_M_PMM_WPQ_FLUSH",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
+ "BriefDescription": "UNC_M_PMM_WPQ_FLUSH_CYC",
+ "EventCode": "0xe9",
+ "EventName": "UNC_M_PMM_WPQ_FLUSH_CYC",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
+ "BriefDescription": "PMM Write Queue Inserts",
+ "EventCode": "0xE7",
+ "EventName": "UNC_M_PMM_WPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PMM Write Queue Inserts : Counts number of write requests allocated in the PMM Write Pending Queue.",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
+ "BriefDescription": "PMM Write Pending Queue Occupancy",
+ "EventCode": "0xE4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
+ "BriefDescription": "PMM Write Pending Queue Occupancy",
+ "EventCode": "0xE4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Read Accepts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
+ "BriefDescription": "PMM Write Pending Queue Occupancy",
+ "EventCode": "0xE4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Read Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
+ "BriefDescription": "Channel PPD Cycles",
+ "EventCode": "0x85",
+ "EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : NM read completions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : NM write completions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : FM read completions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : FM write completions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Write Accepts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
+ "BriefDescription": "Throttle Cycles for Rank 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Write Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
+ "BriefDescription": "Throttle Cycles for Rank 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Alloc",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.ALLOC",
+ "BriefDescription": "Clock-Enabled Self-Refresh",
+ "EventCode": "0x43",
+ "EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Dealloc",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.DEALLOC",
+ "BriefDescription": "Throttle Cycles for Rank 0",
+ "EventCode": "0x46",
+ "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Reject",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.VLD",
+ "BriefDescription": "Throttle Cycles for Rank 0",
+ "EventCode": "0x46",
+ "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
+ "BriefDescription": "DRAM Precharge commands.",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x1c",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to page miss",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests)",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.PGT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to read",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.FMTGRWR_STARVED",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.RDS",
+ "BriefDescription": "Read Data Buffer Full",
+ "EventCode": "0x19",
+ "EventName": "UNC_M_RDB_FULL",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.WRS",
+ "BriefDescription": "Read Data Buffer Inserts",
+ "EventCode": "0x17",
+ "EventName": "UNC_M_RDB_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Block region reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
+ "BriefDescription": "Read Data Buffer Not Empty",
+ "EventCode": "0x18",
+ "EventName": "UNC_M_RDB_NOT_EMPTY",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Block region writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
+ "BriefDescription": "Read Data Buffer Occupancy",
+ "EventCode": "0x1A",
+ "EventName": "UNC_M_RDB_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.RDS",
+ "BriefDescription": "Read Pending Queue Full Cycles",
+ "EventCode": "0x12",
+ "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Block region reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
+ "BriefDescription": "Read Pending Queue Full Cycles",
+ "EventCode": "0x15",
+ "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Block region writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
+ "BriefDescription": "Read Pending Queue Not Empty",
+ "EventCode": "0x11",
+ "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
+ "BriefDescription": "Read Pending Queue Not Empty",
+ "EventCode": "0x11",
+ "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS.PCH0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS.PCH1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.CANARY",
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x80",
+ "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NMRD",
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x81",
+ "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FMRD",
+ "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Accepted",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.ACCEPTS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NMWR",
+ "EventCode": "0xd2",
+ "EventName": "UNC_M_SB_ACCESSES.FMRD_CMPS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FMWR",
+ "EventCode": "0xd2",
+ "EventName": "UNC_M_SB_ACCESSES.FMWR_CMPS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FMTGR",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.NMRD",
+ "BriefDescription": "Scoreboard Accesses : Write Accepts",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FMRD",
+ "BriefDescription": "Scoreboard Accesses : Write Rejects",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.NMWR",
+ "EventCode": "0xd2",
+ "EventName": "UNC_M_SB_ACCESSES.NMRD_CMPS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FMWR",
+ "EventCode": "0xd2",
+ "EventName": "UNC_M_SB_ACCESSES.NMWR_CMPS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FMTGR",
+ "BriefDescription": "Scoreboard Accesses : FM read completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.NMRD",
+ "BriefDescription": "Scoreboard Accesses : FM write completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.FMRD",
+ "BriefDescription": "Scoreboard Accesses : Read Accepts",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.NMWR",
+ "BriefDescription": "Scoreboard Accesses : Read Rejects",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.FMWR",
+ "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Rejected",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.REJECTS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.FMTGR",
+ "BriefDescription": "Scoreboard Accesses : NM read completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.NEW",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.NEW",
+ "BriefDescription": "Scoreboard Accesses : NM write completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.RD_HIT",
+ "BriefDescription": ": Alloc",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.ALLOC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.RD_MISS",
+ "BriefDescription": ": Dealloc",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.DEALLOC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.OCC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.OCC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.FMTGRWR_STARVED",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
+ "BriefDescription": ": Near Mem Write Starved",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
+ "BriefDescription": ": Far Mem Write Starved",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
+ "BriefDescription": ": Far Mem Read Starved",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PCLS.RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M_PCLS.RD",
+ "BriefDescription": ": Valid",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PCLS.WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M_PCLS.WR",
+ "BriefDescription": ": Near Mem Read Starved",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PCLS.TOTAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M_PCLS.TOTAL",
+ "BriefDescription": ": Reject",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.VLD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Inserts : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDA",
- "EventName": "UNC_M_SB_PREF_INSERTS.ALL",
+ "BriefDescription": "Scoreboard Cycles Full",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M_SB_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Occupancy : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDB",
- "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL",
+ "BriefDescription": "Scoreboard Cycles Not-Empty",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M_SB_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP",
+ "BriefDescription": "Scoreboard Inserts : Block region reads",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M_DRAM_PRE_ALL",
+ "BriefDescription": "Scoreboard Inserts : Block region writes",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
"PerPkg": "1",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PARITY_ERRORS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2c",
- "EventName": "UNC_M_PARITY_ERRORS",
+ "BriefDescription": "Scoreboard Inserts : Persistent Mem reads",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Channel PPD Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M_POWER_CHANNEL_PPD",
+ "BriefDescription": "Scoreboard Inserts : Persistent Mem writes",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
"PerPkg": "1",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Clock-Enabled Self-Refresh",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M_POWER_SELF_REFRESH",
+ "BriefDescription": "Scoreboard Inserts : Reads",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.RDS",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M_RDB_FULL",
+ "BriefDescription": "Scoreboard Inserts : Writes",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.WRS",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M_RDB_NOT_EMPTY",
+ "BriefDescription": "Scoreboard Occupancy : Block region reads",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
"PerPkg": "1",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1A",
- "EventName": "UNC_M_RDB_OCCUPANCY",
+ "BriefDescription": "Scoreboard Occupancy : Block region writes",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
"PerPkg": "1",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
+ "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
+ "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
"PerPkg": "1",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M_SB_CYCLES_FULL",
+ "BriefDescription": "Scoreboard Occupancy : Reads",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.RDS",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Cycles Not-Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M_SB_CYCLES_NE",
+ "BriefDescription": "Scoreboard Prefetch Inserts : All",
+ "EventCode": "0xDA",
+ "EventName": "UNC_M_SB_PREF_INSERTS.ALL",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
+ "BriefDescription": "Scoreboard Prefetch Inserts : DDR4",
+ "EventCode": "0xDA",
+ "EventName": "UNC_M_SB_PREF_INSERTS.DDR",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
+ "BriefDescription": "Scoreboard Prefetch Inserts : Persistent Mem",
+ "EventCode": "0xDA",
+ "EventName": "UNC_M_SB_PREF_INSERTS.PMM",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
+ "BriefDescription": "Scoreboard Prefetch Occupancy : All",
+ "EventCode": "0xDB",
+ "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to page miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4",
+ "EventCode": "0xDB",
+ "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR",
"PerPkg": "1",
- "UMask": "0x0c",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_PREF_OCCUPANCY.PMM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"Deprecated": "1",
"EventCode": "0xdb",
"EventName": "UNC_M_SB_PREF_OCCUPANCY.PMEM",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd2",
- "EventName": "UNC_M_SB_ACCESSES.NMRD_CMPS",
+ "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem",
+ "EventCode": "0xdb",
+ "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd2",
- "EventName": "UNC_M_SB_ACCESSES.NMWR_CMPS",
+ "BriefDescription": "Number of Scoreboard Requests Rejected",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.CANARY",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : RPQ GNTs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
+ "BriefDescription": "Number of Scoreboard Requests Rejected",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Underfill GNTs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
+ "BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Misc GNTs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
+ "BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Misc Commands (error, flow ACKs)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.MISC",
+ "BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Opportunistic Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.OPP_RD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FMRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FMTGR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FMWR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
+ "BriefDescription": ": Far Mem Read - Set",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
+ "BriefDescription": ": Near Mem Read - Clear",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : ECC Errors",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
+ "BriefDescription": ": Far Mem Write - Set",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : ERID detectable parity error",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NMRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.PMM_ERID_STARVED",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NMWR",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT",
+ "BriefDescription": ": Near Mem Read - Set",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
+ "BriefDescription": ": Near Mem Write - Set",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FMRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR",
+ "Deprecated": "1",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FMTGR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR",
"Deprecated": "1",
- "EventCode": "0xd2",
- "EventName": "UNC_M_SB_ACCESSES.FMRD_CMPS",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FMWR",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": ": Far Mem Read - Set",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": ": Near Mem Read - Clear",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": ": Far Mem Write - Set",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD",
"Deprecated": "1",
- "EventCode": "0xd2",
- "EventName": "UNC_M_SB_ACCESSES.FMWR_CMPS",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.NMRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Persistent Mem reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.NMWR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Persistent Mem writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
+ "BriefDescription": ": Near Mem Read - Set",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
+ "BriefDescription": ": Near Mem Write - Set",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.FMRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.FMTGR",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.FMWR",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "BriefDescription": ": Far Mem Read",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.FM_RD",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Inserts : DDR4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDA",
- "EventName": "UNC_M_SB_PREF_INSERTS.DDR",
+ "BriefDescription": ": Near Mem Read - Clear",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.FM_TGR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Inserts : Persistent Mem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDA",
- "EventName": "UNC_M_SB_PREF_INSERTS.PMM",
+ "BriefDescription": ": Far Mem Write",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.FM_WR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDB",
- "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.NMRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Queue Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.NMWR",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
+ "BriefDescription": ": Near Mem Read",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.NM_RD",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Queue Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
+ "BriefDescription": ": Near Mem Write",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.NM_WR",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
+ "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
"PerPkg": "1",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PMM_WPQ_FLUSH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe8",
- "EventName": "UNC_M_PMM_WPQ_FLUSH",
+ "BriefDescription": "UNC_M_SB_TAGGED.NEW",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.NEW",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PMM_WPQ_FLUSH_CYC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe9",
- "EventName": "UNC_M_PMM_WPQ_FLUSH_CYC",
+ "BriefDescription": "UNC_M_SB_TAGGED.OCC",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.OCC",
"PerPkg": "1",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xdb",
- "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM",
+ "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Free running counter that increments for the Memory Controller",
- "Counter": "4",
- "CounterType": "FREERUN",
- "EventName": "UNC_M_CLOCKTICKS_FREERUN",
+ "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
"PerPkg": "1",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": ": Valid",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED",
+ "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read Starved",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED",
+ "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.RD_HIT",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Write Starved",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED",
+ "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.RD_MISS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Read Starved",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED",
+ "BriefDescription": "2LM Tag Check : Hit in Near Memory Cache",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.HIT",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Write Starved",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
+ "BriefDescription": "2LM Tag Check : Miss, no data in this line",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD",
+ "BriefDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Read - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD",
+ "BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.NM_RD_HIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Write - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR",
+ "BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cache",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.NM_WR_HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Write - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR",
+ "BriefDescription": "Write Pending Queue Full Cycles",
+ "EventCode": "0x22",
+ "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Clear",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR",
+ "BriefDescription": "Write Pending Queue Full Cycles",
+ "EventCode": "0x16",
+ "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD",
+ "BriefDescription": "Write Pending Queue Not Empty",
+ "EventCode": "0x21",
+ "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Read - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD",
+ "BriefDescription": "Write Pending Queue Not Empty",
+ "EventCode": "0x21",
+ "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Write - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR",
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS.PCH0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Write - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR",
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS.PCH1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Clear",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR",
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x82",
+ "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.NM_RD",
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x83",
+ "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Read",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.FM_RD",
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Write",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.NM_WR",
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Write",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.FM_WR",
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x24",
+ "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Clear",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.FM_TGR",
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x24",
+ "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x2",
"Unit": "iMC"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
index 03e99b8aed93..8c09d1358849 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
@@ -1,38557 +1,33727 @@
[
{
- "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "Deprecated": "1",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Remote read requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+ "Deprecated": "1",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+ "Deprecated": "1",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Remote write requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+ "Deprecated": "1",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventName": "UNC_CHA_CLOCKTICKS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "Deprecated": "1",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "Deprecated": "1",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : All Lines Victimized",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x0F",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x0c",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for E-state entries",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for M-state entries",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for S-state entries",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0xC001FF01",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x81",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0xC001FD01",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x81",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0xC80FFD01",
- "UMaskExt": "0xC80FFD",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x81",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0xC817FD01",
- "UMaskExt": "0xC817FD",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0xCCC7FD01",
- "UMaskExt": "0xCCC7FD",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0xC807FD01",
- "UMaskExt": "0xC807FD",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0xC80FFE01",
- "UMaskExt": "0xC80FFE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0xC817FE01",
- "UMaskExt": "0xC817FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0xCCC7FE01",
- "UMaskExt": "0xCCC7FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0xC807FE01",
- "UMaskExt": "0xC807FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0xC001FF04",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x83",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0xC001FD04",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x83",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0xC001FE04",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x83",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0xC001FF01",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0xC001FD01",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0xC80FFE01",
- "UMaskExt": "0xC80FFE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0xC817FE01",
- "UMaskExt": "0xC817FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0xC807FE01",
- "UMaskExt": "0xC807FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0xC001FF04",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0xC001FD04",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0xC001FE04",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x89",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0xCC43FE04",
- "UMaskExt": "0xCC43FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_IIO_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "IIO"
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x89",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x89",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "PortMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8B",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8B",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8B",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x85",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x85",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x85",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "PortMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x87",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x87",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x87",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Lost Forward",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_I_MISC1.LOST_FWD",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Coherent Ops : WbMtoI",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x8D",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x8D",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x8D",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2e",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Hit : Clean NearMem Read Hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Hit : Dirty NearMem Read Hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the mesh to memory (M2M)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventName": "UNC_M2M_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8F",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8F",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8F",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "CHA to iMC Bypass : Not Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CHA to iMC Bypass : Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)",
+ "EventName": "UNC_CHA_CLOCKTICKS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_CHA_CMS_CLOCKTICKS",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xf2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xf1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x42",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x41",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x82",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x81",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x22",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x22",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number requests PCIe makes of the main die : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Counter 0 Occupancy",
+ "EventCode": "0x1F",
+ "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6E",
+ "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6E",
+ "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6E",
+ "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that did not have to send any snoops because the directory was clean.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that had to send one or more snoops because the directory was not clean.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.HA",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.TOR",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Distress signal asserted : DPT Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Distress signal asserted : DPT Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
- "PortMask": "0x80",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0f",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+ "BriefDescription": "Distress signal asserted : PMM Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound write (fast path) requests received by the IRP",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+ "BriefDescription": "Distress signal asserted : PMM Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : All Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : All Non Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "EventCode": "0xBA",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x97",
- "Unit": "UPI LL"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : All Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xBA",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : All Non Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
+ "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
"PerPkg": "1",
- "UMask": "0x97",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state.",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
"PerPkg": "1",
+ "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state. : Shared hit and op is RdInvOwn, RdInv, Inv*",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_I_CLOCKTICKS",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
"PerPkg": "1",
- "Unit": "IRP"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FAF RF full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_I_FAF_FULL",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_I_FAF_INSERTS",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests",
+ "EventCode": "0x5E",
+ "EventName": "UNC_CHA_HITME_LOOKUP.READ",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Occupancy of the IRP FAF queue",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_I_FAF_OCCUPANCY",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests",
+ "EventCode": "0x5E",
+ "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FAF allocation -- sent to ADQ",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_I_FAF_TRANSACTIONS",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F and op is RdInvOwn",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M2P_CLOCKTICKS",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInvOwn",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M2P_CMS_CLOCKTICKS",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HtiME$ on Reads without RspFwdI*",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M3UPI_CLOCKTICKS",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
"PerPkg": "1",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of kfclks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_UPI_CLOCKTICKS",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles in L1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_UPI_L1_POWER_CYCLES",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xC88FFD01",
- "UMaskExt": "0xC88FFD",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC897FD01",
- "UMaskExt": "0xC897FD",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xC887FD01",
- "UMaskExt": "0xC887FD",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0xC88FFE01",
- "UMaskExt": "0xC88FFE",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xC897FE01",
- "UMaskExt": "0xC897FE",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC887FE01",
- "UMaskExt": "0xC887FE",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xCC43FD04",
- "UMaskExt": "0xCC43FD",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
- "Counter": "FIXED",
- "CounterType": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_U_CLOCKTICKS",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "Unit": "UBOX"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xCC43FF04",
- "UMaskExt": "0xCC43FF",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC887FF01",
- "UMaskExt": "0xC887FF",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xC807FF01",
- "UMaskExt": "0xC807FF",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0xCCC7FF01",
- "UMaskExt": "0xCCC7FF",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xC897FF01",
- "UMaskExt": "0xC897FF",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC80FFF01",
- "UMaskExt": "0xC80FFF",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xC807FF01",
- "UMaskExt": "0xC807FF",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0xC817FF01",
- "UMaskExt": "0xC817FF",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
+ "BriefDescription": "Horizontal IV Ring in Use : Left",
+ "EventCode": "0xB9",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0xC80FFF01",
- "UMaskExt": "0xC80FFF",
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
+ "BriefDescription": "Horizontal IV Ring in Use : Right",
+ "EventCode": "0xB9",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x27",
- "Unit": "UPI LL"
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
+ "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
"PerPkg": "1",
- "UMask": "0x27",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
+ "BriefDescription": "HA to iMC Reads Issued : ISOCH",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
"PerPkg": "1",
- "UMask": "0xC816FE01",
- "UMaskExt": "0xC816FE",
+ "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
"PerPkg": "1",
- "UMask": "0xC8177E01",
- "UMaskExt": "0xC8177E",
+ "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
"PerPkg": "1",
- "UMask": "0xC816FE01",
- "UMaskExt": "0xC816FE",
+ "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
"PerPkg": "1",
- "UMask": "0xC8177E01",
- "UMaskExt": "0xC8177E",
+ "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
"PerPkg": "1",
- "UMask": "0xC896FE01",
- "UMaskExt": "0xC896FE",
+ "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
"PerPkg": "1",
- "UMask": "0xC8977E01",
- "UMaskExt": "0xC8977E",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
+ "UMask": "0x1fffff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
+ "BriefDescription": "Cache Lookups : All transactions from Remote Agents",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
"PerPkg": "1",
- "UMask": "0xC806FE01",
- "UMaskExt": "0xC806FE",
+ "PublicDescription": "Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1e20ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
+ "BriefDescription": "Cache Lookups : All Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
"PerPkg": "1",
- "UMask": "0xC8077E01",
- "UMaskExt": "0xC8077E",
+ "PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
"PerPkg": "1",
- "UMask": "0xC886FE01",
- "UMaskExt": "0xC886FE",
+ "UMask": "0x1bd0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL",
"PerPkg": "1",
- "UMask": "0xC8877E01",
- "UMaskExt": "0xC8877E",
+ "UMask": "0x19d0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
+ "BriefDescription": "Cache Lookups : Code Reads",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
"PerPkg": "1",
- "UMask": "0xC8C7FF01",
- "UMaskExt": "0xC8C7FF",
+ "PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
+ "BriefDescription": "Cache Lookups : CRd Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
"PerPkg": "1",
- "UMask": "0xCC57FF01",
- "UMaskExt": "0xCC57FF",
+ "PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
+ "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
"PerPkg": "1",
- "UMask": "0xCD43FF04",
- "UMaskExt": "0xCD43FF",
+ "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
+ "UMask": "0x19d0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
+ "BriefDescription": "Cache Lookups : Code Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
"PerPkg": "1",
- "UMask": "0xCD43FD04",
- "UMaskExt": "0xCD43FD",
+ "PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd001",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
+ "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket.",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
"PerPkg": "1",
- "UMask": "0xCD43FE04",
- "UMaskExt": "0xCD43FE",
+ "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
+ "UMask": "0x1a10ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE",
"PerPkg": "1",
- "UMask": "0xC8178A01",
- "UMaskExt": "0xC8178A",
+ "UMask": "0x1a10ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
+ "BriefDescription": "Cache Lookups : Local request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
"PerPkg": "1",
- "UMask": "0xC8168A01",
- "UMaskExt": "0xC8168A",
+ "PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
"PerPkg": "1",
- "UMask": "0xC8170A01",
- "UMaskExt": "0xC8170A",
+ "UMask": "0x1bc1ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
- "UMask": "0xc867fe01",
- "UMaskExt": "0xc867fe",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x1bc1ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
"PerPkg": "1",
- "UMask": "0xc86ffe01",
- "UMaskExt": "0xc86ffe",
+ "UMask": "0x1fc1ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
+ "BriefDescription": "Cache Lookups : Data Read Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
"PerPkg": "1",
- "UMask": "0xC8178A01",
- "UMaskExt": "0xC8178A",
+ "PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions.",
"Unit": "CHA"
},
{
- "BriefDescription": "Free running counter that increments for IIO clocktick",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x19c1ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.TO_PMM",
+ "BriefDescription": "Cache Lookups : Data Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
"PerPkg": "1",
- "UMask": "0x0720",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bc101",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE",
"PerPkg": "1",
- "UMask": "0x1C80",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x1a01ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
"PerPkg": "1",
- "UMask": "0xCCD7FE01",
- "UMaskExt": "0xCCD7FE",
+ "UMask": "0x841ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
+ "BriefDescription": "Cache Lookups : E State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.E",
"PerPkg": "1",
- "UMask": "0xC8F3FE04",
- "UMaskExt": "0xC8F3FE",
+ "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
+ "BriefDescription": "Cache Lookups : F State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.F",
"PerPkg": "1",
- "UMask": "0xc8f3fe04",
- "UMaskExt": "0xc8f3fe",
+ "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
+ "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
"PerPkg": "1",
- "UMask": "0xC8178601",
- "UMaskExt": "0xC81786",
+ "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1a44ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
+ "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL",
"PerPkg": "1",
- "UMask": "0xC8168601",
- "UMaskExt": "0xC81686",
+ "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1844ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
+ "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket.",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE",
"PerPkg": "1",
- "UMask": "0xC8170601",
- "UMaskExt": "0xC81706",
+ "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1a04ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
+ "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
"PerPkg": "1",
- "UMask": "0xC8178601",
- "UMaskExt": "0xC81786",
+ "PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
+ "BriefDescription": "Cache Lookups : I State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.I",
"PerPkg": "1",
- "UMask": "0xC8F3FD04",
- "UMaskExt": "0xC8F3FD",
+ "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
"PerPkg": "1",
- "UMask": "0xC8F3FF04",
- "UMaskExt": "0xC8F3FF",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x189dff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
+ "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F",
"PerPkg": "1",
- "UMask": "0xCCD7FF01",
- "UMaskExt": "0xCCD7FF",
+ "PublicDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL",
"PerPkg": "1",
- "UMask": "0xC8F3FF04",
- "UMaskExt": "0xC8F3FF",
+ "UMask": "0x189dff",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM",
+ "Deprecated": "1",
"EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
"PerPkg": "1",
- "UMask": "0x1BC1FF",
- "UMaskExt": "0x1BC1",
+ "UMask": "0xbdfff",
"Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Transactions homed locally",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
+ "UMask": "0xbdfff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : M State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.M",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : All Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1fe001",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Write Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remote non-snoop request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remote non-snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Non-snoop transactions to the LLC from remote agent",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Reads",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd9ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x9d9ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x11d9ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd901",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0xbd901",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x13d901",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x161901",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0xa19ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd90e",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
- "FCMask": "0x04",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x15dfff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+ "BriefDescription": "Cache Lookups : Transactions homed remotely Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F",
"PerPkg": "1",
- "UMask": "0x78",
- "Unit": "IRP"
+ "PublicDescription": "Cache Lookups : Transactions homed remotely Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remote snoop request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F",
"PerPkg": "1",
- "PortMask": "0xff",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remote snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Snoop transactions to the LLC from remote agent",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
- "FCMask": "0x04",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
"PerPkg": "1",
- "UMask": "0xff",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
+ "UMask": "0x1c19ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
+ "BriefDescription": "Cache Lookups : Transactions homed remotely",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM",
"PerPkg": "1",
- "UMask": "0xCC42FF04",
- "UMaskExt": "0xCC42FF",
+ "PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
+ "UMask": "0x15dfff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
+ "BriefDescription": "Cache Lookups : RFO Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
"PerPkg": "1",
- "UMask": "0xCC437F04",
- "UMaskExt": "0xCC437F",
+ "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
+ "UMask": "0x1bc8ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
+ "BriefDescription": "Cache Lookups : RFO Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
"PerPkg": "1",
- "UMask": "0xCD42FF04",
- "UMaskExt": "0xCD42FF",
+ "PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
+ "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
"PerPkg": "1",
- "UMask": "0xCD437F04",
- "UMaskExt": "0xCD437F",
+ "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
+ "UMask": "0x19c8ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+ "BriefDescription": "Cache Lookups : RFO Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bc801",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x888ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.HA",
+ "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket.",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
+ "UMask": "0x1a08ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline directory state updates : Directory Updated memory write from TOR pipe",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.TOR",
+ "BriefDescription": "Cache Lookups : S State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.S",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
+ "BriefDescription": "Cache Lookups : SnoopFilter - E State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - All Lines",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+ "BriefDescription": "Cache Lookups : SnoopFilter - H State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
"PerPkg": "1",
- "UMask": "0x200F",
- "UMaskExt": "0x20",
+ "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote - All Lines",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+ "BriefDescription": "Cache Lookups : SnoopFilter - S State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
"PerPkg": "1",
- "UMask": "0x800F",
- "UMaskExt": "0x80",
+ "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR",
+ "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.",
+ "UMask": "0x1a42ff",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
"Deprecated": "1",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x842ff",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
"Deprecated": "1",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x17c2ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+ "BriefDescription": "Lines Victimized : All Lines Victimized",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
"PerPkg": "1",
+ "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0xf",
"Unit": "CHA"
},
{
- "BriefDescription": "Number of times that an RFO hit in S state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RFO_HIT_S",
+ "BriefDescription": "Lines Victimized : Lines in E state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE",
+ "BriefDescription": "Lines Victimized : Local - All Lines",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
"PerPkg": "1",
- "UMask": "0x30",
+ "PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x200f",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Lines Victimized : Local - Lines in E State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2002",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
+ "BriefDescription": "Lines Victimized : Local - Lines in M State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2001",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspIFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
+ "BriefDescription": "Lines Victimized : Local Only",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
+ "BriefDescription": "Lines Victimized : Local - Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2004",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspSFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
+ "BriefDescription": "Lines Victimized : Lines in M state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL",
+ "BriefDescription": "Lines Victimized : Remote - All Lines",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
"PerPkg": "1",
- "UMask": "0xC001FFff",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "Lines Victimized : Remote - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x800f",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD",
+ "BriefDescription": "Lines Victimized : Remote - Lines in E State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
"PerPkg": "1",
- "UMask": "0xcccffd01",
- "UMaskExt": "0xcccffd",
+ "PublicDescription": "Lines Victimized : Remote - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8002",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD",
+ "BriefDescription": "Lines Victimized : Remote - Lines in M State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
"PerPkg": "1",
- "UMask": "0xccd7fd01",
- "UMaskExt": "0xccd7fd",
+ "PublicDescription": "Lines Victimized : Remote - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8001",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "BriefDescription": "Lines Victimized : Remote Only",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY",
"PerPkg": "1",
- "UMask": "0xC80FFD01",
- "UMaskExt": "0xC80FFD",
+ "PublicDescription": "Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+ "BriefDescription": "Lines Victimized : Remote - Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
"PerPkg": "1",
- "UMask": "0xC817FD01",
- "UMaskExt": "0xC817FD",
+ "PublicDescription": "Lines Victimized : Remote - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8004",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
+ "BriefDescription": "Lines Victimized : Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
- "UMask": "0xCCC7FD01",
- "UMaskExt": "0xCCC7FD",
+ "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+ "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
"PerPkg": "1",
- "UMask": "0xC807FD01",
- "UMaskExt": "0xC807FD",
+ "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
+ "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
"PerPkg": "1",
- "UMask": "0xCCC7FE01",
- "UMaskExt": "0xCCC7FE",
+ "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+ "BriefDescription": "Number of times that an RFO hit in S state.",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RFO_HIT_S",
"PerPkg": "1",
- "UMask": "0xc803fe04",
- "UMaskExt": "0xc803fe",
+ "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+ "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "UMask": "0xc803fe04",
- "UMaskExt": "0xc803fe",
+ "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+ "BriefDescription": "Cbo Misc : Write Combining Aliasing",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.WC_ALIASING",
"PerPkg": "1",
- "UMask": "0xcc43fe04",
- "UMaskExt": "0xcc43fe",
+ "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "EventCode": "0xE6",
+ "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "EventCode": "0xE6",
+ "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Local Rd",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.LOCAL_READ",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Off",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Remote Rd",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.REMOTE_READ",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : Hit M",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.RFO",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles when Direct2UPI was Disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.NI",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
"PerPkg": "1",
- "UMaskExt": "0x1E",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M2M_TAG_MISS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass : Not Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to core transaction was overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ALL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI",
"PerPkg": "1",
- "UMask": "0x0704",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.NORMAL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH",
"PerPkg": "1",
- "UMask": "0x0701",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.ALL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM",
"PerPkg": "1",
- "UMask": "0x1C10",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
"PerPkg": "1",
- "UMask": "0x1C01",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
"PerPkg": "1",
- "UMask": "0x1C02",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M2M_RxC_AD_INSERTS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M2M_RxC_BL_INSERTS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x06",
- "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x09",
- "EventName": "UNC_M2M_TxC_AD_INSERTS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0A",
- "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass : Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass : Not Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE",
+ "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the LLC.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+ "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the SF.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+ "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due to a pending read to the same near memory set in the TOR.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
"PerPkg": "1",
- "UMask": "0x81",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
"PerPkg": "1",
- "UMask": "0xF1",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
"PerPkg": "1",
- "UMask": "0x22",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
"PerPkg": "1",
- "UMask": "0x22",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ",
"PerPkg": "1",
- "UMask": "0x42",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
"PerPkg": "1",
- "UMask": "0x82",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT",
"PerPkg": "1",
- "UMask": "0xF2",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
+ "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.THROTTLE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
+ "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
+ "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
+ "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+ "EventCode": "0x67",
+ "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": ": count # of FAST TOR Request inserted to ha_tor_req_fifo",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
+ "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
+ "EventCode": "0x67",
+ "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": ": count # of SLOW TOR Request inserted to ha_pmm_tor_req_fifo",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
"PerPkg": "1",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_CHA_HITME_LOOKUP.READ",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+ "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x30",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+ "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
+ "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
+ "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .",
+ "UMask": "0x3",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HtiME$ on Reads without RspFwdI*",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
+ "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "HA to iMC Reads Issued : ISOCH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+ "BriefDescription": "Remote read requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+ "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0xc",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+ "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+ "BriefDescription": "Remote write requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Lines in M state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Lines in E state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Lines in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local Only",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote Only",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMaskExt": "0x80",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - Lines in M State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x2001",
- "UMaskExt": "0x20",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - Lines in E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x2002",
- "UMaskExt": "0x20",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - Lines in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x2004",
- "UMaskExt": "0x20",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote - Lines in M State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x8001",
- "UMaskExt": "0x80",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote - Lines in E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x8002",
- "UMaskExt": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote - Lines in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x8004",
- "UMaskExt": "0x80",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : Write Combining Aliasing",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.WC_ALIASING",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+ "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Local Rd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.LOCAL_READ",
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Remote Rd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.REMOTE_READ",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_CHA_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Off",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
+ "BriefDescription": "Ingress (from CMS) Allocations : IPQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
+ "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
+ "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
+ "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
+ "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
+ "BriefDescription": "Ingress (from CMS) Allocations : RRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
+ "BriefDescription": "Ingress (from CMS) Allocations : WBQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x10",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x40",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x80",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x100",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMaskExt": "0x200",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMaskExt": "0x800",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
"PerPkg": "1",
- "UMaskExt": "0x1000",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMaskExt": "0x2000",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMaskExt": "0x4000",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMaskExt": "0x8000",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMaskExt": "0x10000",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMaskExt": "0x20000",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMaskExt": "0x40000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x80000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x100000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x200000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMaskExt": "0x400000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x800000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x1000000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x2000000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMaskExt": "0x4000000",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMaskExt": "0x8000000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
"PerPkg": "1",
- "UMaskExt": "0x10000000",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
+ "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
+ "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
+ "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x08",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
+ "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x10",
+ "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
+ "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+ "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : IPQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : RRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : WBQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
"PerPkg": "1",
+ "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "ISMQ Rejects - Set 1 : HA",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "ISMQ Retries - Set 1 : HA",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "Ingress (from CMS) Occupancy : IPQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Ingress (from CMS) Occupancy : RRQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Ingress (from CMS) Occupancy : WBQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
+ "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+ "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "Other Retries - Set 1 : ANY0",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "Other Retries - Set 1 : HA",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "Other Retries - Set 1 : LLC Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Other Retries - Set 1 : SF Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+ "BriefDescription": "Other Retries - Set 1 : Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+ "PerPkg": "1",
+ "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+ "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+ "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+ "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+ "BriefDescription": "Request Queue Retries - Set 1 : HA",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy : IPQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
+ "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy : RRQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
+ "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy : WBQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
+ "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "Request Queue Retries - Set 1 : Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+ "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+ "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+ "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+ "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "BriefDescription": "RRQ Rejects - Set 1 : ANY0",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+ "BriefDescription": "RRQ Rejects - Set 1 : HA",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+ "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+ "BriefDescription": "RRQ Rejects - Set 1 : SF Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "RRQ Rejects - Set 1 : Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+ "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+ "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "WBQ Rejects - Set 1 : ANY0",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "WBQ Rejects - Set 1 : HA",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
+ "PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
"PerPkg": "1",
+ "PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "WBQ Rejects - Set 1 : SF Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "WBQ Rejects - Set 1 : Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "BriefDescription": "Transgress Ingress Bypass : AK",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AK",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
+ "BriefDescription": "Transgress Injection Starvation : IV",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "Transgress Ingress Allocations : AK",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
- "PerPkg": "1",
- "UMask": "0x04",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
+ "PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Transgress Ingress Occupancy : AK",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
- "PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : Broadcast snoops for Remote Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to remote requests",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : Directed snoops for Local Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : Directed snoops for Remote Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to remote requests",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : Rsp*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPWB",
+ "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB",
+ "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Snoops Sent : Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to remote requests",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Snoop Responses Received : RSPCNFLCT*",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "Snoop Responses Received : RspFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+ "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+ "BriefDescription": "Snoop Responses Received : RspI",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspIFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+ "BriefDescription": "Snoop Responses Received : RspIFwd",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspSFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "BriefDescription": "Snoop Responses Received : RspS",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
+ "BriefDescription": "Snoop Responses Received : RspSFwd",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
+ "BriefDescription": "Snoop Responses Received : Rsp*WB",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPWB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Snoop Responses Received Local : RspCnflct",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "Snoop Responses Received Local : RspFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
+ "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
+ "BriefDescription": "Snoop Responses Received Local : RspI",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
+ "BriefDescription": "Snoop Responses Received Local : RspIFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
+ "BriefDescription": "Snoop Responses Received Local : RspS",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
+ "BriefDescription": "Snoop Responses Received Local : RspSFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
"EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI : Pushed to LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+ "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI : Pushed to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+ "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
+ "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
+ "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
+ "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMaskExt": "0x08",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMaskExt": "0x10",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Sent (on 0?)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.SENT0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Sent (on 1?)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.SENT1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "PortMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x10",
- "Unit": "IIO"
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD1",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD1",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD1",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD3",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD3",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD3",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD5",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD5",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD5",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD7",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD7",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD7",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ffff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DDR4 Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.DDR",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : SF/LLC Evictions",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Just Hits",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.HIT",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8d7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; CRd Pref from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0xcccffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0xccd7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB lookups first",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB lookups all",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Hits to a 4K Page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.4K_HITS",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Hits to a 2M Page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.2M_HITS",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Hits to a 1G Page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.1G_HITS",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.MISSES",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Context cache lookups",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Context cache hits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": PageWalk cache lookup",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOMMU memory access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Cycles PWT full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Interrupt Entry cache lookup",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Interrupt Entry cache hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccfff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817fe01",
+ "Unit": "CHA"
},
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
- "FCMask": "0x07",
+ {
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8178601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc816fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8178a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc896fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter",
+ "UMask": "0xc8977e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8177e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc867fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8678a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Total Write Cache Occupancy : Any Source",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0F",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Total Write Cache Occupancy : Snoops",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0F",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Coherent Ops : CLFlush",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.EVICTS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1e",
- "EventName": "UNC_I_MISC0.FAST_REQ",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.FAST_REJ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1e",
- "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1e",
- "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.FAST_XFER",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f0a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_I",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_S",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_E",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_M",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc806fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Received Invalid",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Received Valid",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc886fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : P2P reads",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8877e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : P2P Writes",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8077e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : P2P Message",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+ "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : P2P completions",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+ "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc877de01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : Match if remote only",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : match if remote and target matches",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+ "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : match if local only",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : match if local and target matches",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : Miss",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.MISS",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : Hit I",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : Hit E or S",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc87fde01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : SnpCode",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : SnpData",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : SnpInv",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+ "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound Transaction Count : Writes",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc3fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound Transaction Count : Atomic",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+ "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc37ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound Transaction Count : Other",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc2fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound Transaction Count : Select Source",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+ "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc27ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass : Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
+ "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc67ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass : Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass : Not Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+ "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On Dirty Line in I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+ "BriefDescription": "TOR Inserts : All requests from IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On Dirty Line in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+ "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On Dirty Line in L State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+ "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On Dirty Line in A State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On NonDirty Line in I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On NonDirty Line in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+ "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On NonDirty Line in L State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+ "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On NonDirty Line in A State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On Dirty Line in I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On Dirty Line in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd42ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On Dirty Line in L State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd437f04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On Dirty Line in A State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc42ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On NonDirty Line in I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc437f04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On NonDirty Line in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+ "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On NonDirty Line in L State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On NonDirty Line in A State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
+ "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x0101",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
+ "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x0102",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
+ "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x0104",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+ "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
"PerPkg": "1",
- "UMask": "0x0140",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
+ "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
"PerPkg": "1",
- "UMask": "0x0201",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc23ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
+ "BriefDescription": "TOR Inserts : IPQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x0202",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
+ "BriefDescription": "TOR Inserts : IRQ - iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
"PerPkg": "1",
- "UMask": "0x0204",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
+ "BriefDescription": "TOR Inserts : IRQ - Non iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
"PerPkg": "1",
- "UMask": "0x0240",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR",
+ "BriefDescription": "TOR Inserts : Just ISOC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
"PerPkg": "1",
- "UMask": "0x0440",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
+ "BriefDescription": "TOR Inserts : Just Local Targets",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
"PerPkg": "1",
- "UMask": "0x0401",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
+ "BriefDescription": "TOR Inserts : All from Local iA and IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x0402",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+ "UMask": "0xc000ff05",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
+ "BriefDescription": "TOR Inserts : All from Local iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
"PerPkg": "1",
- "UMask": "0x0404",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+ "UMask": "0xc000ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
+ "BriefDescription": "TOR Inserts : All from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
"PerPkg": "1",
- "UMask": "0x0408",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+ "UMask": "0xc000ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
+ "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
"PerPkg": "1",
- "UMask": "0x0410",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
+ "BriefDescription": "TOR Inserts : Just Misses",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MISS",
"PerPkg": "1",
- "UMaskExt": "0x05",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_NI",
+ "BriefDescription": "TOR Inserts : MMCFG Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
"PerPkg": "1",
- "UMaskExt": "0x06",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
+ "BriefDescription": "TOR Inserts : Just NearMem",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
"PerPkg": "1",
- "UMask": "0x0801",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
+ "BriefDescription": "TOR Inserts : Just NonCoherent",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
"PerPkg": "1",
- "UMask": "0x0802",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
+ "BriefDescription": "TOR Inserts : Just NotNearMem",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
"PerPkg": "1",
- "UMask": "0x0804",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
+ "BriefDescription": "TOR Inserts : PMM Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PMM",
"PerPkg": "1",
- "UMask": "0x0808",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PMM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
+ "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
"PerPkg": "1",
- "UMask": "0x0810",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
+ "BriefDescription": "TOR Inserts : PRQ - IOSF",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
"PerPkg": "1",
- "UMaskExt": "0x09",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_NI",
+ "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
"PerPkg": "1",
- "UMaskExt": "0x0A",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Packet Header Matches : Mesh Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MESH",
+ "BriefDescription": "TOR Inserts : Just Remote Targets",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Packet Header Matches : MC Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MC",
+ "BriefDescription": "TOR Inserts : RRQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
+ "BriefDescription": "TOR Inserts : WBQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
+ "BriefDescription": "TOR Occupancy : DDR4 Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2",
+ "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
+ "BriefDescription": "TOR Occupancy : Just Hits",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
+ "BriefDescription": "TOR Occupancy : All requests from iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2",
+ "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Full : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_FULL.CH0",
+ "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8d7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Full : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_FULL.CH1",
+ "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Full : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_FULL.CH2",
+ "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+ "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_NE.CH0",
+ "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_NE.CH1",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_NE.CH2",
+ "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.NDR",
+ "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+ "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897fd01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+ "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+ "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+ "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
"PerPkg": "1",
- "UMask": "0x88",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x90",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+ "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0xA0",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccfff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+ "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+ "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+ "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+ "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+ "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+ "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+ "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8178601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc816fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8178a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+ "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc896fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+ "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc8977e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8177e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc867fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Full : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8678a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "WPQ Flush : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "WPQ Flush : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "WPQ Flush : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_WPQ_FLUSH.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f0a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Mirror",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Inserts : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc806fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.CH2",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc886fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8877e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x63",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8077e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x63",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
+ "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC: For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x63",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2",
+ "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc877de01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x62",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x62",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x62",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy : Mirror",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
+ "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc87fde01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Inserts : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2",
+ "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
+ "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc27ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
+ "BriefDescription": "TOR Occupancy : All requests from IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
+ "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
+ "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
+ "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
+ "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
+ "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
+ "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
+ "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
+ "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
+ "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc23ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
+ "BriefDescription": "TOR Occupancy : IPQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
+ "BriefDescription": "TOR Occupancy : IRQ - iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
+ "BriefDescription": "TOR Occupancy : IRQ - Non iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.ALL",
+ "BriefDescription": "TOR Occupancy : Just ISOC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+ "BriefDescription": "TOR Occupancy : Just Local Targets",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+ "BriefDescription": "TOR Occupancy : All from Local iA and IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+ "UMask": "0xc000ff05",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+ "BriefDescription": "TOR Occupancy : All from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+ "UMask": "0xc000ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+ "BriefDescription": "TOR Occupancy : All from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+ "UMask": "0xc000ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+ "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+ "BriefDescription": "TOR Occupancy : Just Misses",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+ "BriefDescription": "TOR Occupancy : MMCFG Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
+ "BriefDescription": "TOR Occupancy : Just NearMem",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
+ "BriefDescription": "TOR Occupancy : Just NonCoherent",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
+ "BriefDescription": "TOR Occupancy : Just NotNearMem",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
+ "BriefDescription": "TOR Occupancy : PMM Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
+ "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
+ "BriefDescription": "TOR Occupancy : PRQ - IOSF",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
+ "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
+ "BriefDescription": "TOR Occupancy : Just Remote Targets",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CBox AD Credits Empty : VNA Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CBox AD Credits Empty : Writebacks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CBox AD Credits Empty : Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CBox AD Credits Empty : Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+ "BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AD - Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AD - Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AD - Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : BL - Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AK - Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AK - Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : Max Parallel Win",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
- {
- "BriefDescription": "Can't Arb for VN0 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ",
+ {
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : VNA In Use",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : Packets in BGF FIFO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : Packets in BGF Path",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : Transmit Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : D2K Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : Credits Consumed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : TSV High",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : No BGF Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : No TxQ Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Accumulate",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Parallel Ok",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Parallel Message",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : One Message",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : Two Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : Three Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : One Message in non-VNA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : One Slot Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : Two Slots Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : All Slots Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : TSV High",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : Cycle valid for Flit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : No BGF Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : No TxQ Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD",
+ "BriefDescription": "Vertical IV Ring in Use : Down",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : VN0",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.VN0",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : VN1",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.VN1",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : Parallel Attempt",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : Parallel Success",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
+ "BriefDescription": "WbPushMtoI : Pushed to LLC",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : Can't Slot AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
+ "BriefDescription": "WbPushMtoI : Pushed to Memory",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : Can't Slot BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
+ "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
+ "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
+ "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
+ "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
+ "BriefDescription": "XPT Prefetches : Sent (on 0?)",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.SENT0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
+ "BriefDescription": "XPT Prefetches : Sent (on 1?)",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.SENT1",
"PerPkg": "1",
+ "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : REQ on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : SNP on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : RSP on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : RSP on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : WB on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : NCB on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : NCS on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : REQ on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
+ "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
+ "EventCode": "0x01",
+ "EventName": "UNC_IIO_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz)",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : SNP on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
+ "BriefDescription": "Free running counter that increments for IIO clocktick",
+ "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : RSP on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
+ "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0xFF",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : RSP on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0xff",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : WB on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : NCB on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : NCS on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Corrected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Level < 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Level < 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Level < 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
+ "FCMask": "0x04",
+ "PerPkg": "1",
+ "PortMask": "0x40",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
+ "UMask": "0x3",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Level < 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+ "UMask": "0xff",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Any In Use",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+ "UMask": "0xff",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
+ "FCMask": "0x04",
"PerPkg": "1",
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
+ "FCMask": "0x04",
"PerPkg": "1",
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
+ "FCMask": "0x04",
"PerPkg": "1",
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
+ "FCMask": "0x04",
"PerPkg": "1",
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
"UMask": "0x80",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN0 NCB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN0 NCS Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN1 NCS Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN1 NCB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VNA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VNA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x81",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x82",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x84",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x90",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xA0",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC0",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.ARB",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : VLW",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : MSI",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : IPI",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UBOX"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : Doorbell",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UBOX"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : Interrupt",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UBOX"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDRAND",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDSEED",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UBOX"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Direct packet attempts : D2C",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Direct packet attempts : D2K",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "BriefDescription": "Incoming arbitration requests : Passing data to be written",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "BriefDescription": "Incoming arbitration requests : Request Ownership",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "BriefDescription": "Incoming arbitration requests : Writing line",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "BriefDescription": "Incoming arbitration requests granted : Writing line",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "BriefDescription": ": IOTLB Hits to a 1G Page",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.1G_HITS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "BriefDescription": ": IOTLB Hits to a 2M Page",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.2M_HITS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "BriefDescription": ": IOTLB Hits to a 4K Page",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.4K_HITS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "BriefDescription": ": IOTLB lookups all",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "BriefDescription": ": Context cache hits",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "BriefDescription": ": Context cache lookups",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "BriefDescription": ": IOTLB lookups first",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.MISSES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "BriefDescription": ": Cycles PWT full",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "BriefDescription": ": IOMMU memory access",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "BriefDescription": ": PWC Hit to a 1G page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+ "BriefDescription": ": PWC Hit to a 2M page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
+ "BriefDescription": ": PWC Hit to a 4K page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
"PerPkg": "1",
- "UMask": "0x108",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+ "BriefDescription": ": PWT Hit to a 256T page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
"PerPkg": "1",
- "UMask": "0x09",
- "Unit": "UPI LL"
+ "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
+ "BriefDescription": ": PageWalk cache fill",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
"PerPkg": "1",
- "UMask": "0x109",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": ": PageWalk cache lookup",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x0A",
- "Unit": "UPI LL"
+ "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "BriefDescription": ": Interrupt Entry cache hit",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
"PerPkg": "1",
- "UMask": "0x10A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+ "BriefDescription": ": Interrupt Entry cache lookup",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x0C",
- "Unit": "UPI LL"
+ "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "BriefDescription": ": Device-selective Context cache invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
"PerPkg": "1",
- "UMask": "0x10C",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+ "BriefDescription": ": Domain-selective Context cache invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
"PerPkg": "1",
- "UMask": "0x0D",
- "Unit": "UPI LL"
+ "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
+ "BriefDescription": ": Context cache global invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
"PerPkg": "1",
- "UMask": "0x10D",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
"PerPkg": "1",
- "UMask": "0x0E",
- "Unit": "UPI LL"
+ "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": ": Global IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
"PerPkg": "1",
- "UMask": "0x10E",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": ": Page-selective IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
"PerPkg": "1",
- "UMask": "0x10F",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
- {
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
+ {
+ "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x1AA",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
+ "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x12A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+ "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+ "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+ "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.DATA",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
"PerPkg": "1",
+ "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.NULL",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
+ "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match",
"UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : LLCTRL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+ "BriefDescription": "Counting disabled",
+ "EventCode": "0x80",
+ "EventName": "UNC_IIO_NOTHING",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Protocol Header",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+ "BriefDescription": "Occupancy of outbound request queue : To device",
+ "EventCode": "0xC5",
+ "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.IDLE",
+ "BriefDescription": ": Passing data to be written",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x47",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": ": Passing data to be written : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+ "BriefDescription": ": Issuing final read or write of line",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+ "BriefDescription": ": Processing response from IOMMU",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+ "BriefDescription": ": Issuing to IOMMU",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+ "BriefDescription": ": Request Ownership",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": ": Request Ownership : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+ "BriefDescription": ": Writing line",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": ": Writing line : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+ "BriefDescription": "Number requests sent to PCIe from main die : From IRP",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "BriefDescription": "Number requests sent to PCIe from main die : From ITC",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
+ "EventCode": "0x85",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "BriefDescription": "Number requests PCIe makes of the main die : All",
+ "EventCode": "0x85",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "BriefDescription": "Num requests sent by PCIe - by target : Abort",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0xFF",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0xFF",
"UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0xFF",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Num requests sent by PCIe - by target : Memory",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "BriefDescription": "ITC address map 1",
+ "EventCode": "0x8F",
+ "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
+ "EventCode": "0xD0",
+ "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
+ "EventCode": "0xD1",
+ "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "BriefDescription": "PWT occupancy",
+ "EventCode": "0x42",
+ "EventName": "UNC_IIO_PWT_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
+ "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
+ "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x108",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
+ "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x09",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
+ "BriefDescription": "PCIe Request - cacheline complete : Writing line",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x109",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": "PCIe Request complete : Passing data to be written",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0A",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
+ "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0C",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10C",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
+ "BriefDescription": "PCIe Request complete : Request Ownership",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0D",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
+ "BriefDescription": "PCIe Request complete : Writing line",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10D",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0E",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10E",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": "PCIe Request - pass complete : Request Ownership",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "PCIe Request - pass complete : Writing line",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10F",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
+ "BriefDescription": "Symbol Times on Link",
+ "EventCode": "0x82",
+ "EventName": "UNC_IIO_SYMBOL_TIMES",
"PerPkg": "1",
- "UMask": "0x1AA",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x12A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.DATA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.NULL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : LLCTRL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
"UMask": "0x40",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Protocol Header",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Idle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.IDLE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x47",
- "Unit": "UPI LL"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.I",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : SnoopFilter - S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : SnoopFilter - E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : SnoopFilter - H State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.S",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.E",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : M State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.M",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : F State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.F",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : RFO Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1BC8FF",
- "UMaskExt": "0x1BC8",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : IRQ - iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : SF/LLC Evictions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : PRQ - IOSF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : IPQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : IRQ - Non iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : RRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : WBQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
"UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : All from Local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF04",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : All from Local iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF01",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : All from Local iA and IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF05",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just Hits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : MMCFG Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just Local Targets",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just Remote Targets",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x100",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x200",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x400",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just NearMem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x400000",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just NotNearMem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x800000",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just NonCoherent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x1000000",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just ISOC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x2000000",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : IRQ - iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : PRQ - IOSF",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : IPQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : IRQ - Non iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF04",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Local iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF01",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Local iA and IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF05",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Hits",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Misses",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : MMCFG Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Local Targets",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Remote Targets",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x100",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x200",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x400",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just NearMem",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x400000",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just NotNearMem",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x800000",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just NonCoherent",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x1000000",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just ISOC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x2000000",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x01",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x01",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x02",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x10",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x10",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x20",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x20",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x80",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x80",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x02",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x08",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x01",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x01",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x10",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x10",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x20",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x20",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x80",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x80",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x02",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x08",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x10",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x10",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
"UMask": "0x40",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x80",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x80",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
- "PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
- "PerPkg": "1",
- "UMaskExt": "0x0C",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Full : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH",
+ "BriefDescription": "Total Write Cache Occupancy : Any Source",
+ "EventCode": "0x0F",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.",
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
+ "BriefDescription": "Total Write Cache Occupancy : Snoops",
+ "EventCode": "0x0F",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
+ "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
+ "EventCode": "0x0f",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.",
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
+ "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
+ "EventCode": "0x01",
+ "EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
+ "BriefDescription": "Coherent Ops : CLFlush",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
+ "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
+ "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
+ "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
+ "BriefDescription": "Coherent Ops : WbMtoI",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
+ "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP",
"UMask": "0x40",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
+ "BriefDescription": "FAF RF full",
+ "EventCode": "0x17",
+ "EventName": "UNC_I_FAF_FULL",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
+ "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+ "EventCode": "0x18",
+ "EventName": "UNC_I_FAF_INSERTS",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH",
+ "BriefDescription": "Occupancy of the IRP FAF queue.",
+ "EventCode": "0x19",
+ "EventName": "UNC_I_FAF_OCCUPANCY",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP",
+ "BriefDescription": "FAF allocation -- sent to ADQ",
+ "EventCode": "0x16",
+ "EventName": "UNC_I_FAF_TRANSACTIONS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION",
+ "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.EVICTS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT",
+ "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B",
+ "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC",
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD",
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
+ "EventCode": "0x1e",
+ "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL",
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
+ "EventCode": "0x1e",
+ "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY",
+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY",
+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+ "EventCode": "0x1e",
+ "EventName": "UNC_I_MISC0.FAST_REQ",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH",
+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH",
+ "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
+ "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI",
+ "BriefDescription": "Misc Events - Set 1 : Lost Forward",
+ "EventCode": "0x1F",
+ "EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
+ "BriefDescription": "Misc Events - Set 1 : Received Invalid",
+ "EventCode": "0x1F",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI",
+ "BriefDescription": "Misc Events - Set 1 : Received Valid",
+ "EventCode": "0x1F",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2",
+ "BriefDescription": "P2P Requests",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_P2P_INSERTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "P2P Requests : P2P requests from the ITC",
+ "Unit": "IRP"
},
{
- "BriefDescription": ": Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
+ "BriefDescription": "P2P Occupancy",
+ "EventCode": "0x15",
+ "EventName": "UNC_I_P2P_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy",
+ "Unit": "IRP"
},
{
- "BriefDescription": ": Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
+ "BriefDescription": "P2P Transactions : P2P completions",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": ": Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2",
+ "BriefDescription": "P2P Transactions : match if local only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "BriefDescription": "P2P Transactions : match if local and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "BriefDescription": "P2P Transactions : P2P Message",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "BriefDescription": "P2P Transactions : P2P reads",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
+ "BriefDescription": "P2P Transactions : Match if remote only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
+ "BriefDescription": "P2P Transactions : match if remote and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
"PerPkg": "1",
"UMask": "0x20",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Write Tracker Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Write Tracker Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
+ "BriefDescription": "P2P Transactions : P2P Writes",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
+ "UMask": "0x7e",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
+ "UMask": "0x74",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
+ "UMask": "0x72",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
+ "UMask": "0x78",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
+ "UMask": "0x71",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "BriefDescription": "Snoop Responses : Hit E or S",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "BriefDescription": "Snoop Responses : Hit I",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "BriefDescription": "Snoop Responses : Hit M",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
+ "BriefDescription": "Snoop Responses : Miss",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "BriefDescription": "Snoop Responses : SnpCode",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "BriefDescription": "Snoop Responses : SnpData",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "BriefDescription": "Snoop Responses : SnpInv",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
+ "BriefDescription": "Inbound Transaction Count : Atomic",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions",
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
+ "BriefDescription": "Inbound Transaction Count : Other",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.",
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
+ "BriefDescription": "Inbound Transaction Count : Writes",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
+ "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
+ "BriefDescription": "AK Egress Allocations",
+ "EventCode": "0x0B",
+ "EventName": "UNC_I_TxC_AK_INSERTS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
+ "BriefDescription": "BL DRS Egress Cycles Full",
+ "EventCode": "0x05",
+ "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
+ "BriefDescription": "BL DRS Egress Inserts",
+ "EventCode": "0x02",
+ "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
+ "BriefDescription": "BL DRS Egress Occupancy",
+ "EventCode": "0x08",
+ "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
+ "BriefDescription": "BL NCB Egress Cycles Full",
+ "EventCode": "0x06",
+ "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
+ "BriefDescription": "BL NCB Egress Inserts",
+ "EventCode": "0x03",
+ "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
+ "BriefDescription": "BL NCB Egress Occupancy",
+ "EventCode": "0x09",
+ "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
+ "BriefDescription": "BL NCS Egress Cycles Full",
+ "EventCode": "0x07",
+ "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
+ "BriefDescription": "BL NCS Egress Inserts",
+ "EventCode": "0x04",
+ "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
+ "BriefDescription": "BL NCS Egress Occupancy",
+ "EventCode": "0x0A",
+ "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
+ "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "BriefDescription": "No AD0 Egress Credits Stalls",
+ "EventCode": "0x1A",
+ "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "BriefDescription": "No AD1 Egress Credits Stalls",
+ "EventCode": "0x1B",
+ "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "BriefDescription": "No BL Egress Credit Stalls",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0x0D",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0x0E",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
+ "BriefDescription": "Outbound Request Queue Occupancy",
+ "EventCode": "0x0C",
+ "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "Outbound Request Queue Occupancy : Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : Local NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : Local NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : Remote NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : Remote NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : All",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : Local NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : Local NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : Remote NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : Remote NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : Local NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : Local NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : Remote NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : Remote NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8B",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8B",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8B",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x8D",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x8D",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x8D",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4d",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4d",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4d",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x2d",
- "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+ "BriefDescription": "M2M to iMC Bypass : Not Taken",
+ "EventCode": "0x22",
+ "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+ "BriefDescription": "M2M to iMC Bypass : Taken",
+ "EventCode": "0x22",
+ "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+ "BriefDescription": "M2M to iMC Bypass : Not Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UBOX"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+ "BriefDescription": "M2M to iMC Bypass : Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UBOX"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+ "BriefDescription": "Clockticks of the mesh to memory (M2M)",
+ "EventName": "UNC_M2M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M2M_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+ "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+ "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "EventCode": "0x60",
+ "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+ "BriefDescription": "Number of reads in which direct to core transaction was overridden",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+ "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+ "EventCode": "0x28",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+ "BriefDescription": "Cycles when Direct2UPI was Disabled",
+ "EventCode": "0x27",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+ "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+ "EventCode": "0x29",
+ "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UBOX"
+ "PublicDescription": "Clockticks of the mesh to PCI (M2P)",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "BriefDescription": "Directory Hit : On NonDirty Line in A State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UBOX"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+ "BriefDescription": "Directory Hit : On NonDirty Line in I State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UBOX"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+ "BriefDescription": "Directory Hit : On NonDirty Line in L State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
"PerPkg": "1",
"UMask": "0x40",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+ "BriefDescription": "Directory Hit : On NonDirty Line in S State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UBOX"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+ "BriefDescription": "Directory Hit : On Dirty Line in A State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+ "BriefDescription": "Directory Hit : On Dirty Line in I State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Directory Hit : On Dirty Line in L State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Directory Hit : On Dirty Line in S State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Directory Miss : On NonDirty Line in A State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Directory Miss : On NonDirty Line in I State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Directory Miss : On NonDirty Line in L State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Directory Miss : On NonDirty Line in S State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Directory Miss : On Dirty Line in A State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Directory Miss : On Dirty Line in I State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Directory Miss : On Dirty Line in L State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Directory Miss : On Dirty Line in S State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.",
+ "EventCode": "0x2e",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Distress signal asserted : DPT Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Distress signal asserted : DPT Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Distress signal asserted : PMM Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Distress signal asserted : PMM Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "UNC_M2M_DISTRESS_PMM",
+ "EventCode": "0xF2",
+ "EventName": "UNC_M2M_DISTRESS_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE",
+ "EventCode": "0xF1",
+ "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "EventCode": "0xBA",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xBA",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Horizontal IV Ring in Use : Left",
+ "EventCode": "0xB9",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Horizontal IV Ring in Use : Right",
+ "EventCode": "0xB9",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x704",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x104",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x140",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x102",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x101",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x110",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x108",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
+ "UMask": "0x120",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x204",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x240",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x202",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x201",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x210",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x208",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
+ "UMask": "0x220",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x440",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x740",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ISOCH",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x702",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.NORMAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x701",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x710",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x708",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.TO_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x720",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1c10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x410",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x401",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x404",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_NI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x402",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x408",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x440",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x420",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
+ "UMask": "0x480",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x810",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x801",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x804",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_NI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x802",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x808",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x840",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x820",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
+ "UMask": "0x880",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
+ "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x1c01",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x1c04",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.NI",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1c02",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1c08",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1c40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1c20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x1c80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Write Tracker Inserts",
+ "EventCode": "0x64",
+ "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "BriefDescription": "Write Tracker Occupancy",
+ "EventCode": "0x65",
+ "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "EventCode": "0xE6",
+ "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "EventCode": "0xE6",
+ "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Number Packet Header Matches : MC Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Number Packet Header Matches : Mesh Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MESH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "EventCode": "0x73",
+ "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Prefetch CAM Cycles Full : Channel 2",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
+ "EventCode": "0x6f",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2a",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
+ "EventCode": "0x6f",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x15",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
"PerPkg": "1",
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels",
+ "UMask": "0x15",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AK",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x15",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.IV",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
"PerPkg": "1",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AK",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.IV",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY",
"PerPkg": "1",
"UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
+ "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
+ "EventCode": "0x6d",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x2a",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x15",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "BriefDescription": "Prefetch CAM Occupancy : All Channels",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "Prefetch CAM Occupancy : Channel 2",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": ": All Channels",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": ": Channel 0",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": ": Channel 1",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "BriefDescription": ": Channel 2",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+ "EventCode": "0x79",
+ "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
+ "EventCode": "0x78",
+ "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+ "EventCode": "0x77",
+ "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_M2M_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD",
+ "BriefDescription": "AD Ingress (from CMS) Full",
+ "EventCode": "0x04",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK",
+ "BriefDescription": "AD Ingress (from CMS) Not Empty",
+ "EventCode": "0x03",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
+ "BriefDescription": "AD Ingress (from CMS) Allocations",
+ "EventCode": "0x01",
+ "EventName": "UNC_M2M_RxC_AD_INSERTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
+ "BriefDescription": "AD Ingress (from CMS) Occupancy",
+ "EventCode": "0x02",
+ "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
+ "EventCode": "0x77",
+ "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M2M_RxC_AK_WR_CMP",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "BriefDescription": "BL Ingress (from CMS) Full",
+ "EventCode": "0x08",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "BL Ingress (from CMS) Not Empty",
+ "EventCode": "0x07",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "BL Ingress (from CMS) Allocations",
+ "EventCode": "0x05",
+ "EventName": "UNC_M2M_RxC_BL_INSERTS",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "BriefDescription": "BL Ingress (from CMS) Occupancy",
+ "EventCode": "0x06",
+ "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
- "PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "BriefDescription": "Transgress Ingress Bypass : AK",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : AK",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
+ "BriefDescription": "Transgress Injection Starvation : IV",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD",
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AK",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
+ "BriefDescription": "Transgress Ingress Allocations : AK",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
+ "BriefDescription": "Transgress Ingress Occupancy : AK",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD",
+ "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK",
+ "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
+ "BriefDescription": "Retry - Mem Mirroring Mode",
+ "EventCode": "0x35",
+ "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
+ "BriefDescription": "Retry - Mem Mirroring Mode",
+ "EventCode": "0x36",
+ "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
+ "BriefDescription": "Scoreboard Accepts",
+ "EventCode": "0x2F",
+ "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
+ "BriefDescription": "Scoreboard Rejects",
+ "EventCode": "0x30",
+ "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
+ "BriefDescription": "Scoreboard Accepts",
+ "EventCode": "0x31",
+ "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "Scoreboard Rejects",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
+ "BriefDescription": "Tag Hit : Clean NearMem Read Hit",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs).",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
+ "BriefDescription": "Tag Hit : Dirty NearMem Read Hit",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs).",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
+ "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0",
+ "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1",
+ "BriefDescription": "Tag Miss",
+ "EventCode": "0x61",
+ "EventName": "UNC_M2M_TAG_MISS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "BriefDescription": "Number AD Ingress Credits",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2M_TGR_AD_CREDITS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "BriefDescription": "Number BL Ingress Credits",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2M_TGR_BL_CREDITS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "BriefDescription": "Tracker Cycles Full : Channel 0",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_FULL.CH0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "BriefDescription": "Tracker Cycles Full : Channel 1",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "BriefDescription": "Tracker Cycles Full : Channel 2",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_FULL.CH2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "BriefDescription": "Tracker Inserts : Channel 0",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "BriefDescription": "Tracker Inserts : Channel 1",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "BriefDescription": "Tracker Inserts : Channel 2",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_NE.CH0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0",
+ "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_NE.CH1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
+ "BriefDescription": "Tracker Cycles Not Empty : Channel 2",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_NE.CH2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
+ "BriefDescription": "Tracker Occupancy : Channel 0",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
+ "BriefDescription": "Tracker Occupancy : Channel 1",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
+ "BriefDescription": "Tracker Occupancy : Channel 2",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
+ "BriefDescription": "AD Egress (to CMS) Credit Acquired",
+ "EventCode": "0x0d",
+ "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
+ "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+ "EventCode": "0x0e",
+ "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0",
+ "BriefDescription": "AD Egress (to CMS) Full",
+ "EventCode": "0x0c",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1",
+ "BriefDescription": "AD Egress (to CMS) Not Empty",
+ "EventCode": "0x0b",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC",
+ "BriefDescription": "AD Egress (to CMS) Allocations",
+ "EventCode": "0x09",
+ "EventName": "UNC_M2M_TxC_AD_INSERTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+ "EventCode": "0x0f",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "AD Egress (to CMS) Occupancy",
+ "EventCode": "0x0A",
+ "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.NDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "AKC Credits",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M2M_TxC_AKC_CREDITS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD",
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Full : All",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x3",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x88",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0xa0",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x90",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "AK Egress (to CMS) Not Empty : All",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x3",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
+ "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Not Empty",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD",
+ "BriefDescription": "AK Egress (to CMS) Not Empty",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "AK Egress (to CMS) Not Empty",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "AK Egress (to CMS) Allocations : All",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "AK Egress (to CMS) Occupancy : All",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "AK Egress (to CMS) Occupancy",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "AK Egress (to CMS) Occupancy",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "AK Egress (to CMS) Occupancy",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "BL Egress (to CMS) Full : All",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "BL Egress (to CMS) Not Empty : All",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "BL Egress (to CMS) Allocations : All",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
- {
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ {
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
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- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AK",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.IV",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AK",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.IV",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "Vertical IV Ring in Use : Down",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "WPQ Flush : Channel 0",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "WPQ Flush : Channel 1",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "WPQ Flush : Channel 2",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_WPQ_FLUSH.CH2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0",
+ "EventCode": "0x51",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1",
+ "EventCode": "0x51",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2",
+ "EventCode": "0x51",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "Write Tracker Cycles Full : Channel 0",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "Write Tracker Cycles Full : Channel 1",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "Write Tracker Cycles Full : Channel 2",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "Write Tracker Cycles Full : Mirror",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "Write Tracker Inserts : Channel 0",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "Write Tracker Inserts : Channel 1",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "Write Tracker Inserts : Channel 2",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.CH2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "Write Tracker Cycles Not Empty",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "Write Tracker Cycles Not Empty",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
+ "EventCode": "0x63",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
+ "EventCode": "0x63",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2",
+ "EventCode": "0x63",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
+ "EventCode": "0x62",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
+ "EventCode": "0x62",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2",
+ "EventCode": "0x62",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "Write Tracker Occupancy : Channel 0",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
+ "BriefDescription": "Write Tracker Occupancy : Channel 1",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "Write Tracker Occupancy : Channel 2",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
+ "BriefDescription": "Write Tracker Occupancy : Mirror",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
+ "BriefDescription": "Write Tracker Occupancy",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
+ "BriefDescription": "Write Tracker Occupancy",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
+ "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "Write Tracker Posted Inserts : Channel 2",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "Write Tracker Posted Occupancy : Channel 2",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8b",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8b",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8b",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x8d",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x8d",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x8d",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8f",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8f",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8f",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
+ "EventCode": "0x01",
+ "EventName": "UNC_M2P_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M2P_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "BriefDescription": "Distress signal asserted : DPT Local",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
+ "BriefDescription": "Distress signal asserted : DPT Remote",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
+ "BriefDescription": "Distress signal asserted : PMM Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
+ "BriefDescription": "Distress signal asserted : PMM Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "EventCode": "0xba",
+ "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xba",
+ "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "BriefDescription": "Horizontal IV Ring in Use : Left",
+ "EventCode": "0xb9",
+ "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "BriefDescription": "Horizontal IV Ring in Use : Right",
+ "EventCode": "0xb9",
+ "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
"PerPkg": "1",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
"PerPkg": "1",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
"UMask": "0x20",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
+ "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
+ "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
+ "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8b",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "EventCode": "0xe6",
+ "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8b",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "EventCode": "0xe6",
+ "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8b",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "P2P Credit Occupancy : All",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "P2P Credit Occupancy : Local NCB",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "P2P Credit Occupancy : Local NCS",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "P2P Credit Occupancy : Remote NCB",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "P2P Credit Occupancy : Remote NCS",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Dedicated Credits Received : All",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Dedicated Credits Received : Local NCB",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Dedicated Credits Received : Local NCS",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Dedicated Credits Received : Remote NCB",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Dedicated Credits Received : Remote NCS",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Shared Credits Received : All",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Shared Credits Received : Local NCB",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Shared Credits Received : Local NCS",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Shared Credits Received : Remote NCB",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Shared Credits Received : Remote NCS",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8d",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8d",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8d",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8f",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8f",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8f",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xba",
- "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS",
+ "EventCode": "0x4d",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xba",
- "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB",
+ "EventCode": "0x4d",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS",
+ "EventCode": "0x4d",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "EventCode": "0xac",
+ "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "EventCode": "0xac",
+ "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "EventCode": "0xac",
+ "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "EventCode": "0xac",
+ "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb9",
- "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb9",
- "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe6",
- "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe6",
- "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xac",
- "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_M2P_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xac",
- "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xac",
- "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xac",
- "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xe5",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xe5",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
"EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
"EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xe2",
+ "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xe2",
+ "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.IV",
+ "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xe3",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xe3",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : IV",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xe1",
+ "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AK",
+ "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AK",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.IV",
+ "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
+ "EventName": "UNC_M2P_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xe0",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AK",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AK",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xd6",
+ "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xd6",
+ "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd1",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd1",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd1",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd3",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd3",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd3",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd5",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd5",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd5",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2P_TxC_CREDITS.PMM",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
+ "EventCode": "0x2d",
+ "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd6",
- "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd6",
- "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd1",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd1",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd1",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd3",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd3",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd3",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd7",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd7",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd7",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xa6",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa6",
"EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xa7",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xa7",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xa2",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xa2",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xa3",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xa3",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xa1",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xa1",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xa4",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xa4",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xa0",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xa0",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xa5",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"EventCode": "0x9c",
- "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"EventCode": "0x9c",
- "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9e",
"EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9e",
"EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x95",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x95",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x97",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x97",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x93",
"EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x93",
"EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x99",
"EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x99",
"EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x91",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x91",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb0",
- "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb0",
- "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
- "PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb4",
- "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xb0",
+ "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb4",
- "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xb0",
+ "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb1",
- "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xb4",
+ "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb1",
- "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xb4",
+ "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb2",
- "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xb1",
+ "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb2",
- "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xb1",
+ "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb3",
- "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xb2",
+ "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xb2",
+ "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb3",
"EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xb3",
+ "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
+ "PerPkg": "1",
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
"EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
"EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
"EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
"EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
"EventCode": "0x81",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
"EventCode": "0x81",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
"EventCode": "0x81",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
"EventCode": "0x83",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
"EventCode": "0x83",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
"EventCode": "0x83",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
"EventCode": "0x89",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
"EventCode": "0x89",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
"EventCode": "0x89",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
"EventCode": "0x8B",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
"EventCode": "0x8B",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
"EventCode": "0x8B",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
"EventCode": "0x85",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
"EventCode": "0x85",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
"EventCode": "0x85",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
"EventCode": "0x87",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
"EventCode": "0x87",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
"EventCode": "0x87",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
"EventCode": "0x8D",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
"EventCode": "0x8D",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
"EventCode": "0x8D",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "CBox AD Credits Empty : Requests",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "CBox AD Credits Empty : Snoops",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "CBox AD Credits Empty : VNA Messages",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+ "PerPkg": "1",
+ "PublicDescription": "CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "CBox AD Credits Empty : Writebacks",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+ "PerPkg": "1",
+ "PublicDescription": "CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)",
+ "EventCode": "0x01",
+ "EventName": "UNC_M3UPI_CLOCKTICKS",
+ "PerPkg": "1",
+ "PublicDescription": "Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "D2C Sent",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M3UPI_D2C_SENT",
+ "PerPkg": "1",
+ "PublicDescription": "D2C Sent : Count cases BL sends direct to core",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "D2U Sent",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M3UPI_D2U_SENT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ",
+ "PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Distress signal asserted : PMM Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL",
+ "PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Distress signal asserted : PMM Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBA",
"EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xBA",
+ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "PerPkg": "1",
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB9",
"EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB9",
"EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO2",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO3",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO4",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO5",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO5",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE6",
"EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE6",
"EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AD - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AD - Slot 1",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AD - Slot 2",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AK - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AK - Slot 2",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : BL - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
"EventCode": "0xAA",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
"EventCode": "0xAA",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
"EventCode": "0xAA",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
"EventCode": "0xAD",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
"EventCode": "0xAD",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
"EventCode": "0xAD",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC",
+ "PerPkg": "1",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_M3UPI_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD",
+ "BriefDescription": "Lost Arb for VN0 : REQ on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD",
+ "BriefDescription": "Lost Arb for VN0 : RSP on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "Lost Arb for VN0 : SNP on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "Lost Arb for VN0 : NCB on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "Lost Arb for VN0 : NCS on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "Lost Arb for VN0 : RSP on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD",
+ "BriefDescription": "Lost Arb for VN0 : WB on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AK",
+ "BriefDescription": "Lost Arb for VN1 : REQ on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD",
+ "BriefDescription": "Lost Arb for VN1 : RSP on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.IV",
+ "BriefDescription": "Lost Arb for VN1 : SNP on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "Lost Arb for VN1 : NCB on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "Lost Arb for VN1 : NCS on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD",
+ "BriefDescription": "Lost Arb for VN1 : RSP on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "Lost Arb for VN1 : WB on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD",
+ "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK",
+ "BriefDescription": "Arb Miscellaneous : Max Parallel Win",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD",
+ "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV",
+ "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side)",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "No Credits to Arb for VN0 : REQ on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "No Credits to Arb for VN0 : RSP on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN0 : SNP on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AK",
+ "BriefDescription": "No Credits to Arb for VN0 : NCB on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN0 : NCS on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.IV",
+ "BriefDescription": "No Credits to Arb for VN0 : RSP on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "No Credits to Arb for VN0 : WB on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
- },
- {
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN1 : REQ on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL",
+ "BriefDescription": "No Credits to Arb for VN1 : RSP on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "No Credits to Arb for VN1 : SNP on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN1 : NCB on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK",
+ "BriefDescription": "No Credits to Arb for VN1 : NCS on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN1 : RSP on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV",
+ "BriefDescription": "No Credits to Arb for VN1 : WB on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Can't Arb for VN0 : REQ on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Can't Arb for VN0 : RSP on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "Can't Arb for VN0 : SNP on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL",
+ "BriefDescription": "Can't Arb for VN0 : NCB on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL",
+ "BriefDescription": "Can't Arb for VN0 : NCS on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "Can't Arb for VN0 : RSP on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "Can't Arb for VN0 : WB on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "Can't Arb for VN1 : REQ on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "Can't Arb for VN1 : RSP on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "Can't Arb for VN1 : SNP on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "Can't Arb for VN1 : NCB on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "BriefDescription": "Can't Arb for VN1 : NCS on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "BriefDescription": "Can't Arb for VN1 : RSP on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "Can't Arb for VN1 : WB on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "BriefDescription": "Miscellaneous Credit Events",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 1",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "Miscellaneous Credit Events",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 2",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "Miscellaneous Credit Events",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "Credit Occupancy : Credits Consumed",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "Credit Occupancy : D2K Credits",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
"PerPkg": "1",
+ "PublicDescription": "Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "Credit Occupancy : Packets in BGF FIFO",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "BriefDescription": "Credit Occupancy : Packets in BGF Path",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+ "PerPkg": "1",
+ "PublicDescription": "Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Credit Occupancy",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
"PerPkg": "1",
+ "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "BriefDescription": "Credit Occupancy",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "Credit Occupancy : Transmit Credits",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "Credit Occupancy : VNA In Use",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "Data Flit Not Sent : All",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "Data Flit Not Sent : No BGF Credits",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "Data Flit Not Sent : No TxQ Credits",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "Data Flit Not Sent : TSV High",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
"PerPkg": "1",
+ "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending completion fifo is full",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK",
+ "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": ": slot 2 request naturally serviced during hold-off period",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": ": slot 2 request forcibly serviced during service window",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": ": slot 2 request received from link layer while idle (with no slot 2 request active immediately prior)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": ": slot 2 request withdrawn during hold-off period or service window",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "BriefDescription": "Slotting BL Message Into Header Flit : All",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "Flit Gen - Header 1 : Accumulate",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "BriefDescription": "Flit Gen - Header 1",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK",
+ "BriefDescription": "Flit Gen - Header 1",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "BriefDescription": "Flit Gen - Header 1",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV",
+ "BriefDescription": "Flit Gen - Header 2 : Parallel Ok",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT",
"PerPkg": "1",
+ "PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "Flit Gen - Header 2 : Parallel Message",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "Sent Header Flit : One Message",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD",
+ "BriefDescription": "Sent Header Flit : One Message in non-VNA",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK",
+ "BriefDescription": "Sent Header Flit : Two Messages",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Sent Header Flit : Two Messages : Two messages in flit; VNA flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD",
+ "BriefDescription": "Sent Header Flit : Three Messages",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Sent Header Flit : Three Messages : Three messages in flit; VNA flit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV",
+ "BriefDescription": "Sent Header Flit : One Slot Taken",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "Sent Header Flit : Two Slots Taken",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "Sent Header Flit : All Slots Taken",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "BriefDescription": "Header Not Sent : All",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL",
+ "BriefDescription": "Header Not Sent : No BGF Credits",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD",
+ "BriefDescription": "Header Not Sent : No TxQ Credits",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK",
+ "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD",
+ "BriefDescription": "Header Not Sent : TSV High",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV",
+ "BriefDescription": "Header Not Sent : Cycle valid for Flit",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "Message Held : Can't Slot AD",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
"PerPkg": "1",
+ "PublicDescription": "Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "Message Held : Can't Slot BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD",
+ "BriefDescription": "Message Held : Parallel Attempt",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "Message Held : Parallel Success",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in paralle",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "Message Held : VN0",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.VN0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "Message Held : VN1",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.VN1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "BriefDescription": "VN0 message can't slot into flit : REQ on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "BriefDescription": "VN0 message can't slot into flit : RSP on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "BriefDescription": "VN0 message can't slot into flit : SNP on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "BriefDescription": "VN0 message can't slot into flit : NCB on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "BriefDescription": "VN0 message can't slot into flit : NCS on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "BriefDescription": "VN0 message can't slot into flit : RSP on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "BriefDescription": "VN0 message can't slot into flit : WB on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : REQ on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "BriefDescription": "VN1 message can't slot into flit : RSP on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : SNP on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : NCB on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : NCS on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : RSP on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "BriefDescription": "VN1 message can't slot into flit : WB on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "BriefDescription": "Remote VNA Credits : Any In Use",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
"PerPkg": "1",
+ "PublicDescription": "Remote VNA Credits : Any In Use : At least one remote vna credit is in use",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "BriefDescription": "Remote VNA Credits : Corrected",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "BriefDescription": "Remote VNA Credits : Level < 1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "BriefDescription": "Remote VNA Credits : Level < 10",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0",
+ "BriefDescription": "Remote VNA Credits : Level < 4",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0",
+ "BriefDescription": "Remote VNA Credits : Level < 5",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": ": remote vna credit count was less than 5 and allocation to ad or bl messages was required",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": ": remote vna credit count was less than 10 and allocation to vn0 or vn1 was required",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "PerPkg": "1",
+ "PublicDescription": ": on vn0, remote vna credits were allocated only to ad messages, not to bl",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": ": on vn0, remote vna credits were allocated only to bl messages, not to ad",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": ": remote vna credits were allocated only to vn0, not to vn1",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
"PerPkg": "1",
+ "PublicDescription": ": on vn1, remote vna credits were allocated only to ad messages, not to bl",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": ": on vn1, remote vna credits were allocated only to bl messages, not to ad",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": ": remote vna credits were allocated only to vn1, not to vn0",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : AK",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AK",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1",
+ "BriefDescription": "Transgress Injection Starvation : IV",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0",
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "Transgress Ingress Allocations : AK",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy : AK",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_CHA_RING_SRC_THRTL",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Counting disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_IIO_NOTHING",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PWT occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_IIO_PWT_OCCUPANCY",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Symbol Times on Link",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_IIO_SYMBOL_TIMES",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "P2P Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_I_P2P_INSERTS",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "P2P Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_I_P2P_OCCUPANCY",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress Allocations",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0B",
- "EventName": "UNC_I_TxC_AK_INSERTS",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL DRS Egress Cycles Full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL DRS Egress Inserts",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL DRS Egress Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x08",
- "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCB Egress Cycles Full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x06",
- "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCB Egress Inserts",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCB Egress Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x09",
- "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCS Egress Cycles Full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x07",
- "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCS Egress Inserts",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCS Egress Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0A",
- "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "No AD0 Egress Credits Stalls",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1A",
- "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "No AD1 Egress Credits Stalls",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1B",
- "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0D",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0E",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0C",
- "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Write Tracker Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x64",
- "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Write Tracker Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x65",
- "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x73",
- "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x79",
- "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x78",
- "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x77",
- "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_M2M_RING_SRC_THRTL",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M2M_RxC_AK_WR_CMP",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x08",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x07",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+ "BriefDescription": "Failed ARB for AD : VN0 REQ Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
+ "BriefDescription": "Failed ARB for AD : VN0 RSP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
+ "BriefDescription": "Failed ARB for AD : VN0 SNP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
+ "BriefDescription": "Failed ARB for AD : VN0 WB Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Retry - Mem Mirroring Mode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS",
+ "BriefDescription": "Failed ARB for AD : VN1 REQ Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Retry - Mem Mirroring Mode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS",
+ "BriefDescription": "Failed ARB for AD : VN1 RSP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Scoreboard Accepts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS",
+ "BriefDescription": "Failed ARB for AD : VN1 SNP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Scoreboard Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Failed ARB for AD : VN1 WB Messages",
"EventCode": "0x30",
- "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Scoreboard Accepts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Scoreboard Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number AD Ingress Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2M_TGR_AD_CREDITS",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number BL Ingress Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2M_TGR_BL_CREDITS",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Egress (to CMS) Credit Acquired",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0d",
- "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+ "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0e",
- "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+ "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0c",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+ "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0b",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+ "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0f",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+ "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+ "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AKC Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M2M_TxC_AKC_CREDITS",
+ "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_M2P_RING_SRC_THRTL",
+ "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
+ "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+ "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "D2C Sent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M3UPI_D2C_SENT",
+ "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "D2U Sent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M3UPI_D2U_SENT",
+ "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_M3UPI_RING_SRC_THRTL",
+ "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1",
+ "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AK Flow Q Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
+ "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AK Flow Q Occupancy",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
+ "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "FlowQ Generated Prefetch",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+ "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "IDI Lock/SplitLock Cycles",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_U_LOCK_CYCLES",
+ "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
"PerPkg": "1",
- "Unit": "UBOX"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "RACU Request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_U_RACU_REQUESTS",
+ "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
"PerPkg": "1",
- "Unit": "UBOX"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_UPI_PHY_INIT_CYCLES",
+ "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "L1 Req Nack",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_UPI_POWER_L1_NACK",
+ "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "L1 Req (same as L1 Ack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_UPI_POWER_L1_REQ",
+ "BriefDescription": "AK Flow Q Inserts",
+ "EventCode": "0x2F",
+ "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
+ "BriefDescription": "AK Flow Q Occupancy",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
+ "BriefDescription": "Failed ARB for BL : VN0 NCB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CRC Errors Detected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0B",
- "EventName": "UNC_UPI_RxL_CRC_ERRORS",
+ "BriefDescription": "Failed ARB for BL : VN0 NCS Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "LLR Requests Sent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x08",
- "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
+ "BriefDescription": "Failed ARB for BL : VN0 RSP Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Consumed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
+ "BriefDescription": "Failed ARB for BL : VN0 WB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Consumed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3A",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
+ "BriefDescription": "Failed ARB for BL : VN1 NCS Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VNA Credit Consumed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
+ "BriefDescription": "Failed ARB for BL : VN1 NCB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "BriefDescription": "Failed ARB for BL : VN1 RSP Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "BriefDescription": "Failed ARB for BL : VN1 WB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
+ "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Tx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_UPI_TxL_BYPASSED",
+ "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_UPI_TxL_INSERTS",
+ "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_UPI_TxL_OCCUPANCY",
+ "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VNA Credits Pending Return - Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
+ "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
+ "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x1FFFFF",
- "UMaskExt": "0x1FFF",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
+ "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
"PerPkg": "1",
- "UMask": "0x1bc1ff",
- "UMaskExt": "0x1bc1",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
+ "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x1A44FF",
- "UMaskExt": "0x1A44",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
+ "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x1bd0ff",
- "UMaskExt": "0x1bd0",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
+ "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x0bdfff",
- "UMaskExt": "0x0bdf",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
+ "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
"PerPkg": "1",
- "UMask": "0x15dfff",
- "UMaskExt": "0x15df",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE",
+ "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x1A04FF",
- "UMaskExt": "0x1A04",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE",
+ "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x1A01FF",
- "UMaskExt": "0x1A01",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE",
+ "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x1A08FF",
- "UMaskExt": "0x1A08",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE",
+ "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
"PerPkg": "1",
- "UMask": "0x1a10ff",
- "UMaskExt": "0x1a10",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x1C19FF",
- "UMaskExt": "0x1C19",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x1844FF",
- "UMaskExt": "0x1844",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x19C1FF",
- "UMaskExt": "0x19C1",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x19C8FF",
- "UMaskExt": "0x19C8",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x19d0ff",
- "UMaskExt": "0x19d0",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x189dff",
- "UMaskExt": "0x189d",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
+ "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0xC827FD01",
- "UMaskExt": "0xC827FD",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
"PerPkg": "1",
- "UMask": "0xC8A7FD01",
- "UMaskExt": "0xC8A7FD",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL",
"PerPkg": "1",
- "UMask": "0xC827FE01",
- "UMaskExt": "0xC827FE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH",
"PerPkg": "1",
- "UMask": "0xC8A7FE01",
- "UMaskExt": "0xC8A7FE",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL",
"PerPkg": "1",
- "UMask": "0xC88FFD01",
- "UMaskExt": "0xC88FFD",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL",
"PerPkg": "1",
- "UMask": "0xC897FD01",
- "UMaskExt": "0xC897FD",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
+ "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH",
"PerPkg": "1",
- "UMask": "0xC827FD01",
- "UMaskExt": "0xC827FD",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL",
"PerPkg": "1",
- "UMask": "0xC8A7FD01",
- "UMaskExt": "0xC8A7FD",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0xC887FD01",
- "UMaskExt": "0xC887FD",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0xC88FFE01",
- "UMaskExt": "0xC88FFE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC897FE01",
- "UMaskExt": "0xC897FE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0xC827FE01",
- "UMaskExt": "0xC827FE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC8A7FE01",
- "UMaskExt": "0xC8A7FE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC887FE01",
- "UMaskExt": "0xC887FE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0xC803FD04",
- "UMaskExt": "0xC803FD",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0xCC43FD04",
- "UMaskExt": "0xCC43FD",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC803FD04",
- "UMaskExt": "0xC803FD",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
+ "BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0xC803FF04",
- "UMaskExt": "0xC803FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xC817FF01",
- "UMaskExt": "0xC817FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0xC827FF01",
- "UMaskExt": "0xC827FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC8A7FF01",
- "UMaskExt": "0xC8A7FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; CRd Pref from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC88FFF01",
- "UMaskExt": "0xC88FFF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0xC803FF04",
- "UMaskExt": "0xC803FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
- "UMask": "0xCC43FF04",
- "UMaskExt": "0xCC43FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0xC887FF01",
- "UMaskExt": "0xC887FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xCCC7FF01",
- "UMaskExt": "0xCCC7FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0xC827FF01",
- "UMaskExt": "0xC827FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8A7FF01",
- "UMaskExt": "0xC8A7FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0xC88FFF01",
- "UMaskExt": "0xC88FFF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC897FF01",
- "UMaskExt": "0xC897FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC896FE01",
- "UMaskExt": "0xC896FE",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0xC8977E01",
- "UMaskExt": "0xC8977E",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
- "UMask": "0xC806FE01",
- "UMaskExt": "0xC806FE",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0xC8077E01",
- "UMaskExt": "0xC8077E",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC886FE01",
- "UMaskExt": "0xC886FE",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0xC8877E01",
- "UMaskExt": "0xC8877E",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8D7FF01",
- "UMaskExt": "0xC8D7FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0xCC47FF01",
- "UMaskExt": "0xCC47FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0xCC23FF04",
- "UMaskExt": "0xCC23FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8C3FF04",
- "UMaskExt": "0xC8C3FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0xcc27ff01",
- "UMaskExt": "0xcc27ff",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0xC8978A01",
- "UMaskExt": "0xC8978A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0xC8968A01",
- "UMaskExt": "0xC8968A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8970A01",
- "UMaskExt": "0xC8970A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0xc8678a01",
- "UMaskExt": "0xc8678a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xc8668a01",
- "UMaskExt": "0xc8668a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0xc8670a01",
- "UMaskExt": "0xc8670a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC8678601",
- "UMaskExt": "0xC86786",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8668601",
- "UMaskExt": "0xC86686",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0xc86f8a01",
- "UMaskExt": "0xc86f8a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
- "UMask": "0xc86e8a01",
- "UMaskExt": "0xc86e8a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0xc86f0a01",
- "UMaskExt": "0xc86f0a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC86F8601",
- "UMaskExt": "0xC86F86",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0xC86E8601",
- "UMaskExt": "0xC86E86",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8168A01",
- "UMaskExt": "0xC8168A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0xC8170A01",
- "UMaskExt": "0xC8170A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC8978A01",
- "UMaskExt": "0xC8978A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8968A01",
- "UMaskExt": "0xC8968A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0xC8970A01",
- "UMaskExt": "0xC8970A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0xc867fe01",
- "UMaskExt": "0xc867fe",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0xc8678a01",
- "UMaskExt": "0xc8678a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xc8668a01",
- "UMaskExt": "0xc8668a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0xc8670a01",
- "UMaskExt": "0xc8670a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xc86ffe01",
- "UMaskExt": "0xc86ffe",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
- {
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM",
+ {
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0xc86f8a01",
- "UMaskExt": "0xc86f8a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0xc86e8a01",
- "UMaskExt": "0xc86e8a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xc86f0a01",
- "UMaskExt": "0xc86f0a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "1",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "2",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "3",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "4",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "5",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "6",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "7",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "8",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "9",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "13",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "12",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "11",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "10",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "15",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "14",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "16",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0xC86FFE01",
- "UMaskExt": "0xC86FFE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2P_TxC_CREDITS.PMM",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : RFO Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMaskExt": "0x800",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Transactions homed remotely Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMaskExt": "0x1000",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Remote snoop request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMaskExt": "0x400",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : All Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Data Read Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Write Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : CRd Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMaskExt": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Local request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMaskExt": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMaskExt": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Remote non-snoop request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMaskExt": "0x200",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : All Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x1fe001",
- "UMaskExt": "0x1fe0",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x1fc1ff",
- "UMaskExt": "0x1fc1",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Data Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x1bc101",
- "UMaskExt": "0x1bc1",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x841ff",
- "UMaskExt": "0x841",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x842ff",
- "UMaskExt": "0x842",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x888ff",
- "UMaskExt": "0x888",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x17c2ff",
- "UMaskExt": "0x17c2",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : All transactions from Remote Agents",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x1e20ff",
- "UMaskExt": "0x1e20",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_DISTRESS_PMM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xF2",
- "EventName": "UNC_M2M_DISTRESS_PMM",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xF1",
- "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ISOCH",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x0702",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x0740",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x1C04",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x1C08",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x1C20",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x1C40",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMaskExt": "0x1D",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x15",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x2a",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x0120",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x0108",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x0110",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x0220",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x0208",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x0210",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x0708",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x0710",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM",
+ "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x0480",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
+ "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x0420",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE",
+ "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x0440",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM",
+ "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x0880",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM",
+ "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x0820",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE",
+ "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x0840",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0",
+ "BriefDescription": "UPI0 AD Credits Empty : VNA",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1",
+ "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2",
+ "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0",
+ "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1",
+ "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2",
+ "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+ "PerPkg": "1",
+ "PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UPI0 BL Credits Empty : VNA",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL",
+ "BriefDescription": "FlowQ Generated Prefetch",
+ "EventCode": "0x29",
+ "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6d",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x2a",
- "Unit": "M2M"
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x15",
- "Unit": "M2M"
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PWC Hit to a 4K page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PWC Hit to a 2M page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PWC Hit to a 1G page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PWT Hit to a 256T page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PageWalk cache fill",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Global IOTLB invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Page-selective IOTLB invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Context cache global invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Domain-selective Context cache invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Device-selective Context cache invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical IV Ring in Use : Down",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Abort",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "ITC address map 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
+ "BriefDescription": "VN0 Credit Used : WB on BL",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Issuing to IOMMU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 Credit Used : NCB on BL",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Processing response from IOMMU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 Credit Used : REQ on AD",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Request Ownership",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 Credit Used : RSP on AD",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+ "PerPkg": "1",
+ "PublicDescription": "VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "VN0 Credit Used : SNP on AD",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Issuing final read or write of line",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 Credit Used : RSP on BL",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Writing line",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : WB on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Passing data to be written",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : NCB on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Occupancy of outbound request queue : To device",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC5",
- "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : REQ on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : RSP on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : SNP on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : RSP on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "VN1 Credit Used : WB on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+ "PerPkg": "1",
+ "PublicDescription": "VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : NCB on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : REQ on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : RSP on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : SNP on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : RSP on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : WB on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : NCB on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - pass complete : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : REQ on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : RSP on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - pass complete : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : SNP on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : RSP on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x82",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0xa0",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x81",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x90",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "PerPkg": "1",
+ "UMask": "0x84",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "PerPkg": "1",
+ "UMask": "0xc0",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
"UMask": "0x20",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number requests sent to PCIe from main die : From IRP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number requests sent to PCIe from main die : From ITC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.ARB",
"PerPkg": "1",
- "UMask": "0xC867FF01",
- "UMaskExt": "0xC867FF",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message is making arbitration request",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
"PerPkg": "1",
- "UMask": "0xC86FFF01",
- "UMaskExt": "0xC86FFF",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message arrived in ingress pipeline",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS",
"PerPkg": "1",
- "UMask": "0xC87FDE01",
- "UMaskExt": "0xC87FDE",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message took bypass path",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED",
"PerPkg": "1",
- "UMask": "0xC80EFE01",
- "UMaskExt": "0xC80EFE",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message was slotted into flit (non bypass)",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
"PerPkg": "1",
- "UMask": "0xC80F7E01",
- "UMaskExt": "0xC80F7E",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message lost arbitration",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
"PerPkg": "1",
- "UMask": "0xC88EFE01",
- "UMaskExt": "0xC88EFE",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message was dropped because it became too old",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
"PerPkg": "1",
- "UMask": "0xC88F7E01",
- "UMaskExt": "0xC88F7E",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
+ "BriefDescription": "Number of kfclks",
+ "EventCode": "0x01",
+ "EventName": "UNC_UPI_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0xCD47FF01",
- "UMaskExt": "0xCD47FF",
- "Unit": "CHA"
+ "PublicDescription": "Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the GT/s speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
+ "BriefDescription": "Direct packet attempts : D2C",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
"PerPkg": "1",
- "UMask": "0xCC47FD01",
- "UMaskExt": "0xCC47FD",
- "Unit": "CHA"
+ "PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
+ "BriefDescription": "Direct packet attempts : D2K",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
"PerPkg": "1",
- "UMask": "0xCC47FE01",
- "UMaskExt": "0xCC47FE",
- "Unit": "CHA"
+ "PublicDescription": "Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0xC877DE01",
- "UMaskExt": "0xC877DE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
"PerPkg": "1",
- "UMask": "0xCCCFFF01",
- "UMaskExt": "0xCCCFFF",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
"PerPkg": "1",
- "UMask": "0xCCCFFD01",
- "UMaskExt": "0xCCCFFD",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
"PerPkg": "1",
- "UMask": "0xCCD7FD01",
- "UMaskExt": "0xCCD7FD",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0xCCCFFE01",
- "UMaskExt": "0xCCCFFE",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
+ "BriefDescription": "Cycles in L1",
+ "EventCode": "0x21",
+ "EventName": "UNC_UPI_L1_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0xCCCFFD01",
- "UMaskExt": "0xCCCFFD",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
"PerPkg": "1",
- "UMask": "0xCCD7FD01",
- "UMaskExt": "0xCCD7FD",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
"PerPkg": "1",
- "UMask": "0xCCCFFE01",
- "UMaskExt": "0xCCCFFE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
"PerPkg": "1",
- "UMask": "0xCCD7FE01",
- "UMaskExt": "0xCCD7FE",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "EventCode": "0x16",
+ "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.THROTTLE",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+ "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
+ "EventCode": "0x20",
+ "EventName": "UNC_UPI_PHY_INIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+ "BriefDescription": "L1 Req Nack",
+ "EventCode": "0x23",
+ "EventName": "UNC_UPI_POWER_L1_NACK",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+ "BriefDescription": "L1 Req (same as L1 Ack).",
+ "EventCode": "0x22",
+ "EventName": "UNC_UPI_POWER_L1_REQ",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x67",
- "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x67",
- "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH",
+ "BriefDescription": "Cycles in L0p",
+ "EventCode": "0x25",
+ "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI",
+ "BriefDescription": "Cycles in L0",
+ "EventCode": "0x24",
+ "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
"PerPkg": "1",
- "UMaskExt": "0x400",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : PMM Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : PMM Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Distress signal asserted : PMM Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Distress signal asserted : PMM Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Request",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0xC8678A01",
- "UMaskExt": "0xC8678A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
- "UMask": "0xC8668A01",
- "UMaskExt": "0xC8668A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x108",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
- "UMask": "0xC8670A01",
- "UMaskExt": "0xC8670A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x1aa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
- "UMask": "0xC86F8A01",
- "UMaskExt": "0xC86F8A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x12a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "UMask": "0xC86E8A01",
- "UMaskExt": "0xC86E8A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
- "UMask": "0xC86F0A01",
- "UMaskExt": "0xC86F0A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10c",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "UMask": "0xC8678A01",
- "UMaskExt": "0xC8678A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
- "UMask": "0xC8668A01",
- "UMaskExt": "0xC8668A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
- "UMask": "0xC8670A01",
- "UMaskExt": "0xC8670A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
- "UMask": "0xC86F8A01",
- "UMaskExt": "0xC86F8A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x109",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0xC86E8A01",
- "UMaskExt": "0xC86E8A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
- "UMask": "0xC86F0A01",
- "UMaskExt": "0xC86F0A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10d",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DDR4 Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.DDR",
+ "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DDR4 Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+ "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
+ "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
"PerPkg": "1",
- "UMask": "0xC8978601",
- "UMaskExt": "0xC89786",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "BriefDescription": "CRC Errors Detected",
+ "EventCode": "0x0B",
+ "EventName": "UNC_UPI_RxL_CRC_ERRORS",
"PerPkg": "1",
- "UMask": "0xC8968601",
- "UMaskExt": "0xC89686",
- "Unit": "CHA"
+ "PublicDescription": "CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "BriefDescription": "LLR Requests Sent",
+ "EventCode": "0x08",
+ "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
"PerPkg": "1",
- "UMask": "0xC8970601",
- "UMaskExt": "0xC89706",
- "Unit": "CHA"
+ "PublicDescription": "LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+ "BriefDescription": "VN0 Credit Consumed",
+ "EventCode": "0x39",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
"PerPkg": "1",
- "UMask": "0xC8678601",
- "UMaskExt": "0xC86786",
- "Unit": "CHA"
+ "PublicDescription": "VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+ "BriefDescription": "VN1 Credit Consumed",
+ "EventCode": "0x3A",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
"PerPkg": "1",
- "UMask": "0xC8668601",
- "UMaskExt": "0xC86686",
- "Unit": "CHA"
+ "PublicDescription": "VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "BriefDescription": "VNA Credit Consumed",
+ "EventCode": "0x38",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
"PerPkg": "1",
- "UMask": "0xC8670601",
- "UMaskExt": "0xC86706",
- "Unit": "CHA"
+ "PublicDescription": "VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+ "BriefDescription": "Valid Flits Received : All Data",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0xC86F8601",
- "UMaskExt": "0xC86F86",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+ "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0xC86E8601",
- "UMaskExt": "0xC86E86",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+ "BriefDescription": "Valid Flits Received : Data",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0xC86F0601",
- "UMaskExt": "0xC86F06",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
+ "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0xC8168601",
- "UMaskExt": "0xC81686",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
+ "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
"PerPkg": "1",
- "UMask": "0xC8170601",
- "UMaskExt": "0xC81706",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
+ "BriefDescription": "Valid Flits Received : LLCTRL",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0xC8978601",
- "UMaskExt": "0xC89786",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "BriefDescription": "Valid Flits Received : All Non Data",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0xC8968601",
- "UMaskExt": "0xC89686",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0xC8970601",
- "UMaskExt": "0xC89706",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
+ "BriefDescription": "Valid Flits Received : Protocol Header",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0xC8678601",
- "UMaskExt": "0xC86786",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
+ "BriefDescription": "Valid Flits Received : Slot 0",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0xC8668601",
- "UMaskExt": "0xC86686",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
+ "BriefDescription": "Valid Flits Received : Slot 1",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMask": "0xC8670601",
- "UMaskExt": "0xC86706",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
+ "BriefDescription": "Valid Flits Received : Slot 2",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
"PerPkg": "1",
- "UMask": "0xC86F8601",
- "UMaskExt": "0xC86F86",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
"PerPkg": "1",
- "UMask": "0xC86E8601",
- "UMaskExt": "0xC86E86",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
"PerPkg": "1",
- "UMask": "0xC86F0601",
- "UMaskExt": "0xC86F06",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
"PerPkg": "1",
- "UMask": "0xC8F3FD04",
- "UMaskExt": "0xC8F3FD",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
"PerPkg": "1",
- "UMask": "0xCCD7FF01",
- "UMaskExt": "0xCCD7FF",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
"PerPkg": "1",
- "UMask": "0xC867FE01",
- "UMaskExt": "0xC867FE",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
"PerPkg": "1",
- "UMask": "0xC867FE01",
- "UMaskExt": "0xC867FE",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
"PerPkg": "1",
- "UMask": "0xC86FFE01",
- "UMaskExt": "0xC86FFE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
"PerPkg": "1",
- "UMask": "0xC80EFE01",
- "UMaskExt": "0xC80EFE",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
"PerPkg": "1",
- "UMask": "0xC80F7E01",
- "UMaskExt": "0xC80F7E",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
"PerPkg": "1",
- "UMask": "0xC88EFE01",
- "UMaskExt": "0xC88EFE",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
"PerPkg": "1",
- "UMask": "0xC88F7E01",
- "UMaskExt": "0xC88F7E",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
"PerPkg": "1",
- "UMask": "0xC8C7FF01",
- "UMaskExt": "0xC8C7FF",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
"PerPkg": "1",
- "UMask": "0xC8D7FF01",
- "UMaskExt": "0xC8D7FF",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
"PerPkg": "1",
- "UMask": "0xCD47FF01",
- "UMaskExt": "0xCD47FF",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
"PerPkg": "1",
- "UMask": "0xCC57FF01",
- "UMaskExt": "0xCC57FF",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
"PerPkg": "1",
- "UMask": "0xCC27FF01",
- "UMaskExt": "0xCC27FF",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
"PerPkg": "1",
- "UMask": "0xCC47FF01",
- "UMaskExt": "0xCC47FF",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
"PerPkg": "1",
- "UMask": "0xCC47FD01",
- "UMaskExt": "0xCC47FD",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
"PerPkg": "1",
- "UMask": "0xCC47FE01",
- "UMaskExt": "0xCC47FE",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
"PerPkg": "1",
- "UMask": "0xC877DE01",
- "UMaskExt": "0xC877DE",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
+ "BriefDescription": "Cycles in L0p",
+ "EventCode": "0x27",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0xC87FDE01",
- "UMaskExt": "0xC87FDE",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "EventCode": "0x28",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
"PerPkg": "1",
- "UMask": "0xC867FF01",
- "UMaskExt": "0xC867FF",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "EventCode": "0x29",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
"PerPkg": "1",
- "UMask": "0xC86FFF01",
- "UMaskExt": "0xC86FFF",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
+ "BriefDescription": "Cycles in L0",
+ "EventCode": "0x26",
+ "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0xCCCFFF01",
- "UMaskExt": "0xCCCFFF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0xCC23FF04",
- "UMaskExt": "0xCC23FF",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMask": "0xC8C3FF04",
- "UMaskExt": "0xC8C3FF",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0xCD43FF04",
- "UMaskExt": "0xCD43FF",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0xCD43FD04",
- "UMaskExt": "0xCD43FD",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Request",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0xCD43FE04",
- "UMaskExt": "0xCD43FE",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
- "UMask": "0xc8678601",
- "UMaskExt": "0xc86786",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x108",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
- "UMask": "0xc8668601",
- "UMaskExt": "0xc86686",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x1aa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
- "UMask": "0xc8670601",
- "UMaskExt": "0xc86706",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x12a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "UMask": "0xc86f8601",
- "UMaskExt": "0xc86f86",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
- "UMask": "0xc86e8601",
- "UMaskExt": "0xc86e86",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10c",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "UMask": "0xc86f0601",
- "UMaskExt": "0xc86f06",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
- "UMask": "0xc8678601",
- "UMaskExt": "0xc86786",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
- "UMask": "0xc8668601",
- "UMaskExt": "0xc86686",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
- "UMask": "0xc8670601",
- "UMaskExt": "0xc86706",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x109",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0xc86f8601",
- "UMaskExt": "0xc86f86",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
- "UMask": "0xc86e8601",
- "UMaskExt": "0xc86e86",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10d",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
+ "BriefDescription": "Tx Flit Buffer Bypassed",
+ "EventCode": "0x41",
+ "EventName": "UNC_UPI_TxL_BYPASSED",
"PerPkg": "1",
- "UMask": "0xc86f0601",
- "UMaskExt": "0xc86f06",
- "Unit": "CHA"
+ "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
+ "BriefDescription": "Valid Flits Sent : All Data",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0xcc3fff01",
- "UMaskExt": "0xcc3fff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+ "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0x71",
- "Unit": "IRP"
+ "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+ "BriefDescription": "Valid Flits Sent : Data",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0x7e",
- "Unit": "IRP"
+ "PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+ "BriefDescription": "Valid Flits Sent : Idle",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0x74",
- "Unit": "IRP"
+ "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+ "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
"PerPkg": "1",
- "UMask": "0x72",
- "Unit": "IRP"
+ "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM",
+ "BriefDescription": "Valid Flits Sent : LLCTRL",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0xcc57fe01",
- "UMaskExt": "0xcc57fe",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM",
+ "BriefDescription": "Valid Flits Sent : All Non Data",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0xcc57fe01",
- "UMaskExt": "0xcc57fe",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
+ "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0xC837FE01",
- "UMaskExt": "0xC837FE",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
+ "BriefDescription": "Valid Flits Sent : Protocol Header",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0xC837FD01",
- "UMaskExt": "0xC837FD",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+ "BriefDescription": "Valid Flits Sent : Slot 0",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0xC837FF01",
- "UMaskExt": "0xC837FF",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM",
+ "BriefDescription": "Valid Flits Sent : Slot 1",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMask": "0xcc57fd01",
- "UMaskExt": "0xcc57fd",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
+ "BriefDescription": "Valid Flits Sent : Slot 2",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
"PerPkg": "1",
- "UMask": "0xcc67ff01",
- "UMaskExt": "0xcc67ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
+ "BriefDescription": "Tx Flit Buffer Allocations",
+ "EventCode": "0x40",
+ "EventName": "UNC_UPI_TxL_INSERTS",
"PerPkg": "1",
- "UMask": "0xcc37ff01",
- "UMaskExt": "0xcc37ff",
- "Unit": "CHA"
+ "PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
+ "BriefDescription": "Tx Flit Buffer Occupancy",
+ "EventCode": "0x42",
+ "EventName": "UNC_UPI_TxL_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0xcc2fff01",
- "UMaskExt": "0xcc2fff",
- "Unit": "CHA"
+ "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
+ "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "EventCode": "0x45",
+ "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
"PerPkg": "1",
- "UMask": "0xC837FF01",
- "UMaskExt": "0xC837FF",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
+ "BriefDescription": "VNA Credits Pending Return - Occupancy",
+ "EventCode": "0x44",
+ "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0xC837FD01",
- "UMaskExt": "0xC837FD",
- "Unit": "CHA"
+ "PublicDescription": "VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
+ "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+ "EventCode": "0xff",
+ "EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0xC837FE01",
- "UMaskExt": "0xC837FE",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x77",
- "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
+ "BriefDescription": "Message Received : Doorbell",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Code Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
+ "BriefDescription": "Message Received : Interrupt",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
"PerPkg": "1",
- "UMask": "0x1BD001",
- "UMaskExt": "0x1BD0",
- "Unit": "CHA"
+ "PublicDescription": "Message Received : Interrupt : Interrupts",
+ "UMask": "0x10",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : RFO Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
+ "BriefDescription": "Message Received : IPI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
"PerPkg": "1",
- "UMask": "0x1BC801",
- "UMaskExt": "0x1BC8",
- "Unit": "CHA"
+ "PublicDescription": "Message Received : IPI : Inter Processor Interrupts",
+ "UMask": "0x4",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ",
+ "BriefDescription": "Message Received : MSI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
"PerPkg": "1",
- "UMask": "0x1BD9FF",
- "UMaskExt": "0x1BD9",
- "Unit": "CHA"
+ "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
+ "BriefDescription": "Message Received : VLW",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
"PerPkg": "1",
- "UMask": "0x1BD901",
- "UMaskExt": "0x1BD9",
- "Unit": "CHA"
+ "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.",
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
+ "BriefDescription": "IDI Lock/SplitLock Cycles",
+ "EventCode": "0x44",
+ "EventName": "UNC_U_LOCK_CYCLES",
"PerPkg": "1",
- "UMask": "0x0BD901",
- "UMaskExt": "0x0BD9",
- "Unit": "CHA"
+ "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
"PerPkg": "1",
- "UMask": "0x13D901",
- "UMaskExt": "0x13D9",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
"PerPkg": "1",
- "UMask": "0x09D9FF",
- "UMaskExt": "0x09D9",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
"PerPkg": "1",
- "UMask": "0x0A19FF",
- "UMaskExt": "0x0A19",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
"PerPkg": "1",
- "UMask": "0x11D9FF",
- "UMaskExt": "0x11D9",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
+ "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
"PerPkg": "1",
- "UMask": "0x1BD90E",
- "UMaskExt": "0x1BD9",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
"PerPkg": "1",
- "UMask": "0x161901",
- "UMaskExt": "0x1619",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
- "FCMask": "0x04",
+ "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x03",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
+ "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
"PerPkg": "1",
- "UMask": "0x1A42FF",
- "UMaskExt": "0x1A42",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Transactions homed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
"PerPkg": "1",
- "UMask": "0x0BDFFF",
- "UMaskExt": "0x0BDF",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Transactions homed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
"PerPkg": "1",
- "UMask": "0x15DFFF",
- "UMaskExt": "0x15DF",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
"PerPkg": "1",
- "UMask": "0x1A10FF",
- "UMaskExt": "0x1A10",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
"PerPkg": "1",
- "UMask": "0x19D0FF",
- "UMaskExt": "0x19D0",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
"PerPkg": "1",
- "UMask": "0x189DFF",
- "UMaskExt": "0x189D",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Code Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
"PerPkg": "1",
- "UMask": "0x1BD0FF",
- "UMaskExt": "0x1BD0",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
- "FCMask": "0x04",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
"PerPkg": "1",
- "UMask": "0xFF",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
+ "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+ "EventCode": "0x4F",
+ "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
"PerPkg": "1",
- "UMask": "0x15",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
+ "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+ "EventCode": "0x4F",
+ "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
+ "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
+ "EventCode": "0x45",
+ "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.",
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
+ "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
+ "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDRAND",
"PerPkg": "1",
- "UMask": "0x15",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
+ "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDSEED",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
+ "BriefDescription": "RACU Request",
+ "EventCode": "0x46",
+ "EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker",
+ "Unit": "UBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
index 281f3605881d..ee4dac6fc797 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
@@ -1,16 +1,13 @@
[
{
"BriefDescription": "Clockticks of the power control unit (PCU)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -18,8 +15,6 @@
},
{
"BriefDescription": "UNC_P_DEMOTIONS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS",
"PerPkg": "1",
@@ -27,44 +22,38 @@
},
{
"BriefDescription": "Phase Shed 0 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 1 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 2 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 3 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
"Unit": "PCU"
},
{
"BriefDescription": "AVX256 Frequency Clipping",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x49",
"EventName": "UNC_P_FREQ_CLIP_AVX256",
"PerPkg": "1",
@@ -72,8 +61,6 @@
},
{
"BriefDescription": "AVX512 Frequency Clipping",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x4a",
"EventName": "UNC_P_FREQ_CLIP_AVX512",
"PerPkg": "1",
@@ -81,155 +68,137 @@
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x05",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C3 : Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x06",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
- "BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0A",
- "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+ "BriefDescription": "Number of cores in C-State : C0 and C1",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
+ "PublicDescription": "Number of cores in C-State : C0 and C1 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x09",
- "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+ "BriefDescription": "Number of cores in C-State : C3",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
+ "PublicDescription": "Number of cores in C-State : C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+ "BriefDescription": "Number of cores in C-State : C6 and C7",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
+ "PublicDescription": "Number of cores in C-State : C6 and C7 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_P_VR_HOT_CYCLES",
+ "BriefDescription": "External Prochot",
+ "EventCode": "0x0A",
+ "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State : C0 and C1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+ "BriefDescription": "Internal Prochot",
+ "EventCode": "0x09",
+ "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State : C3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+ "BriefDescription": "Total Core C State Transition Cycles",
+ "EventCode": "0x72",
+ "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State : C6 and C7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+ "BriefDescription": "VR Hot",
+ "EventCode": "0x42",
+ "EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
"Unit": "PCU"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
index d70864da5c67..e3227c7f2fe9 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
@@ -1,269 +1,181 @@
[
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
"SampleAfterValue": "100007",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "STLB flush attempts",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
"SampleAfterValue": "100007",
- "Speculative": "1",
"UMask": "0x20"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 8949b58f89be..7e489749a0d4 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -12,7 +12,7 @@ GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-(3C|45|46),v32,haswell,core
GenuineIntel-6-3F,v26,haswellx,core
GenuineIntel-6-(7D|7E|A7),v1.15,icelake,core
-GenuineIntel-6-6[AC],v1.16,icelakex,core
+GenuineIntel-6-6[AC],v1.17,icelakex,core
GenuineIntel-6-3A,v22,ivybridge,core
GenuineIntel-6-3E,v22,ivytown,core
GenuineIntel-6-2D,v21,jaketown,core
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 16/32] perf vendor events intel: Refresh ivybridge metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (5 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 15/32] perf vendor events intel: Refresh icelakex " Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 17/32] perf vendor events intel: Refresh ivytown " Ian Rogers
` (15 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the ivybridge metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
events are unchanged but the version number is 23 to match the perfmon
version. In the events unused json values are removed. The formatting
changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/ivybridge/cache.json | 235 ----------------
.../arch/x86/ivybridge/floating-point.json | 34 ---
.../arch/x86/ivybridge/frontend.json | 60 -----
.../arch/x86/ivybridge/ivb-metrics.json | 119 +++++----
.../pmu-events/arch/x86/ivybridge/memory.json | 54 ----
.../pmu-events/arch/x86/ivybridge/other.json | 8 -
.../arch/x86/ivybridge/pipeline.json | 250 ------------------
.../arch/x86/ivybridge/uncore-cache.json | 50 ----
.../arch/x86/ivybridge/uncore-other.json | 28 +-
.../arch/x86/ivybridge/virtual-memory.json | 36 ---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
11 files changed, 76 insertions(+), 800 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
index 8adb2e45e23d..6ddc7d1c61d5 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts the number of lines brought into the L1 data cache.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "L1D miss oustandings duration in cycles",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -54,8 +44,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.ALL",
"SampleAfterValue": "200003",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_E",
"PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
@@ -73,8 +59,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_M",
"PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
@@ -83,8 +67,6 @@
},
{
"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.MISS",
"PublicDescription": "Not rejected writebacks that missed LLC.",
@@ -93,8 +75,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "L2 cache lines filling L2.",
@@ -103,8 +83,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "L2 cache lines in E state filling L2.",
@@ -113,8 +91,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "L2 cache lines in I state filling L2.",
@@ -123,8 +99,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "L2 cache lines in S state filling L2.",
@@ -133,8 +107,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by demand.",
@@ -143,8 +115,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by demand.",
@@ -153,8 +123,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines filling the L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DIRTY_ALL",
"PublicDescription": "Dirty L2 cache lines filling the L2.",
@@ -163,8 +131,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
@@ -173,8 +139,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
@@ -183,8 +147,6 @@
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts all L2 code requests.",
@@ -193,8 +155,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
@@ -203,8 +163,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts all L2 HW prefetcher requests.",
@@ -213,8 +171,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts all L2 store RFO requests.",
@@ -223,8 +179,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
@@ -233,8 +187,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
@@ -243,8 +195,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Demand Data Read requests that hit L2 cache.",
@@ -253,8 +203,6 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
@@ -263,8 +211,6 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
@@ -273,8 +219,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "RFO requests that hit L2 cache.",
@@ -283,8 +227,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
@@ -293,8 +235,6 @@
},
{
"BriefDescription": "RFOs that access cache lines in any state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.ALL",
"PublicDescription": "RFOs that access cache lines in any state.",
@@ -303,8 +243,6 @@
},
{
"BriefDescription": "RFOs that hit cache lines in M state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
"PublicDescription": "RFOs that hit cache lines in M state.",
@@ -313,8 +251,6 @@
},
{
"BriefDescription": "RFOs that miss cache lines",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.MISS",
"PublicDescription": "RFOs that miss cache lines.",
@@ -323,8 +259,6 @@
},
{
"BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
@@ -333,8 +267,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "Transactions accessing L2 pipe.",
@@ -343,8 +275,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "L2 cache accesses when fetching instructions.",
@@ -353,8 +283,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "Demand Data Read requests that access L2 cache.",
@@ -363,8 +291,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "L1D writebacks that access L2 cache.",
@@ -373,8 +299,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "L2 fill requests that access L2 cache.",
@@ -383,8 +307,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "L2 writebacks that access L2 cache.",
@@ -393,8 +315,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "RFO requests that access L2 cache.",
@@ -403,8 +323,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D is locked.",
@@ -413,8 +331,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
@@ -423,8 +339,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
@@ -433,8 +347,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
"PEBS": "1",
@@ -443,8 +355,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
@@ -453,8 +363,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
@@ -463,8 +371,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
@@ -473,8 +379,6 @@
},
{
"BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
"PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).",
@@ -483,8 +387,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -493,8 +395,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
@@ -503,8 +403,6 @@
},
{
"BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PEBS": "1",
@@ -513,8 +411,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
@@ -523,8 +419,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache misses as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PEBS": "1",
@@ -533,8 +427,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
"PEBS": "1",
@@ -543,8 +435,6 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -553,8 +443,6 @@
},
{
"BriefDescription": "All retired load uops. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
@@ -563,8 +451,6 @@
},
{
"BriefDescription": "All retired store uops. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
@@ -573,8 +459,6 @@
},
{
"BriefDescription": "Retired load uops with locked access. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
@@ -583,8 +467,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
@@ -593,8 +475,6 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
@@ -603,8 +483,6 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
@@ -613,8 +491,6 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PEBS": "1",
@@ -623,8 +499,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
@@ -633,8 +507,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Demand code read requests sent to uncore.",
@@ -643,8 +515,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Demand data read requests sent to uncore.",
@@ -653,8 +523,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
@@ -663,8 +531,6 @@
},
{
"BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
@@ -673,8 +539,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -683,8 +547,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -694,8 +556,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -705,8 +565,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -716,8 +574,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -727,8 +583,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -737,8 +591,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -747,8 +599,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -758,8 +608,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -768,332 +616,249 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x000105B3",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x000107F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch prefetch RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all writebacks from the core to the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10008",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand rfo's",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts non-temporal stores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
index 4c2ac010cf55..87c958213c7a 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@@ -12,8 +10,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "Number of X87 FP assists due to input values.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "Number of X87 FP assists due to output values.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"PublicDescription": "Counts number of X87 uops executed.",
@@ -102,8 +82,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -120,8 +96,6 @@
},
{
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
@@ -130,8 +104,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
@@ -139,8 +111,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
@@ -148,8 +118,6 @@
},
{
"BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
@@ -158,8 +126,6 @@
},
{
"BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
index 2b1a82dd86ab..89004a6c9ed1 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"PublicDescription": "Number of DSB to MITE switches.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Cycles DSB to MITE switches caused delay.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"PublicDescription": "DSB Fill encountered > 3 DSB lines.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFETCH_STALL",
"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -93,8 +75,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -104,8 +84,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -115,8 +93,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -126,8 +102,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -136,8 +110,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "Counts cycles the IDQ is empty.",
@@ -146,8 +118,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -156,8 +126,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -167,8 +135,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -177,8 +143,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -188,8 +152,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -199,8 +161,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -211,8 +171,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -221,8 +179,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -231,8 +187,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -243,8 +197,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
@@ -253,8 +205,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
@@ -263,8 +213,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -273,8 +221,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -284,8 +230,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -294,8 +238,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -304,8 +246,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
index 63db3397af0f..88980c1a3a64 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
@@ -88,7 +88,7 @@
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -96,7 +96,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -120,7 +120,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+ "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -152,7 +152,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+ "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
@@ -192,7 +192,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -200,7 +200,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / CLKS",
+ "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -208,7 +208,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS",
+ "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -216,7 +216,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS",
+ "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -224,7 +224,7 @@
},
{
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_sq_full",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -232,7 +232,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -264,7 +264,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -312,7 +312,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
+ "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -320,7 +320,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0",
"PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@@ -328,7 +328,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_1",
"PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
@@ -336,7 +336,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_2",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
@@ -344,7 +344,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
- "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m",
"ScaleUnit": "100%"
@@ -400,7 +400,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricExpr": "tma_port_4",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_store_op_utilization",
"ScaleUnit": "100%"
@@ -470,7 +470,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -543,19 +543,19 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
+ "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
@@ -622,7 +622,7 @@
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
@@ -634,7 +634,7 @@
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
"MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency"
},
@@ -646,19 +646,19 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
@@ -671,19 +671,19 @@
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
@@ -713,19 +713,19 @@
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1000000000) / duration_time",
+ "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -738,7 +738,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@@ -756,68 +756,87 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+ "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+ "MetricExpr": "MEM_Parallel_Requests",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Request_Latency"
},
{
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+ "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests"
},
+ {
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "UNC_CLOCK.SOCKET",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
+ },
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
+ {
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
+ },
{
"BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
index 30fc0af61eb3..fd1fe491c577 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Loads with latency value being above 128",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
@@ -19,13 +15,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 128.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 16",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
@@ -33,13 +26,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 16.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
@@ -47,13 +37,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 256.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 32",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
@@ -61,13 +48,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 32.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
@@ -75,13 +59,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 4.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
@@ -89,13 +70,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 512.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 64",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
@@ -103,13 +81,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 64.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
@@ -117,25 +92,18 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 8.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
"PEBS": "2",
- "PRECISE_STORE": "1",
"SampleAfterValue": "2000003",
- "TakenAlone": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
@@ -144,8 +112,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
@@ -154,80 +120,60 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3004003f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts LLC replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6004001b3",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of any page walk that had a miss in LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBE",
"EventName": "PAGE_WALKS.LLC_MISS",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/other.json b/tools/perf/pmu-events/arch/x86/ivybridge/other.json
index 2d62521791d8..e80e99d064ba 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/other.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@@ -23,8 +19,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
index d89d3f8db190..d1e64e0d683e 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Divide operations executed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -13,8 +11,6 @@
},
{
"BriefDescription": "Cycles when divider is busy executing divide operations",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.",
@@ -23,8 +19,6 @@
},
{
"BriefDescription": "Speculative and retired branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"PublicDescription": "Speculative and retired macro-conditional branches.",
@@ -43,8 +35,6 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
@@ -53,8 +43,6 @@
},
{
"BriefDescription": "Speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"PublicDescription": "Speculative and retired direct near calls.",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Speculative and retired indirect branches excluding calls and returns.",
@@ -73,8 +59,6 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Not taken macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "Not taken macro-conditional branches.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "Taken speculative and retired macro-conditional branches.",
@@ -102,8 +82,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
@@ -112,8 +90,6 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"PublicDescription": "Taken speculative and retired direct near calls.",
@@ -122,8 +98,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
@@ -132,8 +106,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "Taken speculative and retired indirect calls.",
@@ -142,8 +114,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.",
@@ -152,8 +122,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "Branch instructions at retirement.",
@@ -161,8 +129,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -171,8 +137,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -181,8 +145,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PublicDescription": "Number of far branches retired.",
@@ -191,8 +153,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -201,8 +161,6 @@
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
@@ -211,8 +169,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -221,8 +177,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -231,8 +185,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "Counts the number of not taken branch instructions retired.",
@@ -241,8 +193,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -251,8 +201,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"PublicDescription": "Speculative and retired mispredicted macro conditional branches.",
@@ -261,8 +209,6 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Mispredicted indirect branches excluding calls and returns.",
@@ -271,8 +217,6 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
@@ -281,8 +225,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.",
@@ -291,8 +233,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -301,8 +241,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "Taken speculative and retired mispredicted indirect calls.",
@@ -311,8 +249,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
@@ -321,8 +257,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Mispredicted branch instructions at retirement.",
@@ -330,8 +264,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -340,8 +272,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -350,8 +280,6 @@
},
{
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -360,8 +288,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -369,8 +295,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
@@ -380,8 +304,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -389,8 +311,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -398,16 +318,12 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
@@ -417,8 +333,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -426,8 +340,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
"UMask": "0x2"
@@ -435,8 +347,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"SampleAfterValue": "2000003",
@@ -444,8 +354,6 @@
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
@@ -454,8 +362,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
@@ -463,8 +369,6 @@
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -473,8 +377,6 @@
},
{
"BriefDescription": "Cycles with pending L1 cache miss loads.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -484,8 +386,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss load* is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -494,8 +394,6 @@
},
{
"BriefDescription": "Cycles with pending L2 cache miss loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -505,8 +403,6 @@
},
{
"BriefDescription": "Cycles with pending memory loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -516,8 +412,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -526,8 +420,6 @@
},
{
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -537,8 +429,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -547,8 +437,6 @@
},
{
"BriefDescription": "Execution stalls due to L1 data cache misses",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -558,8 +446,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -568,8 +454,6 @@
},
{
"BriefDescription": "Execution stalls due to L2 cache misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -579,8 +463,6 @@
},
{
"BriefDescription": "Execution stalls due to memory subsystem.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -589,8 +471,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -599,8 +479,6 @@
},
{
"BriefDescription": "Total execution stalls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -609,8 +487,6 @@
},
{
"BriefDescription": "Stall cycles because IQ is full",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"PublicDescription": "Stall cycles due to IQ is full.",
@@ -619,8 +495,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000003",
@@ -628,16 +502,12 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PublicDescription": "Number of instructions at retirement.",
@@ -645,8 +515,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "2",
@@ -656,8 +524,6 @@
},
{
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -667,8 +533,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -677,8 +541,6 @@
},
{
"BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x0D",
@@ -688,8 +550,6 @@
},
{
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -698,8 +558,6 @@
},
{
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.",
@@ -708,8 +566,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "False dependencies in MOB due to partial compare on address.",
@@ -718,8 +574,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
@@ -728,8 +582,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
@@ -738,8 +590,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -749,8 +599,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -760,8 +608,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
@@ -769,8 +615,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -780,8 +624,6 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
@@ -790,8 +632,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Number of self-modifying-code machine clears detected.",
@@ -800,8 +640,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -809,8 +647,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -818,8 +654,6 @@
},
{
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"SampleAfterValue": "100003",
@@ -827,8 +661,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.",
@@ -837,8 +669,6 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
@@ -846,8 +676,6 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
@@ -855,8 +683,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).",
@@ -865,8 +691,6 @@
},
{
"BriefDescription": "Count cases of saving new LBR",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Count cases of saving new LBR records by hardware.",
@@ -875,8 +699,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "Cycles the RS is empty for the thread.",
@@ -885,8 +707,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -897,8 +717,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "Cycles which a Uop is dispatched on port 0.",
@@ -908,8 +726,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 0.",
@@ -918,8 +734,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "Cycles which a Uop is dispatched on port 1.",
@@ -929,8 +743,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 1.",
@@ -939,8 +751,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "Cycles which a Uop is dispatched on port 2.",
@@ -950,8 +760,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -959,8 +767,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "Cycles which a Uop is dispatched on port 3.",
@@ -970,8 +776,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
"PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
@@ -980,8 +784,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "Cycles which a Uop is dispatched on port 4.",
@@ -991,8 +793,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 4.",
@@ -1001,8 +801,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "Cycles which a Uop is dispatched on port 5.",
@@ -1012,8 +810,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 5.",
@@ -1022,8 +818,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
@@ -1032,8 +826,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1043,8 +835,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1054,8 +844,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1065,8 +853,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1076,8 +862,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
@@ -1087,8 +871,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1098,8 +880,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1109,8 +889,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1120,8 +898,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1131,8 +907,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1142,8 +916,6 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.",
@@ -1152,8 +924,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.",
@@ -1163,8 +933,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1175,8 +943,6 @@
},
{
"BriefDescription": "Number of flags-merge uops being allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
@@ -1185,8 +951,6 @@
},
{
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL",
"PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
@@ -1195,8 +959,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
@@ -1205,8 +967,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1217,8 +977,6 @@
},
{
"BriefDescription": "Retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@@ -1228,8 +986,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1239,8 +995,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -1249,8 +1003,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1260,8 +1012,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
index 6b0639944d78..c538557ba4c0 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
@@ -1,251 +1,201 @@
[
{
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"UMask": "0x86",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"UMask": "0x8f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"UMask": "0x46",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"UMask": "0x41",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"UMask": "0x4f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"UMask": "0x16",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"UMask": "0x18",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
"UMask": "0x11",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"UMask": "0x1f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"UMask": "0x26",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"UMask": "0x2f",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"PerPkg": "1",
- "PublicDescription": "An external snoop hits a modified line in some processor core.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"UMask": "0x84",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"PerPkg": "1",
- "PublicDescription": "An external snoop hits a non-modified line in some processor core.",
"UMask": "0x24",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"UMask": "0x44",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"PerPkg": "1",
- "PublicDescription": "An external snoop misses in some processor core.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"UMask": "0x41",
"Unit": "CBO"
}
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
index 88f1e326205f..c3252c094a9c 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
@@ -4,18 +4,15 @@
"EventCode": "0x83",
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
- "Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
- "PublicDescription": "Number of requests allocated in Coherency Tracker.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
@@ -23,69 +20,56 @@
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "Counter": "0,1",
"CounterMask": "10",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
"PerPkg": "1",
- "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "Counter": "0,1",
"CounterMask": "1",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
- "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
- "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of LLC evictions allocated.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
"PerPkg": "1",
- "PublicDescription": "Counts the number of LLC evictions allocated.",
"UMask": "0x80",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
- "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
"UMask": "0x20",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
- "Counter": "Fixed",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",
- "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Unit": "ARB"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
index a5e387bbb134..b97f15cb20fc 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Page walk for a large page completed for Demand load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5F",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
@@ -30,8 +24,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.",
@@ -40,8 +32,6 @@
},
{
"BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "Cycle PMH is busy with a walk due to demand loads.",
@@ -50,8 +40,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
@@ -60,8 +48,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
@@ -70,8 +56,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).",
@@ -80,8 +64,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"PublicDescription": "Cycles PMH is busy with this walk.",
@@ -90,8 +72,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
@@ -99,8 +79,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
@@ -109,8 +87,6 @@
},
{
"BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",
"PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
@@ -119,8 +95,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all ITLB levels that cause page walks.",
@@ -129,8 +103,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "Number of cache load STLB hits. No page walk.",
@@ -139,8 +111,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
@@ -149,8 +119,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "Cycle PMH is busy with a walk.",
@@ -159,8 +127,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "DTLB flush attempts of the thread-specific entries.",
@@ -169,8 +135,6 @@
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Count number of STLB flush attempts.",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 7e489749a0d4..de3f9dd4e6f7 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -13,7 +13,7 @@ GenuineIntel-6-(3C|45|46),v32,haswell,core
GenuineIntel-6-3F,v26,haswellx,core
GenuineIntel-6-(7D|7E|A7),v1.15,icelake,core
GenuineIntel-6-6[AC],v1.17,icelakex,core
-GenuineIntel-6-3A,v22,ivybridge,core
+GenuineIntel-6-3A,v23,ivybridge,core
GenuineIntel-6-3E,v22,ivytown,core
GenuineIntel-6-2D,v21,jaketown,core
GenuineIntel-6-(57|85),v9,knightslanding,core
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 17/32] perf vendor events intel: Refresh ivytown metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (6 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 16/32] perf vendor events intel: Refresh ivybridge " Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 18/32] perf vendor events intel: Refresh jaketown " Ian Rogers
` (14 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the ivytown metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/ivytown/cache.json | 274 ----------
.../arch/x86/ivytown/floating-point.json | 34 --
.../pmu-events/arch/x86/ivytown/frontend.json | 60 ---
.../arch/x86/ivytown/ivt-metrics.json | 133 +++--
.../pmu-events/arch/x86/ivytown/memory.json | 121 -----
.../pmu-events/arch/x86/ivytown/other.json | 8 -
.../pmu-events/arch/x86/ivytown/pipeline.json | 250 ---------
.../arch/x86/ivytown/uncore-cache.json | 388 ++------------
.../arch/x86/ivytown/uncore-interconnect.json | 505 +++++++-----------
.../arch/x86/ivytown/uncore-memory.json | 209 +-------
.../arch/x86/ivytown/uncore-other.json | 254 +--------
.../arch/x86/ivytown/uncore-power.json | 95 ----
.../arch/x86/ivytown/virtual-memory.json | 40 --
13 files changed, 346 insertions(+), 2025 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/cache.json b/tools/perf/pmu-events/arch/x86/ivytown/cache.json
index d95b98c83914..c8f7d5e66504 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts the number of lines brought into the L1 data cache.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "L1D miss outstanding duration in cycles",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -54,8 +44,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.ALL",
"SampleAfterValue": "200003",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_E",
"PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
@@ -73,8 +59,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_M",
"PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
@@ -83,8 +67,6 @@
},
{
"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.MISS",
"PublicDescription": "Not rejected writebacks that missed LLC.",
@@ -93,8 +75,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "L2 cache lines filling L2.",
@@ -103,8 +83,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "L2 cache lines in E state filling L2.",
@@ -113,8 +91,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "L2 cache lines in I state filling L2.",
@@ -123,8 +99,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "L2 cache lines in S state filling L2.",
@@ -133,8 +107,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by demand.",
@@ -143,8 +115,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by demand.",
@@ -153,8 +123,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines filling the L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DIRTY_ALL",
"PublicDescription": "Dirty L2 cache lines filling the L2.",
@@ -163,8 +131,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
@@ -173,8 +139,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
@@ -183,8 +147,6 @@
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts all L2 code requests.",
@@ -193,8 +155,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
@@ -203,8 +163,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts all L2 HW prefetcher requests.",
@@ -213,8 +171,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts all L2 store RFO requests.",
@@ -223,8 +179,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
@@ -233,8 +187,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
@@ -243,8 +195,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Demand Data Read requests that hit L2 cache.",
@@ -253,8 +203,6 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
@@ -263,8 +211,6 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
@@ -273,8 +219,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "RFO requests that hit L2 cache.",
@@ -283,8 +227,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
@@ -293,8 +235,6 @@
},
{
"BriefDescription": "RFOs that access cache lines in any state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.ALL",
"PublicDescription": "RFOs that access cache lines in any state.",
@@ -303,8 +243,6 @@
},
{
"BriefDescription": "RFOs that hit cache lines in M state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
"PublicDescription": "RFOs that hit cache lines in M state.",
@@ -313,8 +251,6 @@
},
{
"BriefDescription": "RFOs that miss cache lines",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.MISS",
"PublicDescription": "RFOs that miss cache lines.",
@@ -323,8 +259,6 @@
},
{
"BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
@@ -333,8 +267,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "Transactions accessing L2 pipe.",
@@ -343,8 +275,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "L2 cache accesses when fetching instructions.",
@@ -353,8 +283,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "Demand Data Read requests that access L2 cache.",
@@ -363,8 +291,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "L1D writebacks that access L2 cache.",
@@ -373,8 +299,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "L2 fill requests that access L2 cache.",
@@ -383,8 +307,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "L2 writebacks that access L2 cache.",
@@ -393,8 +315,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "RFO requests that access L2 cache.",
@@ -403,8 +323,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D is locked.",
@@ -413,8 +331,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
@@ -423,8 +339,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
@@ -433,8 +347,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
"PEBS": "1",
@@ -443,8 +355,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
@@ -453,8 +363,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
@@ -463,8 +371,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
@@ -473,8 +379,6 @@
},
{
"BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
"SampleAfterValue": "100007",
@@ -482,8 +386,6 @@
},
{
"BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",
"SampleAfterValue": "100007",
@@ -491,8 +393,6 @@
},
{
"BriefDescription": "Data forwarded from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD",
"SampleAfterValue": "100007",
@@ -500,8 +400,6 @@
},
{
"BriefDescription": "Remote cache HITM.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM",
"SampleAfterValue": "100007",
@@ -509,8 +407,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -519,8 +415,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
@@ -529,8 +423,6 @@
},
{
"BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PEBS": "1",
@@ -539,8 +431,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
@@ -549,8 +439,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache misses as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PEBS": "1",
@@ -559,8 +447,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
"PEBS": "1",
@@ -569,8 +455,6 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -579,8 +463,6 @@
},
{
"BriefDescription": "All retired load uops. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
@@ -589,8 +471,6 @@
},
{
"BriefDescription": "All retired store uops. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
@@ -599,8 +479,6 @@
},
{
"BriefDescription": "Retired load uops with locked access. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
@@ -609,8 +487,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
@@ -619,8 +495,6 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
@@ -629,8 +503,6 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
@@ -639,8 +511,6 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PEBS": "1",
@@ -649,8 +519,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
@@ -659,8 +527,6 @@
},
{
"BriefDescription": "Cacheable and noncacheable code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Demand code read requests sent to uncore.",
@@ -669,8 +535,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Demand data read requests sent to uncore.",
@@ -679,8 +543,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
@@ -689,8 +551,6 @@
},
{
"BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
@@ -699,8 +559,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -709,8 +567,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -720,8 +576,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -731,8 +585,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -742,8 +594,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -753,8 +603,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -763,8 +611,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -773,8 +619,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -784,8 +628,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -794,464 +636,348 @@
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all writebacks from the core to the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10008",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803c8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23ffc08000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts non-temporal stores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json
index 88891cba54ec..89c6d47cc077 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@@ -12,8 +10,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "Number of X87 FP assists due to input values.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "Number of X87 FP assists due to output values.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"PublicDescription": "Counts number of X87 uops executed.",
@@ -102,8 +82,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -120,8 +96,6 @@
},
{
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
@@ -130,8 +104,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
@@ -139,8 +111,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
@@ -148,8 +118,6 @@
},
{
"BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
@@ -158,8 +126,6 @@
},
{
"BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json
index 0a295c4e093d..4ee100024ca9 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"PublicDescription": "Number of DSB to MITE switches.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Cycles DSB to MITE switches caused delay.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"PublicDescription": "DSB Fill encountered > 3 DSB lines.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFETCH_STALL",
"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -93,8 +75,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -104,8 +84,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -115,8 +93,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -126,8 +102,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -136,8 +110,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "Counts cycles the IDQ is empty.",
@@ -146,8 +118,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -156,8 +126,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -167,8 +135,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -177,8 +143,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -188,8 +152,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -199,8 +161,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -211,8 +171,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -221,8 +179,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -231,8 +187,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -243,8 +197,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
@@ -253,8 +205,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
@@ -263,8 +213,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -273,8 +221,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -284,8 +230,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -294,8 +238,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -304,8 +246,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json
index 99a45c8d8cee..80444bc4e66e 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json
@@ -88,7 +88,7 @@
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -96,7 +96,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -120,7 +120,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+ "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -152,7 +152,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+ "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
@@ -192,7 +192,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -200,7 +200,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
+ "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -208,7 +208,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
+ "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -216,7 +216,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
+ "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -224,7 +224,7 @@
},
{
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_sq_full",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -232,7 +232,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -256,7 +256,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
- "MetricExpr": "200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
+ "MetricExpr": "200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
"MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
"MetricName": "tma_local_dram",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS",
@@ -264,7 +264,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
- "MetricExpr": "310 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
+ "MetricExpr": "310 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
"MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
"MetricName": "tma_remote_dram",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS",
@@ -272,7 +272,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
- "MetricExpr": "(200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
+ "MetricExpr": "(200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
"MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
"MetricName": "tma_remote_cache",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS",
@@ -288,7 +288,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -336,7 +336,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
+ "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -344,7 +344,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0",
"PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@@ -352,7 +352,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_1",
"PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
@@ -360,7 +360,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_2",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
@@ -368,7 +368,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
- "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m",
"ScaleUnit": "100%"
@@ -424,7 +424,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricExpr": "tma_port_4",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_store_op_utilization",
"ScaleUnit": "100%"
@@ -494,7 +494,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -567,19 +567,19 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
+ "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
@@ -646,7 +646,7 @@
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
@@ -658,7 +658,7 @@
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
"MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency"
},
@@ -670,19 +670,19 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
@@ -695,19 +695,19 @@
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
@@ -737,19 +737,19 @@
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1000000000) / duration_time",
+ "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -762,7 +762,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@@ -780,10 +780,22 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
+ {
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
+ },
+ {
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
+ },
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
"MetricExpr": "cbox_0@event\\=0x0@",
@@ -796,52 +808,59 @@
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
+ {
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
+ },
{
"BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
- },
- {
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/memory.json b/tools/perf/pmu-events/arch/x86/ivytown/memory.json
index 99b71e43acad..138d1aa0b32d 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Loads with latency value being above 128",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
@@ -19,13 +15,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 128.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 16",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
@@ -33,13 +26,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 16.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
@@ -47,13 +37,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 256.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 32",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
@@ -61,13 +48,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 32.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
@@ -75,13 +59,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 4.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
@@ -89,13 +70,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 512.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 64",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
@@ -103,13 +81,10 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 64.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
@@ -117,25 +92,18 @@
"PEBS": "2",
"PublicDescription": "Loads with latency value being above 8.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
"PEBS": "2",
- "PRECISE_STORE": "1",
"SampleAfterValue": "2000003",
- "TakenAlone": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
@@ -144,8 +112,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
@@ -154,349 +120,262 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc00244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f800244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that hits the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc203f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6004003f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc003f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f8203f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f820004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67fc00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f820001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc20002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67fc00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f820010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/other.json b/tools/perf/pmu-events/arch/x86/ivytown/other.json
index 2d62521791d8..e80e99d064ba 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/other.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@@ -23,8 +19,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
index d89d3f8db190..d1e64e0d683e 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Divide operations executed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -13,8 +11,6 @@
},
{
"BriefDescription": "Cycles when divider is busy executing divide operations",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.",
@@ -23,8 +19,6 @@
},
{
"BriefDescription": "Speculative and retired branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"PublicDescription": "Speculative and retired macro-conditional branches.",
@@ -43,8 +35,6 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
@@ -53,8 +43,6 @@
},
{
"BriefDescription": "Speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"PublicDescription": "Speculative and retired direct near calls.",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Speculative and retired indirect branches excluding calls and returns.",
@@ -73,8 +59,6 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Not taken macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "Not taken macro-conditional branches.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "Taken speculative and retired macro-conditional branches.",
@@ -102,8 +82,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
@@ -112,8 +90,6 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"PublicDescription": "Taken speculative and retired direct near calls.",
@@ -122,8 +98,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
@@ -132,8 +106,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "Taken speculative and retired indirect calls.",
@@ -142,8 +114,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.",
@@ -152,8 +122,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "Branch instructions at retirement.",
@@ -161,8 +129,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -171,8 +137,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -181,8 +145,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PublicDescription": "Number of far branches retired.",
@@ -191,8 +153,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -201,8 +161,6 @@
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
@@ -211,8 +169,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -221,8 +177,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -231,8 +185,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "Counts the number of not taken branch instructions retired.",
@@ -241,8 +193,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -251,8 +201,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"PublicDescription": "Speculative and retired mispredicted macro conditional branches.",
@@ -261,8 +209,6 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Mispredicted indirect branches excluding calls and returns.",
@@ -271,8 +217,6 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
@@ -281,8 +225,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.",
@@ -291,8 +233,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -301,8 +241,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "Taken speculative and retired mispredicted indirect calls.",
@@ -311,8 +249,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
@@ -321,8 +257,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Mispredicted branch instructions at retirement.",
@@ -330,8 +264,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -340,8 +272,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -350,8 +280,6 @@
},
{
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -360,8 +288,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -369,8 +295,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
@@ -380,8 +304,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -389,8 +311,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -398,16 +318,12 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
@@ -417,8 +333,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -426,8 +340,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
"UMask": "0x2"
@@ -435,8 +347,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"SampleAfterValue": "2000003",
@@ -444,8 +354,6 @@
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
@@ -454,8 +362,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
@@ -463,8 +369,6 @@
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -473,8 +377,6 @@
},
{
"BriefDescription": "Cycles with pending L1 cache miss loads.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -484,8 +386,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss load* is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -494,8 +394,6 @@
},
{
"BriefDescription": "Cycles with pending L2 cache miss loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -505,8 +403,6 @@
},
{
"BriefDescription": "Cycles with pending memory loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -516,8 +412,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -526,8 +420,6 @@
},
{
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -537,8 +429,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -547,8 +437,6 @@
},
{
"BriefDescription": "Execution stalls due to L1 data cache misses",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -558,8 +446,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -568,8 +454,6 @@
},
{
"BriefDescription": "Execution stalls due to L2 cache misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -579,8 +463,6 @@
},
{
"BriefDescription": "Execution stalls due to memory subsystem.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -589,8 +471,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -599,8 +479,6 @@
},
{
"BriefDescription": "Total execution stalls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -609,8 +487,6 @@
},
{
"BriefDescription": "Stall cycles because IQ is full",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"PublicDescription": "Stall cycles due to IQ is full.",
@@ -619,8 +495,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000003",
@@ -628,16 +502,12 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PublicDescription": "Number of instructions at retirement.",
@@ -645,8 +515,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "2",
@@ -656,8 +524,6 @@
},
{
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -667,8 +533,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -677,8 +541,6 @@
},
{
"BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x0D",
@@ -688,8 +550,6 @@
},
{
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -698,8 +558,6 @@
},
{
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.",
@@ -708,8 +566,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "False dependencies in MOB due to partial compare on address.",
@@ -718,8 +574,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
@@ -728,8 +582,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
@@ -738,8 +590,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -749,8 +599,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -760,8 +608,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
@@ -769,8 +615,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -780,8 +624,6 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
@@ -790,8 +632,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Number of self-modifying-code machine clears detected.",
@@ -800,8 +640,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -809,8 +647,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -818,8 +654,6 @@
},
{
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"SampleAfterValue": "100003",
@@ -827,8 +661,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.",
@@ -837,8 +669,6 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
@@ -846,8 +676,6 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
@@ -855,8 +683,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).",
@@ -865,8 +691,6 @@
},
{
"BriefDescription": "Count cases of saving new LBR",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Count cases of saving new LBR records by hardware.",
@@ -875,8 +699,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "Cycles the RS is empty for the thread.",
@@ -885,8 +707,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -897,8 +717,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "Cycles which a Uop is dispatched on port 0.",
@@ -908,8 +726,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 0.",
@@ -918,8 +734,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "Cycles which a Uop is dispatched on port 1.",
@@ -929,8 +743,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 1.",
@@ -939,8 +751,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "Cycles which a Uop is dispatched on port 2.",
@@ -950,8 +760,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -959,8 +767,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "Cycles which a Uop is dispatched on port 3.",
@@ -970,8 +776,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
"PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
@@ -980,8 +784,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "Cycles which a Uop is dispatched on port 4.",
@@ -991,8 +793,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 4.",
@@ -1001,8 +801,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "Cycles which a Uop is dispatched on port 5.",
@@ -1012,8 +810,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 5.",
@@ -1022,8 +818,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
@@ -1032,8 +826,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1043,8 +835,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1054,8 +844,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1065,8 +853,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1076,8 +862,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
@@ -1087,8 +871,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1098,8 +880,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1109,8 +889,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1120,8 +898,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1131,8 +907,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1142,8 +916,6 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.",
@@ -1152,8 +924,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.",
@@ -1163,8 +933,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1175,8 +943,6 @@
},
{
"BriefDescription": "Number of flags-merge uops being allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
@@ -1185,8 +951,6 @@
},
{
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL",
"PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
@@ -1195,8 +959,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
@@ -1205,8 +967,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1217,8 +977,6 @@
},
{
"BriefDescription": "Retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@@ -1228,8 +986,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1239,8 +995,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -1249,8 +1003,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1260,8 +1012,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json
index c118ff54c30e..521175881173 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json
@@ -1,14 +1,12 @@
[
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventName": "UNC_C_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CBO"
},
{
"BriefDescription": "Counter 0 Occupancy",
- "Counter": "1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_C_COUNTER0_OCCUPANCY",
"PerPkg": "1",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Cache Lookups; Any Request",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.ANY",
"PerPkg": "1",
@@ -27,7 +24,6 @@
},
{
"BriefDescription": "Cache Lookups; Data Read Request",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
@@ -37,7 +33,6 @@
},
{
"BriefDescription": "Cache Lookups; Lookups that Match NID",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.NID",
"PerPkg": "1",
@@ -47,7 +42,6 @@
},
{
"BriefDescription": "Cache Lookups; External Snoop Request",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
@@ -57,7 +51,6 @@
},
{
"BriefDescription": "Cache Lookups; Write Requests",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
@@ -67,7 +60,6 @@
},
{
"BriefDescription": "Lines Victimized; Lines in E state",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
@@ -77,7 +69,6 @@
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.MISS",
"PerPkg": "1",
@@ -87,7 +78,6 @@
},
{
"BriefDescription": "Lines Victimized; Lines in M state",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
@@ -97,7 +87,6 @@
},
{
"BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.NID",
"PerPkg": "1",
@@ -107,7 +96,6 @@
},
{
"BriefDescription": "Lines Victimized; Lines in S State",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
@@ -117,7 +105,6 @@
},
{
"BriefDescription": "Cbo Misc; RFO HitS",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RFO_HIT_S",
"PerPkg": "1",
@@ -127,7 +114,6 @@
},
{
"BriefDescription": "Cbo Misc; Silent Snoop Eviction",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
@@ -137,7 +123,6 @@
},
{
"BriefDescription": "Cbo Misc",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.STARTED",
"PerPkg": "1",
@@ -147,7 +132,6 @@
},
{
"BriefDescription": "Cbo Misc; Write Combining Aliasing",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.WC_ALIASING",
"PerPkg": "1",
@@ -157,7 +141,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Age 0",
- "Counter": "0,1",
"EventCode": "0x3c",
"EventName": "UNC_C_QLRU.AGE0",
"PerPkg": "1",
@@ -167,7 +150,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Age 1",
- "Counter": "0,1",
"EventCode": "0x3c",
"EventName": "UNC_C_QLRU.AGE1",
"PerPkg": "1",
@@ -177,7 +159,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Age 2",
- "Counter": "0,1",
"EventCode": "0x3c",
"EventName": "UNC_C_QLRU.AGE2",
"PerPkg": "1",
@@ -187,7 +168,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Age 3",
- "Counter": "0,1",
"EventCode": "0x3c",
"EventName": "UNC_C_QLRU.AGE3",
"PerPkg": "1",
@@ -197,7 +177,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Bits Decremented",
- "Counter": "0,1",
"EventCode": "0x3c",
"EventName": "UNC_C_QLRU.LRU_DECREMENT",
"PerPkg": "1",
@@ -207,7 +186,6 @@
},
{
"BriefDescription": "LRU Queue; Non-0 Aged Victim",
- "Counter": "0,1",
"EventCode": "0x3c",
"EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
"PerPkg": "1",
@@ -217,17 +195,15 @@
},
{
"BriefDescription": "AD Ring In Use; Counterclockwise",
- "Counter": "2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Clockwise",
- "Counter": "2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.CW",
"PerPkg": "1",
@@ -237,17 +213,15 @@
},
{
"BriefDescription": "AD Ring In Use; Down",
- "Counter": "2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.DOWN",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Even on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.DOWN_VR0_EVEN",
"PerPkg": "1",
@@ -257,7 +231,6 @@
},
{
"BriefDescription": "AD Ring In Use; Down and Odd on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.DOWN_VR0_ODD",
"PerPkg": "1",
@@ -267,7 +240,6 @@
},
{
"BriefDescription": "AD Ring In Use; Down and Even on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.DOWN_VR1_EVEN",
"PerPkg": "1",
@@ -277,7 +249,6 @@
},
{
"BriefDescription": "AD Ring In Use; Down and Odd on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.DOWN_VR1_ODD",
"PerPkg": "1",
@@ -287,7 +258,6 @@
},
{
"BriefDescription": "AD Ring In Use; Up",
- "Counter": "2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.UP",
"PerPkg": "1",
@@ -297,7 +267,6 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Even on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.UP_VR0_EVEN",
"PerPkg": "1",
@@ -307,7 +276,6 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Odd on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.UP_VR0_ODD",
"PerPkg": "1",
@@ -317,7 +285,6 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Even on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.UP_VR1_EVEN",
"PerPkg": "1",
@@ -327,7 +294,6 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Odd on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.UP_VR1_ODD",
"PerPkg": "1",
@@ -337,17 +303,15 @@
},
{
"BriefDescription": "AK Ring In Use; Counterclockwise",
- "Counter": "2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Clockwise",
- "Counter": "2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.CW",
"PerPkg": "1",
@@ -357,17 +321,15 @@
},
{
"BriefDescription": "AK Ring In Use; Down",
- "Counter": "2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Even on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.DOWN_VR0_EVEN",
"PerPkg": "1",
@@ -377,7 +339,6 @@
},
{
"BriefDescription": "AK Ring In Use; Down and Odd on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.DOWN_VR0_ODD",
"PerPkg": "1",
@@ -387,7 +348,6 @@
},
{
"BriefDescription": "AK Ring In Use; Down and Even on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.DOWN_VR1_EVEN",
"PerPkg": "1",
@@ -397,7 +357,6 @@
},
{
"BriefDescription": "AK Ring In Use; Down and Odd on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.DOWN_VR1_ODD",
"PerPkg": "1",
@@ -407,7 +366,6 @@
},
{
"BriefDescription": "AK Ring In Use; Up",
- "Counter": "2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.UP",
"PerPkg": "1",
@@ -417,7 +375,6 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Even on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.UP_VR0_EVEN",
"PerPkg": "1",
@@ -427,7 +384,6 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Odd on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.UP_VR0_ODD",
"PerPkg": "1",
@@ -437,7 +393,6 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Even on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.UP_VR1_EVEN",
"PerPkg": "1",
@@ -447,7 +402,6 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Odd on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.UP_VR1_ODD",
"PerPkg": "1",
@@ -457,17 +411,15 @@
},
{
"BriefDescription": "BL Ring in Use; Counterclockwise",
- "Counter": "2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Clockwise",
- "Counter": "2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.CW",
"PerPkg": "1",
@@ -477,17 +429,15 @@
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Even on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.DOWN_VR0_EVEN",
"PerPkg": "1",
@@ -497,7 +447,6 @@
},
{
"BriefDescription": "BL Ring in Use; Down and Odd on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.DOWN_VR0_ODD",
"PerPkg": "1",
@@ -507,7 +456,6 @@
},
{
"BriefDescription": "BL Ring in Use; Down and Even on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.DOWN_VR1_EVEN",
"PerPkg": "1",
@@ -517,7 +465,6 @@
},
{
"BriefDescription": "BL Ring in Use; Down and Odd on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.DOWN_VR1_ODD",
"PerPkg": "1",
@@ -527,7 +474,6 @@
},
{
"BriefDescription": "BL Ring in Use; Up",
- "Counter": "2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.UP",
"PerPkg": "1",
@@ -537,7 +483,6 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Even on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.UP_VR0_EVEN",
"PerPkg": "1",
@@ -547,7 +492,6 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Odd on Vring 0",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.UP_VR0_ODD",
"PerPkg": "1",
@@ -557,7 +501,6 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Even on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.UP_VR1_EVEN",
"PerPkg": "1",
@@ -567,7 +510,6 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Odd on VRing 1",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.UP_VR1_ODD",
"PerPkg": "1",
@@ -577,7 +519,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AD_IRQ",
"PerPkg": "1",
@@ -586,7 +527,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AK",
"PerPkg": "1",
@@ -595,7 +535,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.: Acknowledgements to core",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AK_CORE",
"PerPkg": "1",
@@ -604,7 +543,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.BL",
"PerPkg": "1",
@@ -613,7 +551,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.: Data Responses to core",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.BL_CORE",
"PerPkg": "1",
@@ -622,7 +559,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.IV",
"PerPkg": "1",
@@ -631,7 +567,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.: Snoops of processor's cache.",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.IV_CORE",
"PerPkg": "1",
@@ -640,27 +575,24 @@
},
{
"BriefDescription": "IV Ring in Use; Any",
- "Counter": "2,3",
"EventCode": "0x1e",
"EventName": "UNC_C_RING_IV_USED.ANY",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters any polarity",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "IV Ring in Use; Down",
- "Counter": "2,3",
"EventCode": "0x1e",
"EventName": "UNC_C_RING_IV_USED.DOWN",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Down polarity",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "CBO"
},
{
"BriefDescription": "IV Ring in Use; Up",
- "Counter": "2,3",
"EventCode": "0x1e",
"EventName": "UNC_C_RING_IV_USED.UP",
"PerPkg": "1",
@@ -668,9 +600,35 @@
"UMask": "0x33",
"Unit": "CBO"
},
+ {
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.AD_IPQ",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CBO"
+ },
+ {
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.AD_IRQ",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.IV",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CBO"
+ },
+ {
+ "EventCode": "0x7",
+ "EventName": "UNC_C_RING_SRC_THRTL",
+ "PerPkg": "1",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
"PerPkg": "1",
@@ -680,7 +638,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
"PerPkg": "1",
@@ -690,7 +647,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
"PerPkg": "1",
@@ -700,7 +656,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
"PerPkg": "1",
@@ -710,7 +665,6 @@
},
{
"BriefDescription": "Ingress Allocations; IPQ",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IPQ",
"PerPkg": "1",
@@ -720,7 +674,6 @@
},
{
"BriefDescription": "Ingress Allocations; IRQ",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ",
"PerPkg": "1",
@@ -730,7 +683,6 @@
},
{
"BriefDescription": "Ingress Allocations; IRQ Rejected",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
"PerPkg": "1",
@@ -740,7 +692,6 @@
},
{
"BriefDescription": "Ingress Allocations: IRQ Rejected",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED",
"PerPkg": "1",
@@ -750,7 +701,6 @@
},
{
"BriefDescription": "Ingress Allocations; VFIFO",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.VFIFO",
"PerPkg": "1",
@@ -760,7 +710,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IPQ",
"PerPkg": "1",
@@ -770,7 +719,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IRQ",
"PerPkg": "1",
@@ -780,7 +728,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
"PerPkg": "1",
@@ -790,7 +737,6 @@
},
{
"BriefDescription": "Probe Queue Retries; Address Conflict",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
@@ -800,7 +746,6 @@
},
{
"BriefDescription": "Probe Queue Retries; Any Reject",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
"PerPkg": "1",
@@ -810,7 +755,6 @@
},
{
"BriefDescription": "Probe Queue Retries; No Egress Credits",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
"PerPkg": "1",
@@ -820,7 +764,6 @@
},
{
"BriefDescription": "Probe Queue Retries; No QPI Credits",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -830,7 +773,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
@@ -840,7 +782,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; Any Reject",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
"PerPkg": "1",
@@ -850,7 +791,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
"PerPkg": "1",
@@ -860,7 +800,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
@@ -870,7 +809,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -880,7 +818,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
"PerPkg": "1",
@@ -890,7 +827,6 @@
},
{
"BriefDescription": "ISMQ Retries; Any Reject",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
"PerPkg": "1",
@@ -900,7 +836,6 @@
},
{
"BriefDescription": "ISMQ Retries; No Egress Credits",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
"PerPkg": "1",
@@ -910,7 +845,6 @@
},
{
"BriefDescription": "ISMQ Retries; No IIO Credits",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
@@ -920,7 +854,6 @@
},
{
"BriefDescription": "ISMQ Retries; No QPI Credits",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -930,7 +863,6 @@
},
{
"BriefDescription": "ISMQ Retries; No RTIDs",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
"PerPkg": "1",
@@ -940,7 +872,6 @@
},
{
"BriefDescription": "ISMQ Retries; No WB Credits",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
"PerPkg": "1",
@@ -995,7 +926,6 @@
},
{
"BriefDescription": "TOR Inserts; All",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.ALL",
"PerPkg": "1",
@@ -1005,7 +935,6 @@
},
{
"BriefDescription": "TOR Inserts; Evictions",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.EVICTION",
"PerPkg": "1",
@@ -1015,7 +944,6 @@
},
{
"BriefDescription": "TOR Inserts; Local Memory",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.LOCAL",
"PerPkg": "1",
@@ -1025,7 +953,6 @@
},
{
"BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
"PerPkg": "1",
@@ -1035,17 +962,15 @@
},
{
"BriefDescription": "TOR Inserts; Misses to Local Memory",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.",
- "UMask": "0x2A",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
"PerPkg": "1",
@@ -1055,7 +980,6 @@
},
{
"BriefDescription": "TOR Inserts; Miss Opcode Match",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
"PerPkg": "1",
@@ -1065,17 +989,15 @@
},
{
"BriefDescription": "TOR Inserts; Misses to Remote Memory",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.",
- "UMask": "0x8A",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
"PerPkg": "1",
@@ -1085,7 +1007,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_ALL",
"PerPkg": "1",
@@ -1095,7 +1016,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Evictions",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
"PerPkg": "1",
@@ -1105,17 +1025,15 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Miss All",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
- "UMask": "0x4A",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
"PerPkg": "1",
@@ -1125,7 +1043,6 @@
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
"PerPkg": "1",
@@ -1135,7 +1052,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Writebacks",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_WB",
"PerPkg": "1",
@@ -1145,7 +1061,6 @@
},
{
"BriefDescription": "TOR Inserts; Opcode Match",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.OPCODE",
"PerPkg": "1",
@@ -1155,7 +1070,6 @@
},
{
"BriefDescription": "TOR Inserts; Remote Memory",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.REMOTE",
"PerPkg": "1",
@@ -1165,7 +1079,6 @@
},
{
"BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
"PerPkg": "1",
@@ -1175,7 +1088,6 @@
},
{
"BriefDescription": "TOR Inserts; Writebacks",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.WB",
"PerPkg": "1",
@@ -1225,7 +1137,7 @@
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "CBO"
},
{
@@ -1234,7 +1146,7 @@
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
- "UMask": "0x2A",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
@@ -1261,7 +1173,7 @@
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
- "UMask": "0x8A",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
@@ -1297,7 +1209,7 @@
"EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
- "UMask": "0x4A",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
@@ -1365,7 +1277,6 @@
},
{
"BriefDescription": "Onto AD Ring",
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AD",
"PerPkg": "1",
@@ -1374,7 +1285,6 @@
},
{
"BriefDescription": "Onto AK Ring",
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AK",
"PerPkg": "1",
@@ -1383,7 +1293,6 @@
},
{
"BriefDescription": "Onto BL Ring",
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.BL",
"PerPkg": "1",
@@ -1392,7 +1301,6 @@
},
{
"BriefDescription": "Egress Allocations; AD - Cachebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
"PerPkg": "1",
@@ -1402,7 +1310,6 @@
},
{
"BriefDescription": "Egress Allocations; AD - Corebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CORE",
"PerPkg": "1",
@@ -1412,7 +1319,6 @@
},
{
"BriefDescription": "Egress Allocations; AK - Cachebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
"PerPkg": "1",
@@ -1422,7 +1328,6 @@
},
{
"BriefDescription": "Egress Allocations; AK - Corebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CORE",
"PerPkg": "1",
@@ -1432,7 +1337,6 @@
},
{
"BriefDescription": "Egress Allocations; BL - Cacheno",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
"PerPkg": "1",
@@ -1442,7 +1346,6 @@
},
{
"BriefDescription": "Egress Allocations; BL - Corebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CORE",
"PerPkg": "1",
@@ -1452,7 +1355,6 @@
},
{
"BriefDescription": "Egress Allocations; IV - Cachebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
"PerPkg": "1",
@@ -1462,7 +1364,6 @@
},
{
"BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AD_CORE",
"PerPkg": "1",
@@ -1472,7 +1373,6 @@
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AK_BOTH",
"PerPkg": "1",
@@ -1482,7 +1382,6 @@
},
{
"BriefDescription": "Injection Starvation; Onto IV Ring",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.IV",
"PerPkg": "1",
@@ -1492,7 +1391,6 @@
},
{
"BriefDescription": "BT Bypass",
- "Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_H_BT_BYPASS",
"PerPkg": "1",
@@ -1501,7 +1399,6 @@
},
{
"BriefDescription": "BT Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_H_BT_CYCLES_NE",
"PerPkg": "1",
@@ -1510,7 +1407,6 @@
},
{
"BriefDescription": "BT Cycles Not Empty: Local",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_H_BT_CYCLES_NE.LOCAL",
"PerPkg": "1",
@@ -1520,7 +1416,6 @@
},
{
"BriefDescription": "BT Cycles Not Empty: Remote",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_H_BT_CYCLES_NE.REMOTE",
"PerPkg": "1",
@@ -1530,7 +1425,6 @@
},
{
"BriefDescription": "BT Occupancy; Local",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_H_BT_OCCUPANCY.LOCAL",
"PerPkg": "1",
@@ -1540,7 +1434,6 @@
},
{
"BriefDescription": "BT Occupancy; Reads Local",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_H_BT_OCCUPANCY.READS_LOCAL",
"PerPkg": "1",
@@ -1550,7 +1443,6 @@
},
{
"BriefDescription": "BT Occupancy; Reads Remote",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_H_BT_OCCUPANCY.READS_REMOTE",
"PerPkg": "1",
@@ -1560,7 +1452,6 @@
},
{
"BriefDescription": "BT Occupancy; Remote",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_H_BT_OCCUPANCY.REMOTE",
"PerPkg": "1",
@@ -1570,7 +1461,6 @@
},
{
"BriefDescription": "BT Occupancy; Writes Local",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_H_BT_OCCUPANCY.WRITES_LOCAL",
"PerPkg": "1",
@@ -1580,7 +1470,6 @@
},
{
"BriefDescription": "BT Occupancy; Writes Remote",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_H_BT_OCCUPANCY.WRITES_REMOTE",
"PerPkg": "1",
@@ -1590,7 +1479,6 @@
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
"PerPkg": "1",
@@ -1600,7 +1488,6 @@
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
"PerPkg": "1",
@@ -1610,7 +1497,6 @@
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
"PerPkg": "1",
@@ -1620,7 +1506,6 @@
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
"PerPkg": "1",
@@ -1630,7 +1515,6 @@
},
{
"BriefDescription": "HA to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
"PerPkg": "1",
@@ -1640,7 +1524,6 @@
},
{
"BriefDescription": "HA to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.TAKEN",
"PerPkg": "1",
@@ -1650,7 +1533,6 @@
},
{
"BriefDescription": "uclks",
- "Counter": "0,1,2,3",
"EventName": "UNC_H_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
@@ -1658,7 +1540,6 @@
},
{
"BriefDescription": "Conflict Checks; Acknowledge Conflicts",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_H_CONFLICT_CYCLES.ACKCNFLTS",
"PerPkg": "1",
@@ -1668,7 +1549,6 @@
},
{
"BriefDescription": "Conflict Checks; Cmp Fwds",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_H_CONFLICT_CYCLES.CMP_FWDS",
"PerPkg": "1",
@@ -1678,7 +1558,6 @@
},
{
"BriefDescription": "Conflict Checks; Conflict Detected",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT",
"PerPkg": "1",
@@ -1688,7 +1567,6 @@
},
{
"BriefDescription": "Conflict Checks; Last in conflict chain",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_H_CONFLICT_CYCLES.LAST",
"PerPkg": "1",
@@ -1698,7 +1576,6 @@
},
{
"BriefDescription": "Direct2Core Messages Sent",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_H_DIRECT2CORE_COUNT",
"PerPkg": "1",
@@ -1707,7 +1584,6 @@
},
{
"BriefDescription": "Cycles when Direct2Core was Disabled",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
"PerPkg": "1",
@@ -1716,7 +1592,6 @@
},
{
"BriefDescription": "Number of Reads that had Direct2Core Overridden",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
@@ -1725,7 +1600,6 @@
},
{
"BriefDescription": "Directory Lat Opt Return",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_H_DIRECTORY_LAT_OPT",
"PerPkg": "1",
@@ -1734,7 +1608,6 @@
},
{
"BriefDescription": "Directory Lookups: Any state",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.ANY",
"PerPkg": "1",
@@ -1744,7 +1617,6 @@
},
{
"BriefDescription": "Directory Lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
"PerPkg": "1",
@@ -1754,7 +1626,6 @@
},
{
"BriefDescription": "Directory Lookups: Snoop A",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_A",
"PerPkg": "1",
@@ -1764,7 +1635,6 @@
},
{
"BriefDescription": "Directory Lookups: Snoop S",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_S",
"PerPkg": "1",
@@ -1774,7 +1644,6 @@
},
{
"BriefDescription": "Directory Lookups; Snoop Needed",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
"PerPkg": "1",
@@ -1784,7 +1653,6 @@
},
{
"BriefDescription": "Directory Lookups: A State",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_A",
"PerPkg": "1",
@@ -1794,7 +1662,6 @@
},
{
"BriefDescription": "Directory Lookups: I State",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_I",
"PerPkg": "1",
@@ -1804,7 +1671,6 @@
},
{
"BriefDescription": "Directory Lookups: S State",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_S",
"PerPkg": "1",
@@ -1814,7 +1680,6 @@
},
{
"BriefDescription": "Directory Updates: A2I",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.A2I",
"PerPkg": "1",
@@ -1824,7 +1689,6 @@
},
{
"BriefDescription": "Directory Updates: A2S",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.A2S",
"PerPkg": "1",
@@ -1834,7 +1698,6 @@
},
{
"BriefDescription": "Directory Updates; Any Directory Update",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
@@ -1844,7 +1707,6 @@
},
{
"BriefDescription": "Directory Updates; Directory Clear",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
"PerPkg": "1",
@@ -1854,7 +1716,6 @@
},
{
"BriefDescription": "Directory Updates: I2A",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.I2A",
"PerPkg": "1",
@@ -1864,7 +1725,6 @@
},
{
"BriefDescription": "Directory Updates: I2S",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.I2S",
"PerPkg": "1",
@@ -1874,7 +1734,6 @@
},
{
"BriefDescription": "Directory Updates: S2A",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.S2A",
"PerPkg": "1",
@@ -1884,7 +1743,6 @@
},
{
"BriefDescription": "Directory Updates: S2I",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.S2I",
"PerPkg": "1",
@@ -1894,7 +1752,6 @@
},
{
"BriefDescription": "Directory Updates; Directory Set",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.SET",
"PerPkg": "1",
@@ -1904,7 +1761,6 @@
},
{
"BriefDescription": "AD QPI Link 2 Credit Accumulator",
- "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_H_IGR_AD_QPI2_ACCUMULATOR",
"PerPkg": "1",
@@ -1913,7 +1769,6 @@
},
{
"BriefDescription": "BL QPI Link 2 Credit Accumulator",
- "Counter": "0,1,2,3",
"EventCode": "0x5a",
"EventName": "UNC_H_IGR_BL_QPI2_ACCUMULATOR",
"PerPkg": "1",
@@ -1922,7 +1777,6 @@
},
{
"BriefDescription": "AD QPI Link 2 Credit Accumulator",
- "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_H_IGR_CREDITS_AD_QPI2",
"PerPkg": "1",
@@ -1931,7 +1785,6 @@
},
{
"BriefDescription": "BL QPI Link 2 Credit Accumulator",
- "Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_H_IGR_CREDITS_BL_QPI2",
"PerPkg": "1",
@@ -1940,7 +1793,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
"PerPkg": "1",
@@ -1950,7 +1802,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
"PerPkg": "1",
@@ -1960,7 +1811,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
"PerPkg": "1",
@@ -1970,7 +1820,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
"PerPkg": "1",
@@ -1980,7 +1829,6 @@
},
{
"BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_H_IMC_READS.NORMAL",
"PerPkg": "1",
@@ -1990,7 +1838,6 @@
},
{
"BriefDescription": "Retry Events",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_H_IMC_RETRY",
"PerPkg": "1",
@@ -1998,17 +1845,15 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.FULL",
"PerPkg": "1",
@@ -2018,7 +1863,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
@@ -2028,7 +1872,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.PARTIAL",
"PerPkg": "1",
@@ -2038,7 +1881,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
@@ -2048,7 +1890,6 @@
},
{
"BriefDescription": "IODC Conflicts; Any Conflict",
- "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_H_IODC_CONFLICTS.ANY",
"PerPkg": "1",
@@ -2057,7 +1898,6 @@
},
{
"BriefDescription": "IODC Conflicts; Last Conflict",
- "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_H_IODC_CONFLICTS.LAST",
"PerPkg": "1",
@@ -2066,7 +1906,6 @@
},
{
"BriefDescription": "IODC Conflicts: Remote InvItoE - Same RTID",
- "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_H_IODC_CONFLICTS.REMOTE_INVI2E_SAME_RTID",
"PerPkg": "1",
@@ -2075,7 +1914,6 @@
},
{
"BriefDescription": "IODC Conflicts: Remote (Other) - Same Addr",
- "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_H_IODC_CONFLICTS.REMOTE_OTHER_SAME_ADDR",
"PerPkg": "1",
@@ -2084,7 +1922,6 @@
},
{
"BriefDescription": "IODC Inserts",
- "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_H_IODC_INSERTS",
"PerPkg": "1",
@@ -2093,7 +1930,6 @@
},
{
"BriefDescription": "Num IODC 0 Length Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_H_IODC_OLEN_WBMTOI",
"PerPkg": "1",
@@ -2102,7 +1938,6 @@
},
{
"BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.INVITOE_LOCAL",
"PerPkg": "1",
@@ -2112,7 +1947,6 @@
},
{
"BriefDescription": "OSB Snoop Broadcast; Local Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.READS_LOCAL",
"PerPkg": "1",
@@ -2122,7 +1956,6 @@
},
{
"BriefDescription": "OSB Snoop Broadcast; Remote",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.REMOTE",
"PerPkg": "1",
@@ -2132,7 +1965,6 @@
},
{
"BriefDescription": "OSB Early Data Return; All",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.ALL",
"PerPkg": "1",
@@ -2142,7 +1974,6 @@
},
{
"BriefDescription": "OSB Early Data Return; Reads to Local I",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
"PerPkg": "1",
@@ -2152,7 +1983,6 @@
},
{
"BriefDescription": "OSB Early Data Return; Reads to Local S",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
"PerPkg": "1",
@@ -2162,7 +1992,6 @@
},
{
"BriefDescription": "OSB Early Data Return; Reads to Remote I",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
"PerPkg": "1",
@@ -2172,7 +2001,6 @@
},
{
"BriefDescription": "OSB Early Data Return; Reads to Remote S",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
"PerPkg": "1",
@@ -2182,7 +2010,6 @@
},
{
"BriefDescription": "Read and Write Requests; Local InvItoEs",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
@@ -2192,7 +2019,6 @@
},
{
"BriefDescription": "Read and Write Requests; Remote InvItoEs",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
@@ -2202,7 +2028,6 @@
},
{
"BriefDescription": "Read and Write Requests; Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
@@ -2212,7 +2037,6 @@
},
{
"BriefDescription": "Read and Write Requests; Local Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_LOCAL",
"PerPkg": "1",
@@ -2222,7 +2046,6 @@
},
{
"BriefDescription": "Read and Write Requests; Remote Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_REMOTE",
"PerPkg": "1",
@@ -2232,17 +2055,15 @@
},
{
"BriefDescription": "Read and Write Requests; Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES",
"PerPkg": "1",
"PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "Read and Write Requests; Local Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
@@ -2252,7 +2073,6 @@
},
{
"BriefDescription": "Read and Write Requests; Remote Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
@@ -2262,17 +2082,15 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "HA"
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CCW_VR0_EVEN",
"PerPkg": "1",
@@ -2282,7 +2100,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CCW_VR0_ODD",
"PerPkg": "1",
@@ -2292,7 +2109,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CCW_VR1_EVEN",
"PerPkg": "1",
@@ -2302,7 +2118,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CCW_VR1_ODD",
"PerPkg": "1",
@@ -2312,7 +2127,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CW",
"PerPkg": "1",
@@ -2322,7 +2136,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CW_VR0_EVEN",
"PerPkg": "1",
@@ -2332,7 +2145,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CW_VR0_ODD",
"PerPkg": "1",
@@ -2342,7 +2154,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CW_VR1_EVEN",
"PerPkg": "1",
@@ -2352,7 +2163,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CW_VR1_ODD",
"PerPkg": "1",
@@ -2362,17 +2172,15 @@
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CCW_VR0_EVEN",
"PerPkg": "1",
@@ -2382,7 +2190,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CCW_VR0_ODD",
"PerPkg": "1",
@@ -2392,7 +2199,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CCW_VR1_EVEN",
"PerPkg": "1",
@@ -2402,7 +2208,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CCW_VR1_ODD",
"PerPkg": "1",
@@ -2412,7 +2217,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CW",
"PerPkg": "1",
@@ -2422,7 +2226,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CW_VR0_EVEN",
"PerPkg": "1",
@@ -2432,7 +2235,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CW_VR0_ODD",
"PerPkg": "1",
@@ -2442,7 +2244,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CW_VR1_EVEN",
"PerPkg": "1",
@@ -2452,7 +2253,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CW_VR1_ODD",
"PerPkg": "1",
@@ -2462,17 +2262,15 @@
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_VR0_EVEN",
"PerPkg": "1",
@@ -2482,7 +2280,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_VR0_ODD",
"PerPkg": "1",
@@ -2492,7 +2289,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_VR1_EVEN",
"PerPkg": "1",
@@ -2502,7 +2298,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_VR1_ODD",
"PerPkg": "1",
@@ -2512,7 +2307,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW",
"PerPkg": "1",
@@ -2522,7 +2316,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_VR0_EVEN",
"PerPkg": "1",
@@ -2532,7 +2325,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_VR0_ODD",
"PerPkg": "1",
@@ -2542,7 +2334,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_VR1_EVEN",
"PerPkg": "1",
@@ -2552,7 +2343,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_VR1_ODD",
"PerPkg": "1",
@@ -2562,7 +2352,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
@@ -2572,7 +2361,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
@@ -2582,7 +2370,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
@@ -2592,7 +2379,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
@@ -2602,7 +2388,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
@@ -2612,7 +2397,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
@@ -2622,7 +2406,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
@@ -2632,7 +2415,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
@@ -2642,7 +2424,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
"PerPkg": "1",
@@ -2652,7 +2433,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPI",
"PerPkg": "1",
@@ -2662,7 +2442,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RspIFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
"PerPkg": "1",
@@ -2672,7 +2451,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RspS",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPS",
"PerPkg": "1",
@@ -2682,7 +2460,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RspSFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
@@ -2692,7 +2469,6 @@
},
{
"BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
"PerPkg": "1",
@@ -2702,7 +2478,6 @@
},
{
"BriefDescription": "Snoop Responses Received; Rsp*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSP_WB",
"PerPkg": "1",
@@ -2712,7 +2487,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; Other",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
"PerPkg": "1",
@@ -2722,7 +2496,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspCnflct",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
"PerPkg": "1",
@@ -2732,7 +2505,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
"PerPkg": "1",
@@ -2742,7 +2514,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspIFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
"PerPkg": "1",
@@ -2752,7 +2523,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspS",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
"PerPkg": "1",
@@ -2762,7 +2532,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspSFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
"PerPkg": "1",
@@ -2772,7 +2541,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
"PerPkg": "1",
@@ -2782,7 +2550,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; Rsp*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
"PerPkg": "1",
@@ -2792,7 +2559,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
"PerPkg": "1",
@@ -2802,7 +2568,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
"PerPkg": "1",
@@ -2812,7 +2577,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
"PerPkg": "1",
@@ -2822,7 +2586,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
"PerPkg": "1",
@@ -2832,7 +2595,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
"PerPkg": "1",
@@ -2842,7 +2604,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
"PerPkg": "1",
@@ -2852,7 +2613,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
"PerPkg": "1",
@@ -2862,7 +2622,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
"PerPkg": "1",
@@ -2872,7 +2631,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
"PerPkg": "1",
@@ -2882,7 +2640,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
"PerPkg": "1",
@@ -2892,7 +2649,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
"PerPkg": "1",
@@ -2902,7 +2658,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
"PerPkg": "1",
@@ -2912,7 +2667,6 @@
},
{
"BriefDescription": "Tracker Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_H_TRACKER_CYCLES_NE",
"PerPkg": "1",
@@ -2921,7 +2675,6 @@
},
{
"BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_H_TxR_AD.HOM",
"PerPkg": "1",
@@ -2931,7 +2684,6 @@
},
{
"BriefDescription": "AD Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -2941,7 +2693,6 @@
},
{
"BriefDescription": "AD Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
"PerPkg": "1",
@@ -2951,7 +2702,6 @@
},
{
"BriefDescription": "AD Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
"PerPkg": "1",
@@ -2961,7 +2711,6 @@
},
{
"BriefDescription": "AD Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -2971,7 +2720,6 @@
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
"PerPkg": "1",
@@ -2981,7 +2729,6 @@
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
"PerPkg": "1",
@@ -2991,7 +2738,6 @@
},
{
"BriefDescription": "AD Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.ALL",
"PerPkg": "1",
@@ -3001,7 +2747,6 @@
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
"PerPkg": "1",
@@ -3011,7 +2756,6 @@
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
"PerPkg": "1",
@@ -3021,7 +2765,6 @@
},
{
"BriefDescription": "AD Egress Occupancy; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0",
"PerPkg": "1",
@@ -3031,7 +2774,6 @@
},
{
"BriefDescription": "AD Egress Occupancy; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1",
"PerPkg": "1",
@@ -3041,7 +2783,6 @@
},
{
"BriefDescription": "Outbound Ring Transactions on AK: CRD Transactions to Cbo",
- "Counter": "0,1,2,3",
"EventCode": "0xe",
"EventName": "UNC_H_TxR_AK.CRD_CBO",
"PerPkg": "1",
@@ -3050,7 +2791,6 @@
},
{
"BriefDescription": "AK Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -3060,7 +2800,6 @@
},
{
"BriefDescription": "AK Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
"PerPkg": "1",
@@ -3070,7 +2809,6 @@
},
{
"BriefDescription": "AK Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
"PerPkg": "1",
@@ -3080,7 +2818,6 @@
},
{
"BriefDescription": "AK Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -3090,7 +2827,6 @@
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
"PerPkg": "1",
@@ -3100,7 +2836,6 @@
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
"PerPkg": "1",
@@ -3110,7 +2845,6 @@
},
{
"BriefDescription": "AK Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_H_TxR_AK_INSERTS.ALL",
"PerPkg": "1",
@@ -3120,7 +2854,6 @@
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
"PerPkg": "1",
@@ -3130,7 +2863,6 @@
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
"PerPkg": "1",
@@ -3140,7 +2872,6 @@
},
{
"BriefDescription": "AK Egress Occupancy; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0",
"PerPkg": "1",
@@ -3150,7 +2881,6 @@
},
{
"BriefDescription": "AK Egress Occupancy; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1",
"PerPkg": "1",
@@ -3160,7 +2890,6 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CACHE",
"PerPkg": "1",
@@ -3170,7 +2899,6 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CORE",
"PerPkg": "1",
@@ -3180,7 +2908,6 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_QPI",
"PerPkg": "1",
@@ -3190,7 +2917,6 @@
},
{
"BriefDescription": "BL Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -3200,7 +2926,6 @@
},
{
"BriefDescription": "BL Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
"PerPkg": "1",
@@ -3210,7 +2935,6 @@
},
{
"BriefDescription": "BL Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
"PerPkg": "1",
@@ -3220,7 +2944,6 @@
},
{
"BriefDescription": "BL Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -3230,7 +2953,6 @@
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
"PerPkg": "1",
@@ -3240,7 +2962,6 @@
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
"PerPkg": "1",
@@ -3250,7 +2971,6 @@
},
{
"BriefDescription": "BL Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.ALL",
"PerPkg": "1",
@@ -3260,7 +2980,6 @@
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
"PerPkg": "1",
@@ -3270,7 +2989,6 @@
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
"PerPkg": "1",
@@ -3280,17 +2998,14 @@
},
{
"BriefDescription": "BL Egress Occupancy: All",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "BL Egress Occupancy",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Occupancy; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0",
"PerPkg": "1",
@@ -3300,7 +3015,6 @@
},
{
"BriefDescription": "BL Egress Occupancy; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1",
"PerPkg": "1",
@@ -3310,7 +3024,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
@@ -3320,7 +3033,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
@@ -3330,7 +3042,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
@@ -3340,7 +3051,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
@@ -3350,7 +3060,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
@@ -3360,7 +3069,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
@@ -3370,7 +3078,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
@@ -3380,7 +3087,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json
index 10ea4afeffc1..e1b9799e3036 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Number of qfclks",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_CLOCKTICKS",
"PerPkg": "1",
@@ -10,17 +9,14 @@
},
{
"BriefDescription": "Count of CTO Events",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_Q_CTO_COUNT",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
"PerPkg": "1",
@@ -30,7 +26,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
"PerPkg": "1",
@@ -40,7 +35,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
"PerPkg": "1",
@@ -50,7 +44,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
"PerPkg": "1",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
"PerPkg": "1",
@@ -70,7 +62,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
"PerPkg": "1",
@@ -80,7 +71,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
"PerPkg": "1",
@@ -90,7 +80,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Success",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
"PerPkg": "1",
@@ -100,16 +89,212 @@
},
{
"BriefDescription": "Cycles in L1",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_L1_POWER_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
"Unit": "QPI LL"
},
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MATCH_MASK",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.AnyDataC",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.AnyResp",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.AnyResp11flits",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.AnyResp9flits",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.DataC_E",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_Cmp",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_FrcAckCnflt",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.DataC_F",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_Cmp",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_FrcAckCnflt",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.DataC_M",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.WbEData",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.WbIData",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.DRS.WbSData",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.HOM.AnyReq",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.HOM.AnyResp",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.HOM.RespFwd",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.HOM.RespFwdI",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.HOM.RespFwdIWb",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.HOM.RespFwdS",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.HOM.RespFwdSWb",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.HOM.RespIWb",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.HOM.RespSWb",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.NCB.AnyInt",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg11flits",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg9flits",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg1or2flits",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg3flits",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.NCS.NcRd",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.NDR.AnyCmp",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
+ {
+ "EventCode": "0x38",
+ "EventName": "UNC_Q_MESSAGE.SNP.AnySnp",
+ "PerPkg": "1",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL0P_POWER_CYCLES",
"PerPkg": "1",
@@ -118,7 +303,6 @@
},
{
"BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
"EventCode": "0xf",
"EventName": "UNC_Q_RxL0_POWER_CYCLES",
"PerPkg": "1",
@@ -127,7 +311,6 @@
},
{
"BriefDescription": "Rx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_BYPASSED",
"PerPkg": "1",
@@ -136,7 +319,6 @@
},
{
"BriefDescription": "CRC Errors Detected; LinkInit",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
"PerPkg": "1",
@@ -146,7 +328,6 @@
},
{
"BriefDescription": "CRC Errors Detected; Normal Operations",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
"PerPkg": "1",
@@ -156,10 +337,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.",
"UMask": "0x1",
@@ -167,10 +346,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.",
"UMask": "0x8",
@@ -178,10 +355,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.",
"UMask": "0x2",
@@ -189,10 +364,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.",
"UMask": "0x4",
@@ -200,10 +373,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.",
"UMask": "0x20",
@@ -211,10 +382,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.",
"UMask": "0x10",
@@ -222,10 +391,8 @@
},
{
"BriefDescription": "VN1 Credit Consumed; DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.",
"UMask": "0x1",
@@ -233,10 +400,8 @@
},
{
"BriefDescription": "VN1 Credit Consumed; HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.",
"UMask": "0x8",
@@ -244,10 +409,8 @@
},
{
"BriefDescription": "VN1 Credit Consumed; NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.",
"UMask": "0x2",
@@ -255,10 +418,8 @@
},
{
"BriefDescription": "VN1 Credit Consumed; NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.",
"UMask": "0x4",
@@ -266,10 +427,8 @@
},
{
"BriefDescription": "VN1 Credit Consumed; NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.",
"UMask": "0x20",
@@ -277,10 +436,8 @@
},
{
"BriefDescription": "VN1 Credit Consumed; SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.",
"UMask": "0x10",
@@ -288,17 +445,14 @@
},
{
"BriefDescription": "VNA Credit Consumed",
- "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_Q_RxL_CYCLES_NE",
"PerPkg": "1",
@@ -307,10 +461,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.",
"UMask": "0x1",
@@ -318,10 +470,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.",
"UMask": "0x2",
@@ -329,10 +479,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.",
"UMask": "0x1",
@@ -340,10 +488,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.",
"UMask": "0x2",
@@ -351,10 +497,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.",
"UMask": "0x1",
@@ -362,10 +506,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.",
"UMask": "0x2",
@@ -373,10 +515,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.",
"UMask": "0x1",
@@ -384,10 +524,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.",
"UMask": "0x2",
@@ -395,10 +533,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.",
"UMask": "0x1",
@@ -406,10 +542,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.",
"UMask": "0x2",
@@ -417,10 +551,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.",
"UMask": "0x1",
@@ -428,10 +560,8 @@
},
{
"BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.",
"UMask": "0x2",
@@ -439,7 +569,6 @@
},
{
"BriefDescription": "Flits Received - Group 0; Data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.DATA",
"PerPkg": "1",
@@ -449,7 +578,6 @@
},
{
"BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
"PerPkg": "1",
@@ -459,7 +587,6 @@
},
{
"BriefDescription": "Flits Received - Group 0; Non-Data protocol Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
@@ -469,10 +596,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.",
"UMask": "0x18",
@@ -480,10 +605,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).",
"UMask": "0x8",
@@ -491,10 +614,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.",
"UMask": "0x10",
@@ -502,10 +623,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.",
"UMask": "0x6",
@@ -513,10 +632,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.",
"UMask": "0x4",
@@ -524,10 +641,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
"UMask": "0x2",
@@ -535,10 +650,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.",
"UMask": "0x1",
@@ -546,21 +659,17 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.",
"UMask": "0x4",
@@ -568,10 +677,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.",
"UMask": "0x8",
@@ -579,10 +686,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.",
"UMask": "0x10",
@@ -590,10 +695,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.",
"UMask": "0x1",
@@ -601,10 +704,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.",
"UMask": "0x2",
@@ -612,7 +713,6 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_Q_RxL_INSERTS",
"PerPkg": "1",
@@ -621,20 +721,16 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
"UMask": "0x1",
@@ -642,10 +738,8 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
"UMask": "0x2",
@@ -653,20 +747,16 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_Q_RxL_INSERTS_HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
"UMask": "0x1",
@@ -674,10 +764,8 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
"UMask": "0x2",
@@ -685,20 +773,16 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_Q_RxL_INSERTS_NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"UMask": "0x1",
@@ -706,10 +790,8 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"UMask": "0x2",
@@ -717,20 +799,16 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_Q_RxL_INSERTS_NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"UMask": "0x1",
@@ -738,10 +816,8 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"UMask": "0x2",
@@ -749,20 +825,16 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0xe",
"EventName": "UNC_Q_RxL_INSERTS_NDR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"UMask": "0x1",
@@ -770,10 +842,8 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"UMask": "0x2",
@@ -781,20 +851,16 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_Q_RxL_INSERTS_SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"UMask": "0x1",
@@ -802,10 +868,8 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"UMask": "0x2",
@@ -813,7 +877,6 @@
},
{
"BriefDescription": "RxQ Occupancy - All Packets",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_Q_RxL_OCCUPANCY",
"PerPkg": "1",
@@ -822,20 +885,16 @@
},
{
"BriefDescription": "RxQ Occupancy - DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"UMask": "0x1",
@@ -843,10 +902,8 @@
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"UMask": "0x2",
@@ -854,20 +911,16 @@
},
{
"BriefDescription": "RxQ Occupancy - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"UMask": "0x1",
@@ -875,10 +928,8 @@
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"UMask": "0x2",
@@ -886,20 +937,16 @@
},
{
"BriefDescription": "RxQ Occupancy - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"UMask": "0x1",
@@ -907,10 +954,8 @@
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"UMask": "0x2",
@@ -918,20 +963,16 @@
},
{
"BriefDescription": "RxQ Occupancy - NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"UMask": "0x1",
@@ -939,10 +980,8 @@
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"UMask": "0x2",
@@ -950,20 +989,16 @@
},
{
"BriefDescription": "RxQ Occupancy - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"UMask": "0x1",
@@ -971,10 +1006,8 @@
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"UMask": "0x2",
@@ -982,20 +1015,16 @@
},
{
"BriefDescription": "RxQ Occupancy - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"UMask": "0x1",
@@ -1003,10 +1032,8 @@
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"UMask": "0x2",
@@ -1014,10 +1041,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x1",
@@ -1025,10 +1050,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x8",
@@ -1036,10 +1059,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x2",
@@ -1047,10 +1068,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x4",
@@ -1058,10 +1077,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x20",
@@ -1069,10 +1086,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x10",
@@ -1080,10 +1095,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events.",
"UMask": "0x40",
@@ -1091,10 +1104,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.GV",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.",
"UMask": "0x80",
@@ -1102,10 +1113,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x3a",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x1",
@@ -1113,10 +1122,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x3a",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x8",
@@ -1124,10 +1131,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x3a",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x2",
@@ -1135,10 +1140,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x3a",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x4",
@@ -1146,10 +1149,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x3a",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x20",
@@ -1157,10 +1158,8 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x3a",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x10",
@@ -1168,7 +1167,6 @@
},
{
"BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_Q_TxL0P_POWER_CYCLES",
"PerPkg": "1",
@@ -1177,7 +1175,6 @@
},
{
"BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_Q_TxL0_POWER_CYCLES",
"PerPkg": "1",
@@ -1186,7 +1183,6 @@
},
{
"BriefDescription": "Tx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_Q_TxL_BYPASSED",
"PerPkg": "1",
@@ -1195,7 +1191,6 @@
},
{
"BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
"PerPkg": "1",
@@ -1205,7 +1200,6 @@
},
{
"BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
"PerPkg": "1",
@@ -1215,7 +1209,6 @@
},
{
"BriefDescription": "Tx Flit Buffer Cycles not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_Q_TxL_CYCLES_NE",
"PerPkg": "1",
@@ -1224,7 +1217,6 @@
},
{
"BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.DATA",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.",
@@ -1233,7 +1225,6 @@
},
{
"BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.",
@@ -1242,9 +1233,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.",
"UMask": "0x18",
@@ -1252,9 +1241,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).",
"UMask": "0x8",
@@ -1262,9 +1249,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.",
"UMask": "0x10",
@@ -1272,9 +1257,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.",
"UMask": "0x6",
@@ -1282,9 +1265,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.",
"UMask": "0x4",
@@ -1292,9 +1273,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
"UMask": "0x2",
@@ -1302,9 +1281,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.",
"UMask": "0x1",
@@ -1312,21 +1289,17 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.",
"UMask": "0x4",
@@ -1334,10 +1307,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.",
"UMask": "0x8",
@@ -1345,10 +1316,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.",
"UMask": "0x10",
@@ -1356,10 +1325,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.",
"UMask": "0x1",
@@ -1367,10 +1334,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.",
"UMask": "0x2",
@@ -1378,7 +1343,6 @@
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_Q_TxL_INSERTS",
"PerPkg": "1",
@@ -1387,7 +1351,6 @@
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_Q_TxL_OCCUPANCY",
"PerPkg": "1",
@@ -1396,10 +1359,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
"UMask": "0x1",
@@ -1407,10 +1368,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
"UMask": "0x2",
@@ -1418,10 +1377,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.",
"UMask": "0x1",
@@ -1429,10 +1386,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.",
"UMask": "0x2",
@@ -1440,10 +1395,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x1",
@@ -1451,10 +1404,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x2",
@@ -1462,10 +1413,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x1",
@@ -1473,10 +1422,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x2",
@@ -1484,10 +1431,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x1",
@@ -1495,10 +1440,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x2",
@@ -1506,10 +1449,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x1",
@@ -1517,10 +1458,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x2",
@@ -1528,20 +1467,16 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
"UMask": "0x1",
@@ -1549,10 +1484,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
"UMask": "0x2",
@@ -1560,20 +1493,16 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.",
"UMask": "0x1",
@@ -1581,10 +1510,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.",
"UMask": "0x2",
@@ -1592,10 +1519,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x1",
@@ -1603,10 +1528,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x2",
@@ -1614,10 +1537,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x4",
@@ -1625,10 +1546,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x1",
@@ -1636,10 +1555,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x2",
@@ -1647,10 +1564,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
- "Counter": "0,1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x4",
@@ -1658,10 +1573,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
"UMask": "0x1",
@@ -1669,10 +1582,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
"UMask": "0x2",
@@ -1680,10 +1591,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.",
"UMask": "0x1",
@@ -1691,10 +1600,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.",
"UMask": "0x2",
@@ -1702,10 +1609,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
"UMask": "0x1",
@@ -1713,10 +1618,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
"UMask": "0x2",
@@ -1724,10 +1627,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.",
"UMask": "0x1",
@@ -1735,10 +1636,8 @@
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.",
"UMask": "0x2",
@@ -1746,20 +1645,16 @@
},
{
"BriefDescription": "VNA Credits Returned",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_Q_VNA_CREDIT_RETURNS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of VNA credits returned.",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
"Unit": "QPI LL"
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json
index ed60ebca35cb..65509342d56a 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
@@ -11,7 +10,6 @@
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Read",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.RD",
"PerPkg": "1",
@@ -21,7 +19,6 @@
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.WR",
"PerPkg": "1",
@@ -31,7 +28,6 @@
},
{
"BriefDescription": "ACT command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M_BYP_CMDS.ACT",
"PerPkg": "1",
@@ -40,7 +36,6 @@
},
{
"BriefDescription": "CAS command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M_BYP_CMDS.CAS",
"PerPkg": "1",
@@ -49,7 +44,6 @@
},
{
"BriefDescription": "PRE command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xa1",
"EventName": "UNC_M_BYP_CMDS.PRE",
"PerPkg": "1",
@@ -58,17 +52,15 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
@@ -78,7 +70,6 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
@@ -88,17 +79,14 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_RMM",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
@@ -108,27 +96,23 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_WMM",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
@@ -138,7 +122,6 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
@@ -148,14 +131,12 @@
},
{
"BriefDescription": "DRAM Clockticks",
- "Counter": "0,1,2,3",
"EventName": "UNC_M_DCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
@@ -164,7 +145,6 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
@@ -174,7 +154,6 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
@@ -184,7 +163,6 @@
},
{
"BriefDescription": "ECC Correctable Errors",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
@@ -193,7 +171,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
@@ -203,7 +180,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
@@ -213,7 +189,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Read Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
@@ -223,7 +198,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Write Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
@@ -233,7 +207,6 @@
},
{
"BriefDescription": "Channel DLLOFF Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
@@ -242,7 +215,6 @@
},
{
"BriefDescription": "Channel PPD Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
@@ -251,7 +223,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
@@ -261,7 +232,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
@@ -271,7 +241,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
@@ -281,7 +250,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
@@ -291,7 +259,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
@@ -301,7 +268,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
@@ -311,7 +277,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
@@ -321,7 +286,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
@@ -331,16 +295,20 @@
},
{
"BriefDescription": "Critical Throttle Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.",
"Unit": "iMC"
},
+ {
+ "EventCode": "0x42",
+ "EventName": "UNC_M_POWER_PCU_THROTTLING",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Clock-Enabled Self-Refresh",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
@@ -349,7 +317,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
@@ -359,7 +326,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
@@ -369,7 +335,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
@@ -379,7 +344,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
@@ -389,7 +353,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
@@ -399,7 +362,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
@@ -409,7 +371,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
@@ -419,7 +380,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
@@ -429,7 +389,6 @@
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
@@ -439,7 +398,6 @@
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
@@ -449,7 +407,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.BYP",
"PerPkg": "1",
@@ -459,7 +416,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
@@ -469,7 +425,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
"PerPkg": "1",
@@ -479,7 +434,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to read",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
@@ -489,7 +443,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to write",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
@@ -499,7 +452,6 @@
},
{
"BriefDescription": "Read CAS issued with HIGH priority",
- "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M_RD_CAS_PRIO.HIGH",
"PerPkg": "1",
@@ -508,7 +460,6 @@
},
{
"BriefDescription": "Read CAS issued with LOW priority",
- "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M_RD_CAS_PRIO.LOW",
"PerPkg": "1",
@@ -517,7 +468,6 @@
},
{
"BriefDescription": "Read CAS issued with MEDIUM priority",
- "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M_RD_CAS_PRIO.MED",
"PerPkg": "1",
@@ -526,7 +476,6 @@
},
{
"BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
- "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M_RD_CAS_PRIO.PANIC",
"PerPkg": "1",
@@ -535,7 +484,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK0",
"PerPkg": "1",
@@ -544,7 +492,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK1",
"PerPkg": "1",
@@ -553,7 +500,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK2",
"PerPkg": "1",
@@ -562,7 +508,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK3",
"PerPkg": "1",
@@ -571,7 +516,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK4",
"PerPkg": "1",
@@ -580,7 +524,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK5",
"PerPkg": "1",
@@ -589,7 +532,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK6",
"PerPkg": "1",
@@ -598,7 +540,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK7",
"PerPkg": "1",
@@ -607,7 +548,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK0",
"PerPkg": "1",
@@ -616,7 +556,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK1",
"PerPkg": "1",
@@ -625,7 +564,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK2",
"PerPkg": "1",
@@ -634,7 +572,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK3",
"PerPkg": "1",
@@ -643,7 +580,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK4",
"PerPkg": "1",
@@ -652,7 +588,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK5",
"PerPkg": "1",
@@ -661,7 +596,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK6",
"PerPkg": "1",
@@ -670,7 +604,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK7",
"PerPkg": "1",
@@ -679,7 +612,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK0",
"PerPkg": "1",
@@ -688,7 +620,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK1",
"PerPkg": "1",
@@ -697,7 +628,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK2",
"PerPkg": "1",
@@ -706,7 +636,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK3",
"PerPkg": "1",
@@ -715,7 +644,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK4",
"PerPkg": "1",
@@ -724,7 +652,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK5",
"PerPkg": "1",
@@ -733,7 +660,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK6",
"PerPkg": "1",
@@ -742,7 +668,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK7",
"PerPkg": "1",
@@ -751,7 +676,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK0",
"PerPkg": "1",
@@ -760,7 +684,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK1",
"PerPkg": "1",
@@ -769,7 +692,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK2",
"PerPkg": "1",
@@ -778,7 +700,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK3",
"PerPkg": "1",
@@ -787,7 +708,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK4",
"PerPkg": "1",
@@ -796,7 +716,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK5",
"PerPkg": "1",
@@ -805,7 +724,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK6",
"PerPkg": "1",
@@ -814,7 +732,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK7",
"PerPkg": "1",
@@ -823,7 +740,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK0",
"PerPkg": "1",
@@ -832,7 +748,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK1",
"PerPkg": "1",
@@ -841,7 +756,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK2",
"PerPkg": "1",
@@ -850,7 +764,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK3",
"PerPkg": "1",
@@ -859,7 +772,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK4",
"PerPkg": "1",
@@ -868,7 +780,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK5",
"PerPkg": "1",
@@ -877,7 +788,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK6",
"PerPkg": "1",
@@ -886,7 +796,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK7",
"PerPkg": "1",
@@ -895,7 +804,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK0",
"PerPkg": "1",
@@ -904,7 +812,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK1",
"PerPkg": "1",
@@ -913,7 +820,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK2",
"PerPkg": "1",
@@ -922,7 +828,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK3",
"PerPkg": "1",
@@ -931,7 +836,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK4",
"PerPkg": "1",
@@ -940,7 +844,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK5",
"PerPkg": "1",
@@ -949,7 +852,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK6",
"PerPkg": "1",
@@ -958,7 +860,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK7",
"PerPkg": "1",
@@ -967,7 +868,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK0",
"PerPkg": "1",
@@ -976,7 +876,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK1",
"PerPkg": "1",
@@ -985,7 +884,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK2",
"PerPkg": "1",
@@ -994,7 +892,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK3",
"PerPkg": "1",
@@ -1003,7 +900,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK4",
"PerPkg": "1",
@@ -1012,7 +908,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK5",
"PerPkg": "1",
@@ -1021,7 +916,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK6",
"PerPkg": "1",
@@ -1030,7 +924,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK7",
"PerPkg": "1",
@@ -1039,7 +932,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK0",
"PerPkg": "1",
@@ -1048,7 +940,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK1",
"PerPkg": "1",
@@ -1057,7 +948,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK2",
"PerPkg": "1",
@@ -1066,7 +956,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK3",
"PerPkg": "1",
@@ -1075,7 +964,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK4",
"PerPkg": "1",
@@ -1084,7 +972,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK5",
"PerPkg": "1",
@@ -1093,7 +980,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK6",
"PerPkg": "1",
@@ -1102,7 +988,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK7",
"PerPkg": "1",
@@ -1111,7 +996,6 @@
},
{
"BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
@@ -1120,7 +1004,6 @@
},
{
"BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
@@ -1129,7 +1012,6 @@
},
{
"BriefDescription": "VMSE MXB write buffer occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
"PerPkg": "1",
@@ -1137,7 +1019,6 @@
},
{
"BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M_VMSE_WR_PUSH.RMM",
"PerPkg": "1",
@@ -1146,7 +1027,6 @@
},
{
"BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M_VMSE_WR_PUSH.WMM",
"PerPkg": "1",
@@ -1155,7 +1035,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
- "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"PerPkg": "1",
@@ -1164,7 +1043,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M_WMM_TO_RMM.STARVE",
"PerPkg": "1",
@@ -1173,7 +1051,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"PerPkg": "1",
@@ -1182,7 +1059,6 @@
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
@@ -1191,7 +1067,6 @@
},
{
"BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
@@ -1200,7 +1075,6 @@
},
{
"BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M_WPQ_INSERTS",
"PerPkg": "1",
@@ -1209,7 +1083,6 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
@@ -1218,7 +1091,6 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
@@ -1227,7 +1099,6 @@
},
{
"BriefDescription": "Not getting the requested Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_M_WRONG_MM",
"PerPkg": "1",
@@ -1235,7 +1106,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK0",
"PerPkg": "1",
@@ -1244,7 +1114,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK1",
"PerPkg": "1",
@@ -1253,7 +1122,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK2",
"PerPkg": "1",
@@ -1262,7 +1130,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK3",
"PerPkg": "1",
@@ -1271,7 +1138,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK4",
"PerPkg": "1",
@@ -1280,7 +1146,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK5",
"PerPkg": "1",
@@ -1289,7 +1154,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK6",
"PerPkg": "1",
@@ -1298,7 +1162,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xb8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK7",
"PerPkg": "1",
@@ -1307,7 +1170,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK0",
"PerPkg": "1",
@@ -1316,7 +1178,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK1",
"PerPkg": "1",
@@ -1325,7 +1186,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK2",
"PerPkg": "1",
@@ -1334,7 +1194,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK3",
"PerPkg": "1",
@@ -1343,7 +1202,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK4",
"PerPkg": "1",
@@ -1352,7 +1210,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK5",
"PerPkg": "1",
@@ -1361,7 +1218,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK6",
"PerPkg": "1",
@@ -1370,7 +1226,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK7",
"PerPkg": "1",
@@ -1379,7 +1234,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 2; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M_WR_CAS_RANK2.BANK0",
"PerPkg": "1",
@@ -1388,7 +1242,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 2; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M_WR_CAS_RANK2.BANK1",
"PerPkg": "1",
@@ -1397,7 +1250,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 2; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M_WR_CAS_RANK2.BANK2",
"PerPkg": "1",
@@ -1406,7 +1258,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 2; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M_WR_CAS_RANK2.BANK3",
"PerPkg": "1",
@@ -1415,7 +1266,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 2; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M_WR_CAS_RANK2.BANK4",
"PerPkg": "1",
@@ -1424,7 +1274,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 2; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M_WR_CAS_RANK2.BANK5",
"PerPkg": "1",
@@ -1433,7 +1282,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 2; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M_WR_CAS_RANK2.BANK6",
"PerPkg": "1",
@@ -1442,7 +1290,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 2; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M_WR_CAS_RANK2.BANK7",
"PerPkg": "1",
@@ -1451,7 +1298,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 3; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M_WR_CAS_RANK3.BANK0",
"PerPkg": "1",
@@ -1460,7 +1306,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 3; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M_WR_CAS_RANK3.BANK1",
"PerPkg": "1",
@@ -1469,7 +1314,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 3; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M_WR_CAS_RANK3.BANK2",
"PerPkg": "1",
@@ -1478,7 +1322,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 3; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M_WR_CAS_RANK3.BANK3",
"PerPkg": "1",
@@ -1487,7 +1330,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 3; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M_WR_CAS_RANK3.BANK4",
"PerPkg": "1",
@@ -1496,7 +1338,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 3; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M_WR_CAS_RANK3.BANK5",
"PerPkg": "1",
@@ -1505,7 +1346,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 3; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M_WR_CAS_RANK3.BANK6",
"PerPkg": "1",
@@ -1514,7 +1354,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 3; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M_WR_CAS_RANK3.BANK7",
"PerPkg": "1",
@@ -1523,7 +1362,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK0",
"PerPkg": "1",
@@ -1532,7 +1370,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK1",
"PerPkg": "1",
@@ -1541,7 +1378,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK2",
"PerPkg": "1",
@@ -1550,7 +1386,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK3",
"PerPkg": "1",
@@ -1559,7 +1394,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK4",
"PerPkg": "1",
@@ -1568,7 +1402,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK5",
"PerPkg": "1",
@@ -1577,7 +1410,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK6",
"PerPkg": "1",
@@ -1586,7 +1418,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK7",
"PerPkg": "1",
@@ -1595,7 +1426,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK0",
"PerPkg": "1",
@@ -1604,7 +1434,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK1",
"PerPkg": "1",
@@ -1613,7 +1442,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK2",
"PerPkg": "1",
@@ -1622,7 +1450,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK3",
"PerPkg": "1",
@@ -1631,7 +1458,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK4",
"PerPkg": "1",
@@ -1640,7 +1466,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK5",
"PerPkg": "1",
@@ -1649,7 +1474,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK6",
"PerPkg": "1",
@@ -1658,7 +1482,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK7",
"PerPkg": "1",
@@ -1667,7 +1490,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK0",
"PerPkg": "1",
@@ -1676,7 +1498,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK1",
"PerPkg": "1",
@@ -1685,7 +1506,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK2",
"PerPkg": "1",
@@ -1694,7 +1514,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK3",
"PerPkg": "1",
@@ -1703,7 +1522,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK4",
"PerPkg": "1",
@@ -1712,7 +1530,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK5",
"PerPkg": "1",
@@ -1721,7 +1538,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK6",
"PerPkg": "1",
@@ -1730,7 +1546,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK7",
"PerPkg": "1",
@@ -1739,7 +1554,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK0",
"PerPkg": "1",
@@ -1748,7 +1562,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK1",
"PerPkg": "1",
@@ -1757,7 +1570,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK2",
"PerPkg": "1",
@@ -1766,7 +1578,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK3",
"PerPkg": "1",
@@ -1775,7 +1586,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK4",
"PerPkg": "1",
@@ -1784,7 +1594,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK5",
"PerPkg": "1",
@@ -1793,7 +1602,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK6",
"PerPkg": "1",
@@ -1802,7 +1610,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK7",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json
index 6c7ddf642fc3..af9d14a6d145 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Address Match (Conflict) Count; Conflict Merges",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT",
"PerPkg": "1",
@@ -11,7 +10,6 @@
},
{
"BriefDescription": "Address Match (Conflict) Count; Conflict Stalls",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT",
"PerPkg": "1",
@@ -21,7 +19,6 @@
},
{
"BriefDescription": "Write Ack Pending Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -31,7 +28,6 @@
},
{
"BriefDescription": "Write Ack Pending Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -41,7 +37,6 @@
},
{
"BriefDescription": "Outstanding Write Ownership Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -51,7 +46,6 @@
},
{
"BriefDescription": "Outstanding Write Ownership Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -61,7 +55,6 @@
},
{
"BriefDescription": "Outstanding Read Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -71,7 +64,6 @@
},
{
"BriefDescription": "Outstanding Read Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -81,7 +73,6 @@
},
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -91,7 +82,6 @@
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -101,7 +91,6 @@
},
{
"BriefDescription": "Outstanding Write Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -111,7 +100,6 @@
},
{
"BriefDescription": "Outstanding Write Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -121,14 +109,12 @@
},
{
"BriefDescription": "Clocks in the IRP",
- "Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Number of clocks in the IRP.",
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0xb",
"EventName": "UNC_I_RxR_AK_CYCLES_FULL",
"PerPkg": "1",
@@ -137,7 +123,6 @@
},
{
"BriefDescription": "AK Ingress Occupancy",
- "Counter": "0,1",
"EventCode": "0xa",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
@@ -145,7 +130,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0xc",
"EventName": "UNC_I_RxR_AK_OCCUPANCY",
"PerPkg": "1",
@@ -153,7 +137,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
@@ -162,7 +145,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
- "Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
@@ -170,7 +152,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
@@ -178,7 +159,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
@@ -187,7 +167,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
@@ -195,7 +174,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
@@ -203,7 +181,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
@@ -212,7 +189,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
@@ -220,7 +196,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
@@ -229,7 +204,6 @@
},
{
"BriefDescription": "Tickle Count; Ownership Lost",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TICKLES.LOST_OWNERSHIP",
"PerPkg": "1",
@@ -239,7 +213,6 @@
},
{
"BriefDescription": "Tickle Count; Data Returned",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TICKLES.TOP_OF_QUEUE",
"PerPkg": "1",
@@ -249,7 +222,6 @@
},
{
"BriefDescription": "Inbound Transaction Count: Read Prefetches",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES",
"PerPkg": "1",
@@ -259,7 +231,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.RD_PREFETCHES",
"PerPkg": "1",
@@ -269,7 +240,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Reads",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
@@ -279,7 +249,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Writes",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
@@ -289,7 +258,6 @@
},
{
"BriefDescription": "No AD Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@@ -298,7 +266,6 @@
},
{
"BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@@ -307,7 +274,6 @@
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xe",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
@@ -316,7 +282,6 @@
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xf",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
@@ -325,7 +290,6 @@
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
"EventCode": "0xd",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
@@ -334,7 +298,6 @@
},
{
"BriefDescription": "Write Ordering Stalls",
- "Counter": "0,1",
"EventCode": "0x1a",
"EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES",
"PerPkg": "1",
@@ -343,7 +306,6 @@
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
@@ -352,7 +314,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
@@ -362,7 +323,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
@@ -372,7 +332,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
@@ -382,7 +341,6 @@
},
{
"BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -392,7 +350,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; DRS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -402,7 +359,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCB",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -412,7 +368,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -422,17 +377,15 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_VR0_EVEN",
"PerPkg": "1",
@@ -442,7 +395,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_VR0_ODD",
"PerPkg": "1",
@@ -452,7 +404,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_VR1_EVEN",
"PerPkg": "1",
@@ -462,7 +413,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_VR1_ODD",
"PerPkg": "1",
@@ -472,7 +422,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW",
"PerPkg": "1",
@@ -482,7 +431,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_VR0_EVEN",
"PerPkg": "1",
@@ -492,7 +440,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_VR0_ODD",
"PerPkg": "1",
@@ -502,7 +449,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_VR1_EVEN",
"PerPkg": "1",
@@ -512,7 +458,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_VR1_ODD",
"PerPkg": "1",
@@ -522,17 +467,15 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_VR0_EVEN",
"PerPkg": "1",
@@ -542,7 +485,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_VR0_ODD",
"PerPkg": "1",
@@ -552,7 +494,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_VR1_EVEN",
"PerPkg": "1",
@@ -562,7 +503,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_VR1_ODD",
"PerPkg": "1",
@@ -572,7 +512,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW",
"PerPkg": "1",
@@ -582,7 +521,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_VR0_EVEN",
"PerPkg": "1",
@@ -592,7 +530,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_VR0_ODD",
"PerPkg": "1",
@@ -602,7 +539,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_VR1_EVEN",
"PerPkg": "1",
@@ -612,7 +548,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_VR1_ODD",
"PerPkg": "1",
@@ -622,17 +557,15 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_VR0_EVEN",
"PerPkg": "1",
@@ -642,7 +575,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_VR0_ODD",
"PerPkg": "1",
@@ -652,7 +584,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_VR1_EVEN",
"PerPkg": "1",
@@ -662,7 +593,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_VR1_ODD",
"PerPkg": "1",
@@ -672,7 +602,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW",
"PerPkg": "1",
@@ -682,7 +611,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_VR0_EVEN",
"PerPkg": "1",
@@ -692,7 +620,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_VR0_ODD",
"PerPkg": "1",
@@ -702,7 +629,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_VR1_EVEN",
"PerPkg": "1",
@@ -712,7 +638,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_VR1_ODD",
"PerPkg": "1",
@@ -722,27 +647,24 @@
},
{
"BriefDescription": "R2 IV Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity",
- "UMask": "0xFF",
+ "UMask": "0xff",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_R2_RING_IV_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_R2_RING_IV_USED.CW",
"PerPkg": "1",
@@ -778,7 +700,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
@@ -788,7 +709,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
@@ -798,7 +718,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCB",
"PerPkg": "1",
@@ -808,7 +727,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCS",
"PerPkg": "1",
@@ -881,7 +799,6 @@
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_TxR_NACK_CCW.AD",
"PerPkg": "1",
@@ -891,7 +808,6 @@
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_TxR_NACK_CCW.AK",
"PerPkg": "1",
@@ -901,7 +817,6 @@
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_TxR_NACK_CCW.BL",
"PerPkg": "1",
@@ -911,7 +826,6 @@
},
{
"BriefDescription": "Egress CW NACK; AD CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.AD",
"PerPkg": "1",
@@ -921,7 +835,6 @@
},
{
"BriefDescription": "Egress CW NACK; AK CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.AK",
"PerPkg": "1",
@@ -931,7 +844,6 @@
},
{
"BriefDescription": "Egress CW NACK; BL CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.BL",
"PerPkg": "1",
@@ -941,7 +853,6 @@
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2",
"EventCode": "0x1",
"EventName": "UNC_R3_CLOCKTICKS",
"PerPkg": "1",
@@ -950,7 +861,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2c",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
"PerPkg": "1",
@@ -960,7 +870,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2c",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
"PerPkg": "1",
@@ -970,7 +879,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2c",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
"PerPkg": "1",
@@ -980,7 +888,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2c",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
"PerPkg": "1",
@@ -990,7 +897,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2c",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14",
"PerPkg": "1",
@@ -1000,7 +906,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2c",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
"PerPkg": "1",
@@ -1010,7 +915,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2c",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
"PerPkg": "1",
@@ -1020,7 +924,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2b",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
"PerPkg": "1",
@@ -1030,7 +933,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2b",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
"PerPkg": "1",
@@ -1040,7 +942,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2b",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
"PerPkg": "1",
@@ -1050,7 +951,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2b",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
"PerPkg": "1",
@@ -1060,7 +960,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2b",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
"PerPkg": "1",
@@ -1070,7 +969,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2b",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
"PerPkg": "1",
@@ -1080,7 +978,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2b",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
"PerPkg": "1",
@@ -1090,7 +987,6 @@
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2b",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
"PerPkg": "1",
@@ -1100,7 +996,6 @@
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2f",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
"PerPkg": "1",
@@ -1110,7 +1005,6 @@
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2f",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
"PerPkg": "1",
@@ -1120,7 +1014,6 @@
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2f",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
"PerPkg": "1",
@@ -1130,7 +1023,6 @@
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2f",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
"PerPkg": "1",
@@ -1140,7 +1032,6 @@
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
@@ -1150,7 +1041,6 @@
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
@@ -1160,7 +1050,6 @@
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
@@ -1170,7 +1059,6 @@
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
@@ -1180,7 +1068,6 @@
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
@@ -1190,7 +1077,6 @@
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
@@ -1200,7 +1086,6 @@
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
@@ -1210,7 +1095,6 @@
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
@@ -1220,7 +1104,6 @@
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
@@ -1230,7 +1113,6 @@
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
@@ -1240,7 +1122,6 @@
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
@@ -1250,7 +1131,6 @@
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
@@ -1260,7 +1140,6 @@
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
@@ -1270,7 +1149,6 @@
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
@@ -1280,7 +1158,6 @@
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2a",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
@@ -1290,7 +1167,6 @@
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2a",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
@@ -1300,7 +1176,6 @@
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2a",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
@@ -1310,7 +1185,6 @@
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2a",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
@@ -1320,7 +1194,6 @@
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2a",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
@@ -1330,7 +1203,6 @@
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2a",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
@@ -1340,7 +1212,6 @@
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2a",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
@@ -1350,7 +1221,6 @@
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2e",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
@@ -1360,7 +1230,6 @@
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2e",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
@@ -1370,7 +1239,6 @@
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2e",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
@@ -1380,7 +1248,6 @@
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2e",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
@@ -1390,7 +1257,6 @@
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2e",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
@@ -1400,7 +1266,6 @@
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2e",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
@@ -1410,7 +1275,6 @@
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2e",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
@@ -1420,17 +1284,15 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_VR0_EVEN",
"PerPkg": "1",
@@ -1440,7 +1302,6 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_VR0_ODD",
"PerPkg": "1",
@@ -1450,7 +1311,6 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW",
"PerPkg": "1",
@@ -1460,7 +1320,6 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise and Even on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW_VR0_EVEN",
"PerPkg": "1",
@@ -1470,7 +1329,6 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise and Odd on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW_VR0_ODD",
"PerPkg": "1",
@@ -1480,17 +1338,15 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_VR0_EVEN",
"PerPkg": "1",
@@ -1500,7 +1356,6 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_VR0_ODD",
"PerPkg": "1",
@@ -1510,7 +1365,6 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW",
"PerPkg": "1",
@@ -1520,7 +1374,6 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise and Even on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW_VR0_EVEN",
"PerPkg": "1",
@@ -1530,7 +1383,6 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise and Odd on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW_VR0_ODD",
"PerPkg": "1",
@@ -1540,17 +1392,15 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_VR0_EVEN",
"PerPkg": "1",
@@ -1560,7 +1410,6 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_VR0_ODD",
"PerPkg": "1",
@@ -1570,7 +1419,6 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW",
"PerPkg": "1",
@@ -1580,7 +1428,6 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise and Even on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW_VR0_EVEN",
"PerPkg": "1",
@@ -1590,7 +1437,6 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise and Odd on VRing 0",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW_VR0_ODD",
"PerPkg": "1",
@@ -1600,27 +1446,24 @@
},
{
"BriefDescription": "R2 IV Ring in Use; Any",
- "Counter": "0,1,2",
"EventCode": "0xA",
"EventName": "UNC_R3_RING_IV_USED.ANY",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity",
- "UMask": "0xFF",
+ "UMask": "0xff",
"Unit": "R3QPI"
},
{
"BriefDescription": "R2 IV Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
"EventCode": "0xa",
"EventName": "UNC_R3_RING_IV_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R2 IV Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0xa",
"EventName": "UNC_R3_RING_IV_USED.CW",
"PerPkg": "1",
@@ -1630,7 +1473,6 @@
},
{
"BriefDescription": "AD Ingress Bypassed",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_R3_RxR_AD_BYPASSED",
"PerPkg": "1",
@@ -1639,7 +1481,6 @@
},
{
"BriefDescription": "Ingress Bypassed",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_R3_RxR_BYPASSED.AD",
"PerPkg": "1",
@@ -1649,7 +1490,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; HOM",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
"PerPkg": "1",
@@ -1659,7 +1499,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NDR",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
"PerPkg": "1",
@@ -1669,7 +1508,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; SNP",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
"PerPkg": "1",
@@ -1679,7 +1517,6 @@
},
{
"BriefDescription": "Ingress Allocations; DRS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.DRS",
"PerPkg": "1",
@@ -1689,7 +1526,6 @@
},
{
"BriefDescription": "Ingress Allocations; HOM",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.HOM",
"PerPkg": "1",
@@ -1699,7 +1535,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCB",
"PerPkg": "1",
@@ -1709,7 +1544,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCS",
"PerPkg": "1",
@@ -1719,7 +1553,6 @@
},
{
"BriefDescription": "Ingress Allocations; NDR",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NDR",
"PerPkg": "1",
@@ -1729,7 +1562,6 @@
},
{
"BriefDescription": "Ingress Allocations; SNP",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.SNP",
"PerPkg": "1",
@@ -1793,7 +1625,6 @@
},
{
"BriefDescription": "Egress NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_TxR_NACK_CCW.AD",
"PerPkg": "1",
@@ -1803,7 +1634,6 @@
},
{
"BriefDescription": "Egress NACK; BL CW",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_TxR_NACK_CCW.AK",
"PerPkg": "1",
@@ -1813,7 +1643,6 @@
},
{
"BriefDescription": "Egress NACK; BL CCW",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_TxR_NACK_CCW.BL",
"PerPkg": "1",
@@ -1823,7 +1652,6 @@
},
{
"BriefDescription": "Egress NACK; AD CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK_CW.AD",
"PerPkg": "1",
@@ -1833,7 +1661,6 @@
},
{
"BriefDescription": "Egress NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK_CW.AK",
"PerPkg": "1",
@@ -1843,7 +1670,6 @@
},
{
"BriefDescription": "Egress NACK; AK CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK_CW.BL",
"PerPkg": "1",
@@ -1853,7 +1679,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -1863,7 +1688,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
"PerPkg": "1",
@@ -1873,7 +1697,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -1883,7 +1706,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -1893,7 +1715,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
"PerPkg": "1",
@@ -1903,7 +1724,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
"PerPkg": "1",
@@ -1913,7 +1733,6 @@
},
{
"BriefDescription": "VN0 Credit Used; DRS Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -1923,7 +1742,6 @@
},
{
"BriefDescription": "VN0 Credit Used; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
"PerPkg": "1",
@@ -1933,7 +1751,6 @@
},
{
"BriefDescription": "VN0 Credit Used; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -1943,7 +1760,6 @@
},
{
"BriefDescription": "VN0 Credit Used; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -1953,7 +1769,6 @@
},
{
"BriefDescription": "VN0 Credit Used; NDR Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
"PerPkg": "1",
@@ -1963,7 +1778,6 @@
},
{
"BriefDescription": "VN0 Credit Used; SNP Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
@@ -1973,7 +1787,6 @@
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -1983,7 +1796,6 @@
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
"PerPkg": "1",
@@ -1993,7 +1805,6 @@
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -2003,7 +1814,6 @@
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -2013,7 +1823,6 @@
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
"PerPkg": "1",
@@ -2023,7 +1832,6 @@
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
"PerPkg": "1",
@@ -2033,7 +1841,6 @@
},
{
"BriefDescription": "VN1 Credit Used; DRS Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -2043,7 +1850,6 @@
},
{
"BriefDescription": "VN1 Credit Used; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
"PerPkg": "1",
@@ -2053,7 +1859,6 @@
},
{
"BriefDescription": "VN1 Credit Used; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -2063,7 +1868,6 @@
},
{
"BriefDescription": "VN1 Credit Used; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -2073,7 +1877,6 @@
},
{
"BriefDescription": "VN1 Credit Used; NDR Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
"PerPkg": "1",
@@ -2083,7 +1886,6 @@
},
{
"BriefDescription": "VN1 Credit Used; SNP Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
"PerPkg": "1",
@@ -2093,7 +1895,6 @@
},
{
"BriefDescription": "VNA credit Acquisitions",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED",
"PerPkg": "1",
@@ -2102,7 +1903,6 @@
},
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
@@ -2112,7 +1912,6 @@
},
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
@@ -2122,7 +1921,6 @@
},
{
"BriefDescription": "VNA Credit Reject; DRS Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -2132,7 +1930,6 @@
},
{
"BriefDescription": "VNA Credit Reject; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
"PerPkg": "1",
@@ -2142,7 +1939,6 @@
},
{
"BriefDescription": "VNA Credit Reject; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -2152,7 +1948,6 @@
},
{
"BriefDescription": "VNA Credit Reject; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -2162,7 +1957,6 @@
},
{
"BriefDescription": "VNA Credit Reject; NDR Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
"PerPkg": "1",
@@ -2172,7 +1966,6 @@
},
{
"BriefDescription": "VNA Credit Reject; SNP Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
"PerPkg": "1",
@@ -2182,7 +1975,6 @@
},
{
"BriefDescription": "Cycles with no VNA credits available",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT",
"PerPkg": "1",
@@ -2191,16 +1983,19 @@
},
{
"BriefDescription": "Cycles with 1 or more VNA credits in use",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED",
"PerPkg": "1",
"PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.",
"Unit": "R3QPI"
},
+ {
+ "EventName": "UNC_U_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "UBOX"
+ },
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
@@ -2210,7 +2005,6 @@
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.INT_PRIO",
"PerPkg": "1",
@@ -2220,7 +2014,6 @@
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
"PerPkg": "1",
@@ -2230,7 +2023,6 @@
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
"PerPkg": "1",
@@ -2240,7 +2032,6 @@
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
"PerPkg": "1",
@@ -2250,7 +2041,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
@@ -2260,7 +2050,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
@@ -2270,7 +2059,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
@@ -2280,7 +2068,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
@@ -2290,7 +2077,6 @@
},
{
"BriefDescription": "IDI Lock/SplitLock Cycles",
- "Counter": "0,1",
"EventCode": "0x44",
"EventName": "UNC_U_LOCK_CYCLES",
"PerPkg": "1",
@@ -2299,7 +2085,6 @@
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
- "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
@@ -2309,7 +2094,6 @@
},
{
"BriefDescription": "RACU Request",
- "Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
@@ -2317,7 +2101,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
@@ -2327,7 +2110,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
@@ -2337,7 +2119,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
@@ -2347,7 +2128,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T0",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
@@ -2357,7 +2137,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T1",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
@@ -2367,7 +2146,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Other",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
@@ -2377,7 +2155,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Trap",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
@@ -2387,7 +2164,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json
index 74c87217d75c..5df1ebfb89ea 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "pclk Cycles",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Core 0 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -18,7 +16,6 @@
},
{
"BriefDescription": "Core 10 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x7a",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -27,7 +24,6 @@
},
{
"BriefDescription": "Core 11 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x7b",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "Core 12 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x7c",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -45,7 +40,6 @@
},
{
"BriefDescription": "Core 13 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x7d",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -54,7 +48,6 @@
},
{
"BriefDescription": "Core 14 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x7e",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -63,7 +56,6 @@
},
{
"BriefDescription": "Core 1 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -72,7 +64,6 @@
},
{
"BriefDescription": "Core 2 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -81,7 +72,6 @@
},
{
"BriefDescription": "Core 3 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -90,7 +80,6 @@
},
{
"BriefDescription": "Core 4 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -99,7 +88,6 @@
},
{
"BriefDescription": "Core 5 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -108,7 +96,6 @@
},
{
"BriefDescription": "Core 6 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -117,7 +104,6 @@
},
{
"BriefDescription": "Core 7 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -126,7 +112,6 @@
},
{
"BriefDescription": "Core 8 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x78",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -135,7 +120,6 @@
},
{
"BriefDescription": "Core 9 C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -144,157 +128,126 @@
},
{
"BriefDescription": "Deep C State Rejection - Core 0",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE0",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE1",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 10",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE10",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 11",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE11",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 12",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE12",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 13",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE13",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 14",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE14",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 2",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE2",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 3",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE3",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 4",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE4",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 5",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE5",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 6",
- "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE6",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 7",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE7",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 8",
- "Counter": "0,1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE8",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Deep C State Rejection - Core 9",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE9",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
"Unit": "PCU"
},
{
"BriefDescription": "Core 0 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
@@ -303,7 +256,6 @@
},
{
"BriefDescription": "Core 1 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
@@ -312,7 +264,6 @@
},
{
"BriefDescription": "Core 10 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
@@ -321,7 +272,6 @@
},
{
"BriefDescription": "Core 11 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
@@ -330,7 +280,6 @@
},
{
"BriefDescription": "Core 12 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
@@ -339,7 +288,6 @@
},
{
"BriefDescription": "Core 13 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
@@ -348,7 +296,6 @@
},
{
"BriefDescription": "Core 14 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
@@ -357,7 +304,6 @@
},
{
"BriefDescription": "Core 2 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
@@ -366,7 +312,6 @@
},
{
"BriefDescription": "Core 3 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
@@ -375,7 +320,6 @@
},
{
"BriefDescription": "Core 4 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
@@ -384,7 +328,6 @@
},
{
"BriefDescription": "Core 5 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
@@ -393,7 +336,6 @@
},
{
"BriefDescription": "Core 6 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
@@ -402,7 +344,6 @@
},
{
"BriefDescription": "Core 7 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
@@ -411,7 +352,6 @@
},
{
"BriefDescription": "Core 8 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
@@ -420,7 +360,6 @@
},
{
"BriefDescription": "Core 9 C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
@@ -429,7 +368,6 @@
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_P_FREQ_BAND0_CYCLES",
"PerPkg": "1",
@@ -438,7 +376,6 @@
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_P_FREQ_BAND1_CYCLES",
"PerPkg": "1",
@@ -447,7 +384,6 @@
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_P_FREQ_BAND2_CYCLES",
"PerPkg": "1",
@@ -456,7 +392,6 @@
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xe",
"EventName": "UNC_P_FREQ_BAND3_CYCLES",
"PerPkg": "1",
@@ -465,7 +400,6 @@
},
{
"BriefDescription": "Current Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES",
"PerPkg": "1",
@@ -474,7 +408,6 @@
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
@@ -483,7 +416,6 @@
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
@@ -492,7 +424,6 @@
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
@@ -501,7 +432,6 @@
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
@@ -510,7 +440,6 @@
},
{
"BriefDescription": "Perf P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES",
"PerPkg": "1",
@@ -519,7 +448,6 @@
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
@@ -528,7 +456,6 @@
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
@@ -537,67 +464,54 @@
},
{
"BriefDescription": "Package C State Exit Latency",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_P_PKG_C_EXIT_LATENCY",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the package is transitioning from package C2 to C3.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Exit Latency",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_P_PKG_C_EXIT_LATENCY_SEL",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the package is transitioning from package C2 to C3.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C0_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the package is in C0",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2",
- "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C2_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the package is in C2",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C3_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the package is in C3",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C6_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the package is in C6",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
@@ -606,7 +520,6 @@
},
{
"BriefDescription": "Number of cores in C-State; C3",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
@@ -615,7 +528,6 @@
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
@@ -624,7 +536,6 @@
},
{
"BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
@@ -633,7 +544,6 @@
},
{
"BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
@@ -642,7 +552,6 @@
},
{
"BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -651,7 +560,6 @@
},
{
"BriefDescription": "Cycles Changing Voltage",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE",
"PerPkg": "1",
@@ -660,7 +568,6 @@
},
{
"BriefDescription": "Cycles Decreasing Voltage",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE",
"PerPkg": "1",
@@ -669,7 +576,6 @@
},
{
"BriefDescription": "Cycles Increasing Voltage",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE",
"PerPkg": "1",
@@ -678,7 +584,6 @@
},
{
"BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
index 6624d02ad715..410763dd4394 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION",
"SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
},
{
"BriefDescription": "Page walk for a large page completed for Demand load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -28,8 +22,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5F",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
@@ -48,8 +38,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.",
@@ -58,8 +46,6 @@
},
{
"BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "Cycle PMH is busy with a walk due to demand loads.",
@@ -68,8 +54,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
@@ -78,8 +62,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
@@ -88,8 +70,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).",
@@ -98,8 +78,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"PublicDescription": "Cycles PMH is busy with this walk.",
@@ -108,8 +86,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
@@ -117,8 +93,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
@@ -127,8 +101,6 @@
},
{
"BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",
"PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
@@ -137,8 +109,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all ITLB levels that cause page walks.",
@@ -147,8 +117,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "Number of cache load STLB hits. No page walk.",
@@ -157,8 +125,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
@@ -167,8 +133,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "Cycle PMH is busy with a walk.",
@@ -177,8 +141,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "DTLB flush attempts of the thread-specific entries.",
@@ -187,8 +149,6 @@
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Count number of STLB flush attempts.",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 18/32] perf vendor events intel: Refresh jaketown metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (7 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 17/32] perf vendor events intel: Refresh ivytown " Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 19/32] perf vendor events intel: Refresh knightslanding events Ian Rogers
` (13 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the jaketown metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/jaketown/cache.json | 289 ------------------
.../arch/x86/jaketown/floating-point.json | 30 --
.../arch/x86/jaketown/frontend.json | 64 ----
.../arch/x86/jaketown/jkt-metrics.json | 91 +++---
.../pmu-events/arch/x86/jaketown/memory.json | 103 -------
.../pmu-events/arch/x86/jaketown/other.json | 12 -
.../arch/x86/jaketown/pipeline.json | 255 ----------------
.../arch/x86/jaketown/uncore-cache.json | 266 +++-------------
.../x86/jaketown/uncore-interconnect.json | 132 --------
.../arch/x86/jaketown/uncore-memory.json | 58 ----
.../arch/x86/jaketown/uncore-other.json | 155 +---------
.../arch/x86/jaketown/uncore-power.json | 51 ----
.../arch/x86/jaketown/virtual-memory.json | 32 --
13 files changed, 106 insertions(+), 1432 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/perf/pmu-events/arch/x86/jaketown/cache.json
index f98649fb92b4..f1271039b6b2 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/cache.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Allocated L1D data cache lines in M state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.ALLOCATED_IN_M",
"SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.ALL_M_REPLACEMENT",
"SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
},
{
"BriefDescription": "L1D data cache lines in M state evicted due to replacement.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.EVICTION",
"SampleAfterValue": "2000003",
@@ -28,8 +22,6 @@
},
{
"BriefDescription": "L1D data line replacements.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xBF",
"EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES",
@@ -48,8 +38,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -58,8 +46,6 @@
},
{
"BriefDescription": "L1D miss oustandings duration in cycles.",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"SampleAfterValue": "2000003",
@@ -67,8 +53,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -78,8 +62,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -88,8 +70,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.ALL",
"SampleAfterValue": "200003",
@@ -97,8 +77,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_E",
"SampleAfterValue": "200003",
@@ -106,8 +84,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_M",
"SampleAfterValue": "200003",
@@ -115,8 +91,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_S",
"SampleAfterValue": "200003",
@@ -124,8 +98,6 @@
},
{
"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.MISS",
"SampleAfterValue": "200003",
@@ -133,8 +105,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
@@ -143,8 +113,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"SampleAfterValue": "100003",
@@ -152,8 +120,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"SampleAfterValue": "100003",
@@ -161,8 +127,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"SampleAfterValue": "100003",
@@ -170,8 +134,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100003",
@@ -179,8 +141,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100003",
@@ -188,8 +148,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines filling the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DIRTY_ALL",
"SampleAfterValue": "100003",
@@ -197,8 +155,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_CLEAN",
"SampleAfterValue": "100003",
@@ -206,8 +162,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_DIRTY",
"SampleAfterValue": "100003",
@@ -215,8 +169,6 @@
},
{
"BriefDescription": "L2 code requests.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"SampleAfterValue": "200003",
@@ -224,8 +176,6 @@
},
{
"BriefDescription": "Demand Data Read requests.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"SampleAfterValue": "200003",
@@ -233,8 +183,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"SampleAfterValue": "200003",
@@ -242,8 +190,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"SampleAfterValue": "200003",
@@ -251,8 +197,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
@@ -260,8 +204,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003",
@@ -269,8 +211,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"SampleAfterValue": "200003",
@@ -278,8 +218,6 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"SampleAfterValue": "200003",
@@ -287,8 +225,6 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"SampleAfterValue": "200003",
@@ -296,8 +232,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
@@ -305,8 +239,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003",
@@ -314,8 +246,6 @@
},
{
"BriefDescription": "RFOs that access cache lines in any state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.ALL",
"SampleAfterValue": "200003",
@@ -323,8 +253,6 @@
},
{
"BriefDescription": "RFOs that hit cache lines in E state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_E",
"SampleAfterValue": "200003",
@@ -332,8 +260,6 @@
},
{
"BriefDescription": "RFOs that hit cache lines in M state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
"SampleAfterValue": "200003",
@@ -341,8 +267,6 @@
},
{
"BriefDescription": "RFOs that miss cache lines.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.MISS",
"SampleAfterValue": "200003",
@@ -350,8 +274,6 @@
},
{
"BriefDescription": "L2 or LLC HW prefetches that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"SampleAfterValue": "200003",
@@ -359,8 +281,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"SampleAfterValue": "200003",
@@ -368,8 +288,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"SampleAfterValue": "200003",
@@ -377,8 +295,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"SampleAfterValue": "200003",
@@ -386,8 +302,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"SampleAfterValue": "200003",
@@ -395,8 +309,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"SampleAfterValue": "200003",
@@ -404,8 +316,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"SampleAfterValue": "200003",
@@ -413,8 +323,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"SampleAfterValue": "200003",
@@ -422,8 +330,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"SampleAfterValue": "2000003",
@@ -431,8 +337,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100003",
@@ -440,8 +344,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "100003",
@@ -449,8 +351,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.",
@@ -459,8 +359,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.",
@@ -469,8 +367,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
"SampleAfterValue": "20011",
@@ -478,8 +374,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
"SampleAfterValue": "100003",
@@ -487,8 +381,6 @@
},
{
"BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
"SampleAfterValue": "100007",
@@ -496,8 +388,6 @@
},
{
"BriefDescription": "Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",
"SampleAfterValue": "100007",
@@ -505,8 +395,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -515,8 +403,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
@@ -525,8 +411,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
@@ -535,8 +419,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.",
@@ -545,8 +427,6 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
"SampleAfterValue": "100007",
@@ -554,8 +434,6 @@
},
{
"BriefDescription": "All retired load uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
@@ -565,8 +443,6 @@
},
{
"BriefDescription": "All retired store uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
@@ -576,8 +452,6 @@
},
{
"BriefDescription": "Retired load uops with locked access.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
@@ -586,8 +460,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
@@ -597,8 +469,6 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
@@ -608,8 +478,6 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
@@ -618,8 +486,6 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PEBS": "1",
@@ -628,8 +494,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"SampleAfterValue": "100003",
@@ -637,8 +501,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"SampleAfterValue": "100003",
@@ -646,8 +508,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"SampleAfterValue": "100003",
@@ -655,8 +515,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"SampleAfterValue": "100003",
@@ -664,8 +522,6 @@
},
{
"BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"SampleAfterValue": "2000003",
@@ -673,8 +529,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"SampleAfterValue": "2000003",
@@ -682,8 +536,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -692,8 +544,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -702,8 +552,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -712,8 +560,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"SampleAfterValue": "2000003",
@@ -721,8 +567,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6",
@@ -731,8 +575,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"SampleAfterValue": "2000003",
@@ -740,524 +582,393 @@
},
{
"BriefDescription": "Counts all demand & prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x000105B3",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x000107F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch prefetch RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all writebacks from the core to the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10008",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand rfo's",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803c8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23ffc08000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts non-temporal stores",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
index eb2ff2cfdf6b..8c2a246adef9 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles with any input/output SSE or FP assist.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"SampleAfterValue": "100003",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"SampleAfterValue": "100003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"SampleAfterValue": "100003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"SampleAfterValue": "100003",
@@ -47,8 +37,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@@ -56,8 +44,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"SampleAfterValue": "2000003",
@@ -65,8 +51,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
@@ -74,8 +58,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"SampleAfterValue": "2000003",
@@ -83,8 +65,6 @@
},
{
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000003",
@@ -92,8 +72,6 @@
},
{
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"SampleAfterValue": "100003",
@@ -101,8 +79,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
@@ -110,8 +86,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
@@ -119,8 +93,6 @@
},
{
"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@@ -128,8 +100,6 @@
},
{
"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
index 0b4dbce2f1c0..3f4fc3481112 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.ALL_CANCEL",
"SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"SampleAfterValue": "2000003",
@@ -47,8 +37,6 @@
},
{
"BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.OTHER_CANCEL",
"SampleAfterValue": "2000003",
@@ -56,8 +44,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
@@ -65,8 +51,6 @@
},
{
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
@@ -75,8 +59,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -85,8 +67,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -95,8 +75,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -105,8 +83,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -115,8 +91,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -125,8 +99,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"SampleAfterValue": "2000003",
@@ -134,8 +106,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"SampleAfterValue": "2000003",
@@ -143,8 +113,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"SampleAfterValue": "2000003",
@@ -152,8 +120,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -162,8 +128,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"SampleAfterValue": "2000003",
@@ -171,8 +135,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -182,8 +144,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -192,8 +152,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -203,8 +161,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"SampleAfterValue": "2000003",
@@ -212,8 +168,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"SampleAfterValue": "2000003",
@@ -221,8 +175,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -232,8 +184,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"SampleAfterValue": "2000003",
@@ -241,8 +191,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
@@ -251,8 +199,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -261,8 +207,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -272,8 +216,6 @@
},
{
"BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
@@ -283,8 +225,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -293,8 +233,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -303,8 +241,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
index 554f87c03c05..cb1420df3768 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
@@ -65,7 +65,7 @@
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -73,7 +73,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -97,7 +97,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+ "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -113,7 +113,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -121,7 +121,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -169,7 +169,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS",
+ "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -233,7 +233,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -284,19 +284,19 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
+ "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_DISPATCHED.THREAD / ((cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
+ "MetricExpr": "UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
@@ -314,25 +314,25 @@
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1000000000) / duration_time",
+ "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -345,7 +345,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@@ -363,10 +363,22 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
+ {
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
+ },
+ {
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
+ },
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
"MetricExpr": "cbox_0@event\\=0x0@",
@@ -379,52 +391,59 @@
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
+ {
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
+ },
{
"BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
- },
- {
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/perf/pmu-events/arch/x86/jaketown/memory.json
index 23756ca9b7da..a71e630fd030 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/memory.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -11,124 +9,94 @@
},
{
"BriefDescription": "Loads with latency value being above 128.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 16.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 32.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4 .",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 64.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
"PEBS": "2",
- "PRECISE_STORE": "1",
"SampleAfterValue": "2000003",
- "TakenAlone": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"SampleAfterValue": "2000003",
@@ -136,8 +104,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"SampleAfterValue": "2000003",
@@ -145,277 +111,208 @@
},
{
"BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC20077",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400077",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x187FC20077",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f820004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67fc00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f820001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67fc00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f820010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/other.json b/tools/perf/pmu-events/arch/x86/jaketown/other.json
index 2f873ab14156..9f96121baef8 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/other.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
@@ -30,8 +24,6 @@
},
{
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4E",
"EventName": "HW_PRE_REQ.DL1_MISS",
"SampleAfterValue": "2000003",
@@ -39,8 +31,6 @@
},
{
"BriefDescription": "Valid instructions written to IQ per cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x17",
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
"SampleAfterValue": "2000003",
@@ -48,8 +38,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
index 61a3db4d67d5..11d41ce8c922 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB6",
"EventName": "AGU_BYPASS_CANCEL.COUNT",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Divide operations executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Cycles when divider is busy executing divide operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"SampleAfterValue": "2000003",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Speculative and retired branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
@@ -40,8 +32,6 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -49,8 +39,6 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"SampleAfterValue": "200003",
@@ -58,8 +46,6 @@
},
{
"BriefDescription": "Speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -67,8 +53,6 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -76,8 +60,6 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -85,8 +67,6 @@
},
{
"BriefDescription": "Not taken macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -94,8 +74,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -103,8 +81,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"SampleAfterValue": "200003",
@@ -112,8 +88,6 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -121,8 +95,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -130,8 +102,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -139,8 +109,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -148,16 +116,12 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -166,8 +130,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -176,8 +138,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"SampleAfterValue": "100007",
@@ -185,8 +145,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -195,8 +153,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -205,8 +161,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -215,8 +169,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"SampleAfterValue": "400009",
@@ -224,8 +176,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
@@ -233,8 +183,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -242,8 +190,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -251,8 +197,6 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -260,8 +204,6 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -269,8 +211,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -278,8 +218,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -287,8 +225,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -296,8 +232,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -305,8 +239,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"SampleAfterValue": "200003",
@@ -314,27 +246,20 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
- "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
"SampleAfterValue": "400009",
"UMask": "0x4"
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -343,8 +268,6 @@
},
{
"BriefDescription": "Direct and indirect mispredicted near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -353,8 +276,6 @@
},
{
"BriefDescription": "Mispredicted not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NOT_TAKEN",
"PEBS": "1",
@@ -363,8 +284,6 @@
},
{
"BriefDescription": "Mispredicted taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN",
"PEBS": "1",
@@ -373,8 +292,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -382,8 +299,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "2000003",
@@ -392,8 +307,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -401,8 +314,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -410,8 +321,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -419,19 +328,14 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
- "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -439,8 +343,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -449,16 +351,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003"
@@ -466,16 +364,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -484,8 +378,6 @@
},
{
"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -494,8 +386,6 @@
},
{
"BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",
@@ -504,8 +394,6 @@
},
{
"BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -514,8 +402,6 @@
},
{
"BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -524,8 +410,6 @@
},
{
"BriefDescription": "Stall cycles because IQ is full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000003",
@@ -533,8 +417,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000003",
@@ -542,8 +424,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
"SampleAfterValue": "2000003",
@@ -551,27 +431,20 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Instructions retired. (Precise Event - PEBS).",
- "Counter": "1",
- "CounterHTOff": "1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "2",
"SampleAfterValue": "2000003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RAT_STALL_CYCLES",
"SampleAfterValue": "2000003",
@@ -579,8 +452,6 @@
},
{
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -590,8 +461,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -600,8 +469,6 @@
},
{
"BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x0D",
@@ -611,8 +478,6 @@
},
{
"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"SampleAfterValue": "100003",
@@ -620,8 +485,6 @@
},
{
"BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"SampleAfterValue": "100003",
@@ -629,8 +492,6 @@
},
{
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003",
@@ -638,8 +499,6 @@
},
{
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
@@ -648,8 +507,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.",
@@ -658,8 +515,6 @@
},
{
"BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",
"SampleAfterValue": "100003",
@@ -667,8 +522,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"SampleAfterValue": "100003",
@@ -676,8 +529,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"SampleAfterValue": "100003",
@@ -685,8 +536,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -695,8 +544,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -705,8 +552,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
@@ -714,8 +559,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
@@ -725,8 +568,6 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -735,8 +576,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -745,8 +584,6 @@
},
{
"BriefDescription": "Retired instructions experiencing ITLB misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",
"SampleAfterValue": "100003",
@@ -754,8 +591,6 @@
},
{
"BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",
"SampleAfterValue": "2000003",
@@ -763,8 +598,6 @@
},
{
"BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",
@@ -774,8 +607,6 @@
},
{
"BriefDescription": "Multiply packed/scalar single precision uops allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",
"SampleAfterValue": "2000003",
@@ -783,8 +614,6 @@
},
{
"BriefDescription": "Cycles with at least one slow LEA uop being allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",
"PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
@@ -793,8 +622,6 @@
},
{
"BriefDescription": "Resource-related stall cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000003",
@@ -802,8 +629,6 @@
},
{
"BriefDescription": "Counts the cycles of stall due to lack of load buffers.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LB",
"SampleAfterValue": "2000003",
@@ -811,8 +636,6 @@
},
{
"BriefDescription": "Resource stalls due to load or store buffers all being in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LB_SB",
"SampleAfterValue": "2000003",
@@ -820,8 +643,6 @@
},
{
"BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MEM_RS",
"SampleAfterValue": "2000003",
@@ -829,8 +650,6 @@
},
{
"BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OOO_RSRC",
"SampleAfterValue": "2000003",
@@ -838,8 +657,6 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
@@ -847,8 +664,6 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
@@ -856,8 +671,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"SampleAfterValue": "2000003",
@@ -865,8 +678,6 @@
},
{
"BriefDescription": "Cycles with either free list is empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",
"SampleAfterValue": "2000003",
@@ -874,8 +685,6 @@
},
{
"BriefDescription": "Resource stalls2 control structures full for physical registers.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",
"SampleAfterValue": "2000003",
@@ -883,8 +692,6 @@
},
{
"BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.BOB_FULL",
"SampleAfterValue": "2000003",
@@ -892,8 +699,6 @@
},
{
"BriefDescription": "Resource stalls out of order resources full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.OOO_RSRC",
"SampleAfterValue": "2000003",
@@ -901,8 +706,6 @@
},
{
"BriefDescription": "Count cases of saving new LBR.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"SampleAfterValue": "2000003",
@@ -910,8 +713,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"SampleAfterValue": "2000003",
@@ -919,8 +720,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -931,8 +730,6 @@
},
{
"BriefDescription": "Uops dispatched from any thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_DISPATCHED.CORE",
"SampleAfterValue": "2000003",
@@ -940,8 +737,6 @@
},
{
"BriefDescription": "Uops dispatched per thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_DISPATCHED.THREAD",
"SampleAfterValue": "2000003",
@@ -949,8 +744,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"SampleAfterValue": "2000003",
@@ -959,8 +752,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
@@ -968,8 +759,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"SampleAfterValue": "2000003",
@@ -978,8 +767,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
@@ -987,8 +774,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue": "2000003",
@@ -997,8 +782,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -1006,8 +789,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue": "2000003",
@@ -1016,8 +797,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
@@ -1025,8 +804,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue": "2000003",
@@ -1035,8 +812,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
@@ -1044,8 +819,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue": "2000003",
@@ -1054,8 +827,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
@@ -1063,8 +834,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1073,8 +842,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1083,8 +850,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1093,8 +858,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1103,8 +866,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
@@ -1113,8 +874,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
@@ -1124,8 +883,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1135,8 +892,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1146,8 +901,6 @@
},
{
"BriefDescription": "Actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@@ -1157,8 +910,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1168,8 +919,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -1179,8 +928,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1190,8 +937,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json
index 351f8b040ed1..b9e68f9f33ea 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json
@@ -1,23 +1,26 @@
[
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventName": "UNC_C_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CBO"
},
{
"BriefDescription": "Counter 0 Occupancy",
- "Counter": "1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_C_COUNTER0_OCCUPANCY",
"PerPkg": "1",
"PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
"Unit": "CBO"
},
+ {
+ "EventCode": "0x21",
+ "EventName": "UNC_C_ISMQ_DRD_MISS_OCC",
+ "PerPkg": "1",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Cache Lookups; Data Read Request",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
@@ -27,7 +30,6 @@
},
{
"BriefDescription": "Cache Lookups; RTID",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.NID",
"PerPkg": "1",
@@ -37,7 +39,6 @@
},
{
"BriefDescription": "Cache Lookups; External Snoop Request",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
@@ -47,7 +48,6 @@
},
{
"BriefDescription": "Cache Lookups; Write Requests",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
@@ -57,7 +57,6 @@
},
{
"BriefDescription": "Lines Victimized; Lines in E state",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
@@ -67,7 +66,6 @@
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.MISS",
"PerPkg": "1",
@@ -77,7 +75,6 @@
},
{
"BriefDescription": "Lines Victimized; Lines in M state",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
@@ -87,7 +84,6 @@
},
{
"BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.NID",
"PerPkg": "1",
@@ -97,7 +93,6 @@
},
{
"BriefDescription": "Lines Victimized; Lines in S State",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
@@ -107,7 +102,6 @@
},
{
"BriefDescription": "Cbo Misc; RFO HitS",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RFO_HIT_S",
"PerPkg": "1",
@@ -117,7 +111,6 @@
},
{
"BriefDescription": "Cbo Misc; Silent Snoop Eviction",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
@@ -127,7 +120,6 @@
},
{
"BriefDescription": "Cbo Misc",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.STARTED",
"PerPkg": "1",
@@ -137,7 +129,6 @@
},
{
"BriefDescription": "Cbo Misc; Write Combining Aliasing",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.WC_ALIASING",
"PerPkg": "1",
@@ -147,7 +138,6 @@
},
{
"BriefDescription": "AD Ring In Use; Down and Even",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
@@ -157,7 +147,6 @@
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
@@ -167,7 +156,6 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Even",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
@@ -177,7 +165,6 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Odd",
- "Counter": "2,3",
"EventCode": "0x1b",
"EventName": "UNC_C_RING_AD_USED.UP_ODD",
"PerPkg": "1",
@@ -187,7 +174,6 @@
},
{
"BriefDescription": "AK Ring In Use; Down and Even",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
@@ -197,7 +183,6 @@
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
@@ -207,7 +192,6 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Even",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
@@ -217,7 +201,6 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Odd",
- "Counter": "2,3",
"EventCode": "0x1c",
"EventName": "UNC_C_RING_AK_USED.UP_ODD",
"PerPkg": "1",
@@ -227,7 +210,6 @@
},
{
"BriefDescription": "BL Ring in Use; Down and Even",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
@@ -237,7 +219,6 @@
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
@@ -247,7 +228,6 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Even",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
@@ -257,7 +237,6 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Odd",
- "Counter": "2,3",
"EventCode": "0x1d",
"EventName": "UNC_C_RING_BL_USED.UP_ODD",
"PerPkg": "1",
@@ -267,7 +246,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AK_CORE",
"PerPkg": "1",
@@ -276,7 +254,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.BL_CORE",
"PerPkg": "1",
@@ -285,7 +262,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.IV_CORE",
"PerPkg": "1",
@@ -294,7 +270,6 @@
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "2,3",
"EventCode": "0x1e",
"EventName": "UNC_C_RING_IV_USED.ANY",
"PerPkg": "1",
@@ -302,9 +277,42 @@
"UMask": "0xf",
"Unit": "CBO"
},
+ {
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.AD_CACHE",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.AK_CORE",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CBO"
+ },
+ {
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.BL_CORE",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
+ {
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.IV_CORE",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CBO"
+ },
+ {
+ "EventCode": "0x7",
+ "EventName": "UNC_C_RING_SRC_THRTL",
+ "PerPkg": "1",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
"PerPkg": "1",
@@ -314,7 +322,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
"PerPkg": "1",
@@ -324,7 +331,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.ISMQ",
"PerPkg": "1",
@@ -334,7 +340,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
"PerPkg": "1",
@@ -344,7 +349,6 @@
},
{
"BriefDescription": "Ingress Allocations; IPQ",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IPQ",
"PerPkg": "1",
@@ -354,7 +358,6 @@
},
{
"BriefDescription": "Ingress Allocations; IRQ",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ",
"PerPkg": "1",
@@ -364,7 +367,6 @@
},
{
"BriefDescription": "Ingress Allocations; IRQ Rejected",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED",
"PerPkg": "1",
@@ -374,7 +376,6 @@
},
{
"BriefDescription": "Ingress Allocations; VFIFO",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.VFIFO",
"PerPkg": "1",
@@ -384,7 +385,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IPQ",
"PerPkg": "1",
@@ -394,7 +394,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IRQ",
"PerPkg": "1",
@@ -404,7 +403,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
"PerPkg": "1",
@@ -414,7 +412,6 @@
},
{
"BriefDescription": "Probe Queue Retries; Address Conflict",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
@@ -424,7 +421,6 @@
},
{
"BriefDescription": "Probe Queue Retries; Any Reject",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
"PerPkg": "1",
@@ -434,7 +430,6 @@
},
{
"BriefDescription": "Probe Queue Retries; No Egress Credits",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
"PerPkg": "1",
@@ -444,7 +439,6 @@
},
{
"BriefDescription": "Probe Queue Retries; No QPI Credits",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -454,7 +448,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
@@ -463,7 +456,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; Any Reject",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
"PerPkg": "1",
@@ -472,7 +464,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
"PerPkg": "1",
@@ -481,7 +472,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -490,7 +480,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
"PerPkg": "1",
@@ -499,7 +488,6 @@
},
{
"BriefDescription": "ISMQ Retries; Any Reject",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
"PerPkg": "1",
@@ -509,7 +497,6 @@
},
{
"BriefDescription": "ISMQ Retries; No Egress Credits",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
"PerPkg": "1",
@@ -519,7 +506,6 @@
},
{
"BriefDescription": "ISMQ Retries; No IIO Credits",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
@@ -529,7 +515,6 @@
},
{
"BriefDescription": "ISMQ Retries; No QPI Credits",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -539,7 +524,6 @@
},
{
"BriefDescription": "ISMQ Retries; No RTIDs",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
"PerPkg": "1",
@@ -585,7 +569,6 @@
},
{
"BriefDescription": "TOR Inserts; Evictions",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.EVICTION",
"PerPkg": "1",
@@ -595,7 +578,6 @@
},
{
"BriefDescription": "TOR Inserts; Miss All",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_ALL",
"PerPkg": "1",
@@ -605,7 +587,6 @@
},
{
"BriefDescription": "TOR Inserts; Miss Opcode Match",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
"PerPkg": "1",
@@ -615,7 +596,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_ALL",
"PerPkg": "1",
@@ -625,7 +605,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Evictions",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
"PerPkg": "1",
@@ -635,7 +614,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Miss All",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
"PerPkg": "1",
@@ -645,7 +623,6 @@
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
"PerPkg": "1",
@@ -655,7 +632,6 @@
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
"PerPkg": "1",
@@ -665,7 +641,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Writebacks",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_WB",
"PerPkg": "1",
@@ -675,7 +650,6 @@
},
{
"BriefDescription": "TOR Inserts; Opcode Match",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.OPCODE",
"PerPkg": "1",
@@ -685,7 +659,6 @@
},
{
"BriefDescription": "TOR Inserts; Writebacks",
- "Counter": "0,1",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.WB",
"PerPkg": "1",
@@ -783,9 +756,14 @@
"UMask": "0x1",
"Unit": "CBO"
},
+ {
+ "EventCode": "0x4",
+ "EventName": "UNC_C_TxR_ADS_USED",
+ "PerPkg": "1",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Egress Allocations; AD - Cachebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
"PerPkg": "1",
@@ -795,7 +773,6 @@
},
{
"BriefDescription": "Egress Allocations; AD - Corebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CORE",
"PerPkg": "1",
@@ -805,7 +782,6 @@
},
{
"BriefDescription": "Egress Allocations; AK - Cachebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
"PerPkg": "1",
@@ -815,7 +791,6 @@
},
{
"BriefDescription": "Egress Allocations; AK - Corebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CORE",
"PerPkg": "1",
@@ -825,7 +800,6 @@
},
{
"BriefDescription": "Egress Allocations; BL - Cacheno",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
"PerPkg": "1",
@@ -835,7 +809,6 @@
},
{
"BriefDescription": "Egress Allocations; BL - Corebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CORE",
"PerPkg": "1",
@@ -845,7 +818,6 @@
},
{
"BriefDescription": "Egress Allocations; IV - Cachebo",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
"PerPkg": "1",
@@ -855,7 +827,6 @@
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AK",
"PerPkg": "1",
@@ -865,7 +836,6 @@
},
{
"BriefDescription": "Injection Starvation; Onto BL Ring",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.BL",
"PerPkg": "1",
@@ -875,7 +845,6 @@
},
{
"BriefDescription": "HA to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
"PerPkg": "1",
@@ -885,7 +854,6 @@
},
{
"BriefDescription": "HA to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.TAKEN",
"PerPkg": "1",
@@ -895,7 +863,6 @@
},
{
"BriefDescription": "uclks",
- "Counter": "0,1,2,3",
"EventName": "UNC_H_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
@@ -903,7 +870,6 @@
},
{
"BriefDescription": "Conflict Checks; Conflict Detected",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT",
"PerPkg": "1",
@@ -912,7 +878,6 @@
},
{
"BriefDescription": "Conflict Checks; No Conflict",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_H_CONFLICT_CYCLES.NO_CONFLICT",
"PerPkg": "1",
@@ -921,7 +886,6 @@
},
{
"BriefDescription": "Direct2Core Messages Sent",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_H_DIRECT2CORE_COUNT",
"PerPkg": "1",
@@ -930,7 +894,6 @@
},
{
"BriefDescription": "Cycles when Direct2Core was Disabled",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
"PerPkg": "1",
@@ -939,7 +902,6 @@
},
{
"BriefDescription": "Number of Reads that had Direct2Core Overridden",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
@@ -948,7 +910,6 @@
},
{
"BriefDescription": "Directory Lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
"PerPkg": "1",
@@ -958,7 +919,6 @@
},
{
"BriefDescription": "Directory Lookups; Snoop Needed",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
"PerPkg": "1",
@@ -968,7 +928,6 @@
},
{
"BriefDescription": "Directory Updates; Any Directory Update",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
@@ -978,7 +937,6 @@
},
{
"BriefDescription": "Directory Updates; Directory Clear",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
"PerPkg": "1",
@@ -988,7 +946,6 @@
},
{
"BriefDescription": "Directory Updates; Directory Set",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_H_DIRECTORY_UPDATE.SET",
"PerPkg": "1",
@@ -998,7 +955,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
"PerPkg": "1",
@@ -1008,7 +964,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
"PerPkg": "1",
@@ -1018,7 +973,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
"PerPkg": "1",
@@ -1028,7 +982,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
"PerPkg": "1",
@@ -1038,7 +991,6 @@
},
{
"BriefDescription": "Retry Events",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_H_IMC_RETRY",
"PerPkg": "1",
@@ -1046,7 +998,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.ALL",
"PerPkg": "1",
@@ -1056,7 +1007,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.FULL",
"PerPkg": "1",
@@ -1066,7 +1016,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
@@ -1076,7 +1025,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.PARTIAL",
"PerPkg": "1",
@@ -1086,7 +1034,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
@@ -1096,7 +1043,6 @@
},
{
"BriefDescription": "Read and Write Requests; Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
@@ -1106,7 +1052,6 @@
},
{
"BriefDescription": "Read and Write Requests; Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES",
"PerPkg": "1",
@@ -1116,7 +1061,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
@@ -1126,7 +1070,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
@@ -1136,7 +1079,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
@@ -1146,7 +1088,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_H_RING_AD_USED.CW_ODD",
"PerPkg": "1",
@@ -1156,7 +1097,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
@@ -1166,7 +1106,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
@@ -1176,7 +1115,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
@@ -1186,7 +1124,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3f",
"EventName": "UNC_H_RING_AK_USED.CW_ODD",
"PerPkg": "1",
@@ -1196,7 +1133,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
@@ -1206,7 +1142,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
@@ -1216,7 +1151,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
@@ -1226,7 +1160,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_ODD",
"PerPkg": "1",
@@ -1236,7 +1169,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
@@ -1246,7 +1178,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
@@ -1256,7 +1187,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
@@ -1266,7 +1196,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
@@ -1276,7 +1205,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
@@ -1286,7 +1214,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
@@ -1296,7 +1223,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
@@ -1306,7 +1232,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
@@ -1316,7 +1241,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
"PerPkg": "1",
@@ -1326,7 +1250,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
"PerPkg": "1",
@@ -1336,7 +1259,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
"PerPkg": "1",
@@ -1346,7 +1268,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
"PerPkg": "1",
@@ -1356,7 +1277,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
"PerPkg": "1",
@@ -1366,7 +1286,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
"PerPkg": "1",
@@ -1376,7 +1295,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
"PerPkg": "1",
@@ -1386,7 +1304,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
"PerPkg": "1",
@@ -1396,7 +1313,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
"PerPkg": "1",
@@ -1406,7 +1322,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
"PerPkg": "1",
@@ -1416,7 +1331,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
"PerPkg": "1",
@@ -1426,7 +1340,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
"PerPkg": "1",
@@ -1436,7 +1349,6 @@
},
{
"BriefDescription": "Tracker Allocations; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_H_TRACKER_INSERTS.ALL",
"PerPkg": "1",
@@ -1446,7 +1358,6 @@
},
{
"BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
- "Counter": "0,1,2,3",
"EventCode": "0xf",
"EventName": "UNC_H_TxR_AD.NDR",
"PerPkg": "1",
@@ -1456,7 +1367,6 @@
},
{
"BriefDescription": "Outbound NDR Ring Transactions; Snoops",
- "Counter": "0,1,2,3",
"EventCode": "0xf",
"EventName": "UNC_H_TxR_AD.SNP",
"PerPkg": "1",
@@ -1466,217 +1376,174 @@
},
{
"BriefDescription": "AD Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
"PerPkg": "1",
- "PublicDescription": "AD Egress Full",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
"PerPkg": "1",
- "PublicDescription": "AD Egress Full",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
"PerPkg": "1",
- "PublicDescription": "AD Egress Full",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
"PerPkg": "1",
- "PublicDescription": "AD Egress Not Empty",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
"PerPkg": "1",
- "PublicDescription": "AD Egress Not Empty",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
"PerPkg": "1",
- "PublicDescription": "AD Egress Not Empty",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.ALL",
"PerPkg": "1",
- "PublicDescription": "AD Egress Allocations",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
"PerPkg": "1",
- "PublicDescription": "AD Egress Allocations",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
"PerPkg": "1",
- "PublicDescription": "AD Egress Allocations",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Occupancy; All",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_H_TxR_AD_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "AD Egress Occupancy",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Occupancy; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0",
"PerPkg": "1",
- "PublicDescription": "AD Egress Occupancy",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Occupancy; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1",
"PerPkg": "1",
- "PublicDescription": "AD Egress Occupancy",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
- "PublicDescription": "AK Egress Full",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
"PerPkg": "1",
- "PublicDescription": "AK Egress Full",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
"PerPkg": "1",
- "PublicDescription": "AK Egress Full",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
"PerPkg": "1",
- "PublicDescription": "AK Egress Not Empty",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
"PerPkg": "1",
- "PublicDescription": "AK Egress Not Empty",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
"PerPkg": "1",
- "PublicDescription": "AK Egress Not Empty",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_H_TxR_AK_INSERTS.ALL",
"PerPkg": "1",
- "PublicDescription": "AK Egress Allocations",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
"PerPkg": "1",
- "PublicDescription": "AK Egress Allocations",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
"PerPkg": "1",
- "PublicDescription": "AK Egress Allocations",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Outbound NDR Ring Transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xe",
"EventName": "UNC_H_TxR_AK_NDR",
"PerPkg": "1",
@@ -1685,37 +1552,30 @@
},
{
"BriefDescription": "AK Egress Occupancy; All",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_H_TxR_AK_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "AK Egress Occupancy",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Occupancy; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0",
"PerPkg": "1",
- "PublicDescription": "AK Egress Occupancy",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Occupancy; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1",
"PerPkg": "1",
- "PublicDescription": "AK Egress Occupancy",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CACHE",
"PerPkg": "1",
@@ -1725,7 +1585,6 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CORE",
"PerPkg": "1",
@@ -1735,7 +1594,6 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_QPI",
"PerPkg": "1",
@@ -1745,127 +1603,102 @@
},
{
"BriefDescription": "BL Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
"PerPkg": "1",
- "PublicDescription": "BL Egress Full",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
"PerPkg": "1",
- "PublicDescription": "BL Egress Full",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
"PerPkg": "1",
- "PublicDescription": "BL Egress Full",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
"PerPkg": "1",
- "PublicDescription": "BL Egress Not Empty",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
"PerPkg": "1",
- "PublicDescription": "BL Egress Not Empty",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
"PerPkg": "1",
- "PublicDescription": "BL Egress Not Empty",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.ALL",
"PerPkg": "1",
- "PublicDescription": "BL Egress Allocations",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
"PerPkg": "1",
- "PublicDescription": "BL Egress Allocations",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
"PerPkg": "1",
- "PublicDescription": "BL Egress Allocations",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Occupancy; All",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "BL Egress Occupancy",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Occupancy; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0",
"PerPkg": "1",
- "PublicDescription": "BL Egress Occupancy",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Occupancy; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1",
"PerPkg": "1",
- "PublicDescription": "BL Egress Occupancy",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
@@ -1875,7 +1708,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
@@ -1885,7 +1717,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
@@ -1895,7 +1726,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
@@ -1905,7 +1735,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
@@ -1915,7 +1744,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
@@ -1925,7 +1753,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
@@ -1935,7 +1762,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json
index 750870fd1cb1..1c2cf94889a1 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Number of qfclks",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_CLOCKTICKS",
"PerPkg": "1",
@@ -10,17 +9,14 @@
},
{
"BriefDescription": "Count of CTO Events",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_Q_CTO_COUNT",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
"PerPkg": "1",
@@ -30,7 +26,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
"PerPkg": "1",
@@ -40,7 +35,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Not Set",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT",
"PerPkg": "1",
@@ -50,7 +44,6 @@
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Success",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.SUCCESS",
"PerPkg": "1",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "Cycles in L1",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_L1_POWER_CYCLES",
"PerPkg": "1",
@@ -69,7 +61,6 @@
},
{
"BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL0P_POWER_CYCLES",
"PerPkg": "1",
@@ -78,7 +69,6 @@
},
{
"BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
"EventCode": "0xf",
"EventName": "UNC_Q_RxL0_POWER_CYCLES",
"PerPkg": "1",
@@ -87,7 +77,6 @@
},
{
"BriefDescription": "Rx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_BYPASSED",
"PerPkg": "1",
@@ -96,7 +85,6 @@
},
{
"BriefDescription": "CRC Errors Detected; LinkInit",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
"PerPkg": "1",
@@ -106,7 +94,6 @@
},
{
"BriefDescription": "CRC Errors Detected; Normal Operations",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
"PerPkg": "1",
@@ -116,10 +103,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"UMask": "0x1",
@@ -127,10 +112,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"UMask": "0x8",
@@ -138,10 +121,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"UMask": "0x2",
@@ -149,10 +130,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"UMask": "0x4",
@@ -160,10 +139,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"UMask": "0x20",
@@ -171,10 +148,8 @@
},
{
"BriefDescription": "VN0 Credit Consumed; SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"UMask": "0x10",
@@ -182,17 +157,14 @@
},
{
"BriefDescription": "VNA Credit Consumed",
- "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_Q_RxL_CYCLES_NE",
"PerPkg": "1",
@@ -201,7 +173,6 @@
},
{
"BriefDescription": "Flits Received - Group 0; Data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.DATA",
"PerPkg": "1",
@@ -211,7 +182,6 @@
},
{
"BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
"PerPkg": "1",
@@ -221,7 +191,6 @@
},
{
"BriefDescription": "Flits Received - Group 0; Non-Data protocol Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
@@ -231,10 +200,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x18",
@@ -242,10 +209,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x8",
@@ -253,10 +218,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x10",
@@ -264,10 +227,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x6",
@@ -275,10 +236,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x4",
@@ -286,10 +245,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x2",
@@ -297,10 +254,8 @@
},
{
"BriefDescription": "Flits Received - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x1",
@@ -308,10 +263,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0xc",
@@ -319,10 +272,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x4",
@@ -330,10 +281,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x8",
@@ -341,10 +290,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x10",
@@ -352,10 +299,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x1",
@@ -363,10 +308,8 @@
},
{
"BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x2",
@@ -374,7 +317,6 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_Q_RxL_INSERTS",
"PerPkg": "1",
@@ -383,67 +325,54 @@
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_Q_RxL_INSERTS_HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_Q_RxL_INSERTS_NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_Q_RxL_INSERTS_NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0xe",
"EventName": "UNC_Q_RxL_INSERTS_NDR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_Q_RxL_INSERTS_SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - All Packets",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_Q_RxL_OCCUPANCY",
"PerPkg": "1",
@@ -452,67 +381,54 @@
},
{
"BriefDescription": "RxQ Occupancy - DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_DRS",
"PerPkg": "1",
@@ -522,7 +438,6 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_HOM",
"PerPkg": "1",
@@ -532,7 +447,6 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_NCB",
"PerPkg": "1",
@@ -542,7 +456,6 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_NCS",
"PerPkg": "1",
@@ -552,7 +465,6 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_NDR",
"PerPkg": "1",
@@ -562,7 +474,6 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.BGF_SNP",
"PerPkg": "1",
@@ -572,7 +483,6 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.EGRESS_CREDITS",
"PerPkg": "1",
@@ -582,7 +492,6 @@
},
{
"BriefDescription": "Stalls Sending to R3QPI; GV",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS.GV",
"PerPkg": "1",
@@ -592,7 +501,6 @@
},
{
"BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_Q_TxL0P_POWER_CYCLES",
"PerPkg": "1",
@@ -601,7 +509,6 @@
},
{
"BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_Q_TxL0_POWER_CYCLES",
"PerPkg": "1",
@@ -610,7 +517,6 @@
},
{
"BriefDescription": "Tx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_Q_TxL_BYPASSED",
"PerPkg": "1",
@@ -619,7 +525,6 @@
},
{
"BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
"PerPkg": "1",
@@ -629,7 +534,6 @@
},
{
"BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
"PerPkg": "1",
@@ -639,7 +543,6 @@
},
{
"BriefDescription": "Tx Flit Buffer Cycles not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_Q_TxL_CYCLES_NE",
"PerPkg": "1",
@@ -648,7 +551,6 @@
},
{
"BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.DATA",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
@@ -657,7 +559,6 @@
},
{
"BriefDescription": "Flits Transferred - Group 0; Idle and Null Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.IDLE",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
@@ -666,7 +567,6 @@
},
{
"BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
@@ -675,9 +575,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x18",
@@ -685,9 +583,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x8",
@@ -695,9 +591,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x10",
@@ -705,9 +599,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x6",
@@ -715,9 +607,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x4",
@@ -725,9 +615,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x2",
@@ -735,9 +623,7 @@
},
{
"BriefDescription": "Flits Transferred - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.SNP",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x1",
@@ -745,10 +631,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0xc",
@@ -756,10 +640,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x4",
@@ -767,10 +649,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x8",
@@ -778,10 +658,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x10",
@@ -789,10 +667,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x1",
@@ -800,10 +676,8 @@
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
"UMask": "0x2",
@@ -811,7 +685,6 @@
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_Q_TxL_INSERTS",
"PerPkg": "1",
@@ -820,7 +693,6 @@
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_Q_TxL_OCCUPANCY",
"PerPkg": "1",
@@ -829,20 +701,16 @@
},
{
"BriefDescription": "VNA Credits Returned",
- "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_Q_VNA_CREDIT_RETURNS",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of VNA credits returned.",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
"Unit": "QPI LL"
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
index a165a77947a0..2faf0dc6675d 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "DRAM Activate Count",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT",
"PerPkg": "1",
@@ -10,77 +9,62 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "uclks",
- "Counter": "0,1,2,3",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Uncore Fixed Counter - uclks",
@@ -88,7 +72,6 @@
},
{
"BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
@@ -97,7 +80,6 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
@@ -107,7 +89,6 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
@@ -117,7 +98,6 @@
},
{
"BriefDescription": "ECC Correctable Errors",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
@@ -126,7 +106,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
@@ -136,7 +115,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
@@ -146,7 +124,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Read Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
@@ -156,7 +133,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Write Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
@@ -166,7 +142,6 @@
},
{
"BriefDescription": "Channel DLLOFF Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
@@ -175,7 +150,6 @@
},
{
"BriefDescription": "Channel PPD Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
@@ -184,7 +158,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
@@ -194,7 +167,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
@@ -204,7 +176,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
@@ -214,7 +185,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
@@ -224,7 +194,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
@@ -234,7 +203,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
@@ -244,7 +212,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
@@ -254,7 +221,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
@@ -264,7 +230,6 @@
},
{
"BriefDescription": "Critical Throttle Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
@@ -273,7 +238,6 @@
},
{
"BriefDescription": "Clock-Enabled Self-Refresh",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
@@ -282,7 +246,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
@@ -292,7 +255,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
@@ -302,7 +264,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
@@ -312,7 +273,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
@@ -322,7 +282,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
@@ -332,7 +291,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
@@ -342,7 +300,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
@@ -352,7 +309,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
@@ -362,7 +318,6 @@
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
@@ -372,7 +327,6 @@
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
@@ -382,7 +336,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
@@ -392,7 +345,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
"PerPkg": "1",
@@ -402,7 +354,6 @@
},
{
"BriefDescription": "Read Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M_RPQ_CYCLES_FULL",
"PerPkg": "1",
@@ -411,7 +362,6 @@
},
{
"BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
@@ -420,7 +370,6 @@
},
{
"BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
@@ -429,7 +378,6 @@
},
{
"BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M_RPQ_OCCUPANCY",
"PerPkg": "1",
@@ -438,7 +386,6 @@
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
@@ -447,7 +394,6 @@
},
{
"BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
@@ -456,7 +402,6 @@
},
{
"BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M_WPQ_INSERTS",
"PerPkg": "1",
@@ -465,7 +410,6 @@
},
{
"BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M_WPQ_OCCUPANCY",
"PerPkg": "1",
@@ -474,7 +418,6 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
@@ -483,7 +426,6 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json
index 588549a668bd..51a9a4e81046 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Address Match (Conflict) Count; Conflict Merges",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT",
"PerPkg": "1",
@@ -11,7 +10,6 @@
},
{
"BriefDescription": "Address Match (Conflict) Count; Conflict Stalls",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT",
"PerPkg": "1",
@@ -21,7 +19,6 @@
},
{
"BriefDescription": "Write Ack Pending Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -31,7 +28,6 @@
},
{
"BriefDescription": "Write Ack Pending Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -41,7 +37,6 @@
},
{
"BriefDescription": "Outstanding Write Ownership Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -51,7 +46,6 @@
},
{
"BriefDescription": "Outstanding Write Ownership Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -61,7 +55,6 @@
},
{
"BriefDescription": "Outstanding Read Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -71,7 +64,6 @@
},
{
"BriefDescription": "Outstanding Read Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -81,7 +73,6 @@
},
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -91,7 +82,6 @@
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -101,7 +91,6 @@
},
{
"BriefDescription": "Outstanding Write Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -111,7 +100,6 @@
},
{
"BriefDescription": "Outstanding Write Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -121,14 +109,12 @@
},
{
"BriefDescription": "Clocks in the IRP",
- "Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Number of clocks in the IRP.",
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0xB",
"EventName": "UNC_I_RxR_AK_CYCLES_FULL",
"PerPkg": "1",
@@ -137,7 +123,6 @@
},
{
"BriefDescription": "AK Ingress Occupancy",
- "Counter": "0,1",
"EventCode": "0xA",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
@@ -145,7 +130,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0xC",
"EventName": "UNC_I_RxR_AK_OCCUPANCY",
"PerPkg": "1",
@@ -153,7 +137,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
@@ -162,7 +145,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
- "Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
@@ -170,7 +152,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
@@ -178,7 +159,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
@@ -187,7 +167,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
@@ -195,7 +174,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
@@ -203,7 +181,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
@@ -212,7 +189,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
@@ -220,7 +196,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
@@ -229,7 +204,6 @@
},
{
"BriefDescription": "Tickle Count; Ownership Lost",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TICKLES.LOST_OWNERSHIP",
"PerPkg": "1",
@@ -239,7 +213,6 @@
},
{
"BriefDescription": "Tickle Count; Data Returned",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TICKLES.TOP_OF_QUEUE",
"PerPkg": "1",
@@ -249,7 +222,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES",
"PerPkg": "1",
@@ -259,7 +231,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Reads",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
@@ -269,7 +240,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Writes",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
@@ -279,7 +249,6 @@
},
{
"BriefDescription": "No AD Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@@ -288,7 +257,6 @@
},
{
"BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@@ -297,7 +265,6 @@
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xE",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
@@ -306,7 +273,6 @@
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xF",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
@@ -315,7 +281,6 @@
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
@@ -324,7 +289,6 @@
},
{
"BriefDescription": "Write Ordering Stalls",
- "Counter": "0,1",
"EventCode": "0x1A",
"EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES",
"PerPkg": "1",
@@ -333,7 +297,6 @@
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
@@ -342,7 +305,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
@@ -352,7 +314,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
@@ -362,7 +323,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
@@ -372,7 +332,6 @@
},
{
"BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -382,7 +341,6 @@
},
{
"BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCB",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R2_IIO_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -392,7 +350,6 @@
},
{
"BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCS",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R2_IIO_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -402,7 +359,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; DRS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -412,7 +368,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCB",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -422,7 +377,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -432,7 +386,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
@@ -442,7 +395,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
@@ -452,7 +404,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
@@ -462,7 +413,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_ODD",
"PerPkg": "1",
@@ -472,7 +422,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
@@ -482,7 +431,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
@@ -492,7 +440,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
@@ -502,7 +449,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_ODD",
"PerPkg": "1",
@@ -512,7 +458,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
@@ -522,7 +467,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
@@ -532,7 +476,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
@@ -542,7 +485,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_ODD",
"PerPkg": "1",
@@ -552,7 +494,6 @@
},
{
"BriefDescription": "R2 IV Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
@@ -570,7 +511,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; DRS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.DRS",
"PerPkg": "1",
@@ -580,7 +520,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
@@ -590,7 +529,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
@@ -654,7 +592,6 @@
},
{
"BriefDescription": "Egress NACK; AD",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACKS.AD",
"PerPkg": "1",
@@ -664,7 +601,6 @@
},
{
"BriefDescription": "Egress NACK; AK",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACKS.AK",
"PerPkg": "1",
@@ -674,7 +610,6 @@
},
{
"BriefDescription": "Egress NACK; BL",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACKS.BL",
"PerPkg": "1",
@@ -684,7 +619,6 @@
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2",
"EventCode": "0x1",
"EventName": "UNC_R3_CLOCKTICKS",
"PerPkg": "1",
@@ -693,7 +627,6 @@
},
{
"BriefDescription": "to IIO BL Credit Acquired",
- "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
@@ -703,7 +636,6 @@
},
{
"BriefDescription": "to IIO BL Credit Acquired",
- "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
@@ -713,7 +645,6 @@
},
{
"BriefDescription": "to IIO BL Credit Acquired",
- "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
@@ -723,7 +654,6 @@
},
{
"BriefDescription": "to IIO BL Credit Rejected",
- "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_IIO_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -733,7 +663,6 @@
},
{
"BriefDescription": "to IIO BL Credit Rejected",
- "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_IIO_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -743,7 +672,6 @@
},
{
"BriefDescription": "to IIO BL Credit Rejected",
- "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_IIO_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -753,7 +681,6 @@
},
{
"BriefDescription": "to IIO BL Credit In Use",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -763,7 +690,6 @@
},
{
"BriefDescription": "to IIO BL Credit In Use",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -773,7 +699,6 @@
},
{
"BriefDescription": "to IIO BL Credit In Use",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -783,7 +708,6 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
@@ -793,7 +717,6 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
@@ -803,7 +726,6 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
@@ -813,7 +735,6 @@
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW_ODD",
"PerPkg": "1",
@@ -823,7 +744,6 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
@@ -833,7 +753,6 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
@@ -843,7 +762,6 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
@@ -853,7 +771,6 @@
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW_ODD",
"PerPkg": "1",
@@ -863,7 +780,6 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
@@ -873,7 +789,6 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
@@ -883,7 +798,6 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
@@ -893,7 +807,6 @@
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW_ODD",
"PerPkg": "1",
@@ -903,7 +816,6 @@
},
{
"BriefDescription": "R3 IV Ring in Use; Any",
- "Counter": "0,1,2",
"EventCode": "0xa",
"EventName": "UNC_R3_RING_IV_USED.ANY",
"PerPkg": "1",
@@ -913,7 +825,6 @@
},
{
"BriefDescription": "Ingress Bypassed",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_R3_RxR_BYPASSED.AD",
"PerPkg": "1",
@@ -923,7 +834,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; DRS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.DRS",
"PerPkg": "1",
@@ -933,7 +843,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; HOM",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
"PerPkg": "1",
@@ -943,7 +852,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
@@ -953,7 +861,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
@@ -963,7 +870,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NDR",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
"PerPkg": "1",
@@ -973,7 +879,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; SNP",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
"PerPkg": "1",
@@ -983,7 +888,6 @@
},
{
"BriefDescription": "Ingress Allocations; DRS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.DRS",
"PerPkg": "1",
@@ -993,7 +897,6 @@
},
{
"BriefDescription": "Ingress Allocations; HOM",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.HOM",
"PerPkg": "1",
@@ -1003,7 +906,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCB",
"PerPkg": "1",
@@ -1013,7 +915,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCS",
"PerPkg": "1",
@@ -1023,7 +924,6 @@
},
{
"BriefDescription": "Ingress Allocations; NDR",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NDR",
"PerPkg": "1",
@@ -1033,7 +933,6 @@
},
{
"BriefDescription": "Ingress Allocations; SNP",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.SNP",
"PerPkg": "1",
@@ -1097,7 +996,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -1107,7 +1005,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
"PerPkg": "1",
@@ -1117,7 +1014,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -1127,7 +1023,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -1137,7 +1032,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
"PerPkg": "1",
@@ -1147,7 +1041,6 @@
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
"PerPkg": "1",
@@ -1157,7 +1050,6 @@
},
{
"BriefDescription": "VN0 Credit Used; DRS Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -1167,7 +1059,6 @@
},
{
"BriefDescription": "VN0 Credit Used; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
"PerPkg": "1",
@@ -1177,7 +1068,6 @@
},
{
"BriefDescription": "VN0 Credit Used; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -1187,7 +1077,6 @@
},
{
"BriefDescription": "VN0 Credit Used; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -1197,7 +1086,6 @@
},
{
"BriefDescription": "VN0 Credit Used; NDR Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
"PerPkg": "1",
@@ -1207,7 +1095,6 @@
},
{
"BriefDescription": "VN0 Credit Used; SNP Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
@@ -1217,7 +1104,6 @@
},
{
"BriefDescription": "VNA credit Acquisitions",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED",
"PerPkg": "1",
@@ -1226,7 +1112,6 @@
},
{
"BriefDescription": "VNA Credit Reject; DRS Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
"PerPkg": "1",
@@ -1236,7 +1121,6 @@
},
{
"BriefDescription": "VNA Credit Reject; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
"PerPkg": "1",
@@ -1246,7 +1130,6 @@
},
{
"BriefDescription": "VNA Credit Reject; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
"PerPkg": "1",
@@ -1256,7 +1139,6 @@
},
{
"BriefDescription": "VNA Credit Reject; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
"PerPkg": "1",
@@ -1266,7 +1148,6 @@
},
{
"BriefDescription": "VNA Credit Reject; NDR Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
"PerPkg": "1",
@@ -1276,7 +1157,6 @@
},
{
"BriefDescription": "VNA Credit Reject; SNP Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
"PerPkg": "1",
@@ -1286,7 +1166,6 @@
},
{
"BriefDescription": "Cycles with no VNA credits available",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT",
"PerPkg": "1",
@@ -1295,16 +1174,19 @@
},
{
"BriefDescription": "Cycles with 1 or more VNA credits in use",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED",
"PerPkg": "1",
"PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.",
"Unit": "R3QPI"
},
+ {
+ "EventName": "UNC_U_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "UBOX"
+ },
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
@@ -1314,7 +1196,6 @@
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.INT_PRIO",
"PerPkg": "1",
@@ -1324,7 +1205,6 @@
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
"PerPkg": "1",
@@ -1334,7 +1214,6 @@
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
"PerPkg": "1",
@@ -1344,7 +1223,6 @@
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
"PerPkg": "1",
@@ -1354,7 +1232,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
@@ -1364,7 +1241,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
@@ -1374,7 +1250,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
@@ -1384,7 +1259,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
@@ -1394,7 +1268,6 @@
},
{
"BriefDescription": "IDI Lock/SplitLock Cycles",
- "Counter": "0,1",
"EventCode": "0x44",
"EventName": "UNC_U_LOCK_CYCLES",
"PerPkg": "1",
@@ -1403,10 +1276,8 @@
},
{
"BriefDescription": "MsgCh Requests by Size; 4B Requests",
- "Counter": "0,1",
"EventCode": "0x47",
"EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.4B",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of transactions on the message channel filtered by request size. This includes both reads and writes.",
"UMask": "0x1",
@@ -1414,10 +1285,8 @@
},
{
"BriefDescription": "MsgCh Requests by Size; 8B Requests",
- "Counter": "0,1",
"EventCode": "0x47",
"EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.8B",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of transactions on the message channel filtered by request size. This includes both reads and writes.",
"UMask": "0x2",
@@ -1425,10 +1294,8 @@
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; ACK to Deassert",
- "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "PHOLD cycles. Filter from source CoreID.",
"UMask": "0x2",
@@ -1436,10 +1303,8 @@
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
- "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "PHOLD cycles. Filter from source CoreID.",
"UMask": "0x1",
@@ -1447,17 +1312,14 @@
},
{
"BriefDescription": "RACU Request",
- "Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS.COUNT",
- "ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
@@ -1467,7 +1329,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
@@ -1477,7 +1338,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
@@ -1487,7 +1347,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T0",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
@@ -1497,7 +1356,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T1",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
@@ -1507,7 +1365,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Other",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
@@ -1517,7 +1374,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Trap",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
@@ -1527,7 +1383,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json
index 817ea6d7f785..638aa8a35cdb 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "pclk Cycles",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
@@ -9,87 +8,70 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
@@ -98,7 +80,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x1f",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
@@ -107,7 +88,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
@@ -116,7 +96,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
@@ -125,7 +104,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
@@ -134,7 +112,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
@@ -143,7 +120,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
@@ -152,7 +128,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
@@ -161,7 +136,6 @@
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_P_FREQ_BAND0_CYCLES",
"PerPkg": "1",
@@ -170,7 +144,6 @@
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xc",
"EventName": "UNC_P_FREQ_BAND1_CYCLES",
"PerPkg": "1",
@@ -179,7 +152,6 @@
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_P_FREQ_BAND2_CYCLES",
"PerPkg": "1",
@@ -188,7 +160,6 @@
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xe",
"EventName": "UNC_P_FREQ_BAND3_CYCLES",
"PerPkg": "1",
@@ -197,7 +168,6 @@
},
{
"BriefDescription": "Current Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES",
"PerPkg": "1",
@@ -206,7 +176,6 @@
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
@@ -215,7 +184,6 @@
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
@@ -224,7 +192,6 @@
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
@@ -233,36 +200,29 @@
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Perf P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower. Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down. This is largely to minimize increases in snoop and remote read latencies.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
@@ -271,7 +231,6 @@
},
{
"BriefDescription": "Number of cores in C0",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
@@ -280,7 +239,6 @@
},
{
"BriefDescription": "Number of cores in C0",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
@@ -289,7 +247,6 @@
},
{
"BriefDescription": "Number of cores in C0",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
@@ -298,7 +255,6 @@
},
{
"BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0xa",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
@@ -307,7 +263,6 @@
},
{
"BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
@@ -316,17 +271,14 @@
},
{
"BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xb",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
- "ExtSel": "1",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles Changing Voltage",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE",
"PerPkg": "1",
@@ -335,7 +287,6 @@
},
{
"BriefDescription": "Cycles Decreasing Voltage",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE",
"PerPkg": "1",
@@ -344,7 +295,6 @@
},
{
"BriefDescription": "Cycles Increasing Voltage",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE",
"PerPkg": "1",
@@ -353,7 +303,6 @@
},
{
"BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
index 98362abba1a7..fa08d355b97e 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
@@ -39,8 +31,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
@@ -48,8 +38,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -57,8 +45,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -66,8 +52,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
@@ -75,8 +59,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
@@ -84,8 +66,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"SampleAfterValue": "100007",
@@ -93,8 +73,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
@@ -102,8 +80,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -111,8 +87,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -120,8 +94,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
@@ -130,8 +102,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"SampleAfterValue": "100007",
@@ -139,8 +109,6 @@
},
{
"BriefDescription": "STLB flush attempts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"SampleAfterValue": "100007",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 19/32] perf vendor events intel: Refresh knightslanding events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (8 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 18/32] perf vendor events intel: Refresh jaketown " Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 20/32] perf vendor events intel: Refresh meteorlake events Ian Rogers
` (12 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the knightslanding events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/knightslanding/cache.json | 411 -------
.../x86/knightslanding/floating-point.json | 3 -
.../arch/x86/knightslanding/frontend.json | 7 -
.../arch/x86/knightslanding/memory.json | 201 ----
.../arch/x86/knightslanding/pipeline.json | 44 -
.../arch/x86/knightslanding/uncore-other.json | 1040 +++++------------
.../x86/knightslanding/virtual-memory.json | 7 -
7 files changed, 299 insertions(+), 1414 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json
index 5e10eabda300..01aea3d2832e 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json
@@ -1,14 +1,12 @@
[
{
"BriefDescription": "Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path.",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ALL",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses.",
- "Counter": "0,1",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
"PublicDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Counts the number of L2 cache misses",
- "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_REQUESTS.MISS",
"SampleAfterValue": "200003",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "Counts the total number of L2 cache references.",
- "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_REQUESTS.REFERENCE",
"SampleAfterValue": "200003",
@@ -33,14 +29,12 @@
},
{
"BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times",
- "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REQUESTS_REJECT.ALL",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts all the load micro-ops retired",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PublicDescription": "This event counts the number of load micro-ops retired.",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "Counts all the store micro-ops retired",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PublicDescription": "This event counts the number of store micro-ops retired.",
@@ -58,7 +51,6 @@
},
{
"BriefDescription": "Counts the loads retired that get the data from the other core in the same tile in M state",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.HITM",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS",
"PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.",
@@ -77,7 +68,6 @@
},
{
"BriefDescription": "Counts the number of load micro-ops retired that hit in the L2",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS",
@@ -87,7 +77,6 @@
},
{
"BriefDescription": "Counts the number of load micro-ops retired that miss in the L2",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS",
@@ -97,7 +86,6 @@
},
{
"BriefDescription": "Counts the number of load micro-ops retired that caused micro TLB miss",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.UTLB_MISS_LOADS",
"SampleAfterValue": "200003",
@@ -105,7 +93,6 @@
},
{
"BriefDescription": "Counts the matrix events specified by MSR_OFFCORE_RESPx",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100007",
@@ -113,2190 +100,1792 @@
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000013091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800403091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800403091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000403091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800183091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800083091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000083091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00000132f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18004032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x08004032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18001832f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x08000832f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10000832f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00040032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00100032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00020032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00080032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x40000032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000018000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800408000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800408000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000408000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800188000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800088000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000088000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010800",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a7",
"MSRValue": "0x0000014000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.ANY_RESPONSE",
"MSRIndex": "0x1a7",
"MSRValue": "0x0000010100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a7",
"MSRValue": "0x1800400100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a7",
"MSRValue": "0x0800400100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a7",
"MSRValue": "0x1000400100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a7",
"MSRValue": "0x1800180100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a7",
"MSRValue": "0x0800080100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a7",
"MSRValue": "0x1000080100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a7",
"MSRValue": "0x0004000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a7",
"MSRValue": "0x0010000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a7",
"MSRValue": "0x0002000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a7",
"MSRValue": "0x0008000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000012000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800402000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800402000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000402000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800182000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800082000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000082000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000020020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000011000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800401000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800401000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000401000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800181000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800081000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000081000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a7",
"MSRValue": "0x0000014800",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json
index ff5db600e420..ecc96f32f167 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of floating operations retired that required microcode assists",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.PACKED_SIMD",
"PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
@@ -19,7 +17,6 @@
},
{
"BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.SCALAR_SIMD",
"PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.",
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json
index 63343a0d1e86..9001f5019848 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.",
- "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.ALL",
"SampleAfterValue": "200003",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.",
- "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.COND",
"SampleAfterValue": "200003",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.",
- "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.RETURN",
"SampleAfterValue": "200003",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "Counts all instruction fetches, including uncacheable fetches.",
- "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200003",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "Counts all instruction fetches that hit the instruction cache.",
- "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200003",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
- "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200003",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "Counts the number of times the MSROM starts a flow of uops.",
- "Counter": "0,1",
"EventCode": "0xE7",
"EventName": "MS_DECODED.MS_ENTRY",
"SampleAfterValue": "200003",
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
index 2611defaeaa2..b0361f6f0dd9 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "200003",
@@ -9,1101 +8,901 @@
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181803091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080803091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180603091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100403091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080203091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01818032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01010032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00808032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01806032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01004032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00802032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181808000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080808000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180608000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100408000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080208000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000020080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0101000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0080800100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM",
"MSRIndex": "0x1a7",
"MSRValue": "0x0180600100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0100400100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0080200100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181802000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080802000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100402000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080202000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000020020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181801000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080801000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180601000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100401000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080201000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json
index 1f13bc2686cb..1b803fa38641 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Counts the number of near CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CALL",
"PEBS": "1",
@@ -18,7 +16,6 @@
},
{
"BriefDescription": "Counts the number of far branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
@@ -27,7 +24,6 @@
},
{
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "1",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.JCC",
"PEBS": "1",
@@ -45,7 +40,6 @@
},
{
"BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PEBS": "1",
@@ -54,7 +48,6 @@
},
{
"BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "1",
@@ -63,7 +56,6 @@
},
{
"BriefDescription": "Counts the number of near RET branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.RETURN",
"PEBS": "1",
@@ -72,7 +64,6 @@
},
{
"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PEBS": "1",
@@ -81,7 +72,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -89,7 +79,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CALL",
"PEBS": "1",
@@ -98,7 +87,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted far branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.FAR_BRANCH",
"PEBS": "1",
@@ -107,7 +95,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PEBS": "1",
@@ -116,7 +103,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.JCC",
"PEBS": "1",
@@ -125,7 +111,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS": "1",
@@ -134,7 +119,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.REL_CALL",
"PEBS": "1",
@@ -143,7 +127,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "1",
@@ -152,7 +135,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PEBS": "1",
@@ -161,7 +143,6 @@
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles",
- "Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000003",
@@ -169,14 +150,12 @@
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
- "Counter": "Fixed counter 3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter",
"SampleAfterValue": "2000003",
@@ -184,14 +163,12 @@
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles",
- "Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider.",
- "Counter": "0,1",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.ALL",
"PublicDescription": "This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides.",
@@ -200,7 +177,6 @@
},
{
"BriefDescription": "Fixed Counter: Counts the number of instructions retired",
- "Counter": "Fixed counter 1",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.",
"SampleAfterValue": "2000003",
@@ -208,14 +184,12 @@
},
{
"BriefDescription": "Counts the total number of instructions retired",
- "Counter": "0,1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts all nukes",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.ALL",
"SampleAfterValue": "200003",
@@ -223,7 +197,6 @@
},
{
"BriefDescription": "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "200003",
@@ -231,7 +204,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for any reason.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.ALL",
"SampleAfterValue": "200003",
@@ -239,7 +211,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.MISPREDICTS",
"PublicDescription": "This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.",
@@ -248,7 +219,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED",
"PublicDescription": "This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched.",
@@ -257,7 +227,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.RAT_STALL",
"SampleAfterValue": "200003",
@@ -265,7 +234,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB is full",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.ROB_FULL",
"SampleAfterValue": "200003",
@@ -273,7 +241,6 @@
},
{
"BriefDescription": "Counts any retired load that was pushed into the recycle queue for any reason.",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.ANY_LD",
"SampleAfterValue": "200003",
@@ -281,7 +248,6 @@
},
{
"BriefDescription": "Counts any retired store that was pushed into the recycle queue for any reason.",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.ANY_ST",
"SampleAfterValue": "200003",
@@ -289,7 +255,6 @@
},
{
"BriefDescription": "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY",
"SampleAfterValue": "200003",
@@ -297,7 +262,6 @@
},
{
"BriefDescription": "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD",
@@ -307,7 +271,6 @@
},
{
"BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once.",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.LD_SPLITS",
@@ -317,7 +280,6 @@
},
{
"BriefDescription": "Counts all the retired locked loads. It does not include stores because we would double count if we count stores",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.LOCK",
"SampleAfterValue": "200003",
@@ -325,7 +287,6 @@
},
{
"BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.STA_FULL",
"SampleAfterValue": "200003",
@@ -333,7 +294,6 @@
},
{
"BriefDescription": "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once.",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.ST_SPLITS",
"PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.",
@@ -342,7 +302,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full.",
- "Counter": "0,1",
"EventCode": "0xCB",
"EventName": "RS_FULL_STALL.ALL",
"SampleAfterValue": "200003",
@@ -350,7 +309,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry.",
- "Counter": "0,1",
"EventCode": "0xCB",
"EventName": "RS_FULL_STALL.MEC",
"SampleAfterValue": "200003",
@@ -358,7 +316,6 @@
},
{
"BriefDescription": "Counts the number of micro-ops retired",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PublicDescription": "This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists.",
@@ -367,7 +324,6 @@
},
{
"BriefDescription": "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS).",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MS",
"PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.",
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
index a5e1a9a47e73..a31dca71e868 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
@@ -1,7 +1,6 @@
[
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
"PerPkg": "1",
@@ -9,8 +8,7 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
"PerPkg": "1",
@@ -18,8 +16,7 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
"PerPkg": "1",
@@ -27,8 +24,7 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
"PerPkg": "1",
@@ -36,8 +32,7 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
@@ -45,8 +40,7 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
"PerPkg": "1",
@@ -54,8 +48,7 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
"PerPkg": "1",
@@ -64,43 +57,38 @@
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "EDC_UCLK"
},
{
- "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Number of EDC Hits or Misses. Miss I",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_INVALID",
"PerPkg": "1",
@@ -109,75 +97,66 @@
},
{
"BriefDescription": "ECLK count",
- "Counter": "0,1,2,3",
"EventName": "UNC_E_E_CLOCKTICKS",
"PerPkg": "1",
"Unit": "EDC_ECLK"
},
{
- "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache.",
"EventCode": "0x01",
"EventName": "UNC_E_RPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "UCLK count",
- "Counter": "0,1,2,3",
"EventName": "UNC_E_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache.",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_WPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
@@ -186,7 +165,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
@@ -195,7 +173,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR6",
"PerPkg": "1",
@@ -204,7 +181,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR7",
"PerPkg": "1",
@@ -213,61 +189,54 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
@@ -276,7 +245,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
@@ -285,7 +253,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR6",
"PerPkg": "1",
@@ -294,7 +261,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR7",
"PerPkg": "1",
@@ -303,61 +269,54 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
@@ -366,7 +325,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
@@ -375,7 +333,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR6",
"PerPkg": "1",
@@ -384,7 +341,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR7",
"PerPkg": "1",
@@ -393,61 +349,54 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
@@ -456,7 +405,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
@@ -465,7 +413,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR6",
"PerPkg": "1",
@@ -474,7 +421,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR7",
"PerPkg": "1",
@@ -483,61 +429,54 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4",
"PerPkg": "1",
@@ -546,7 +485,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5",
"PerPkg": "1",
@@ -555,7 +493,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6",
"PerPkg": "1",
@@ -564,7 +501,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7",
"PerPkg": "1",
@@ -573,61 +509,54 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4",
"PerPkg": "1",
@@ -636,7 +565,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5",
"PerPkg": "1",
@@ -645,7 +573,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6",
"PerPkg": "1",
@@ -654,7 +581,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7",
"PerPkg": "1",
@@ -663,61 +589,54 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
@@ -726,7 +645,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
@@ -735,7 +653,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR6",
"PerPkg": "1",
@@ -744,7 +661,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR7",
"PerPkg": "1",
@@ -753,61 +669,54 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
@@ -816,7 +725,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
@@ -825,7 +733,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR6",
"PerPkg": "1",
@@ -834,7 +741,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR7",
"PerPkg": "1",
@@ -843,61 +749,54 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
@@ -906,7 +805,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
@@ -915,7 +813,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR6",
"PerPkg": "1",
@@ -924,7 +821,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR7",
"PerPkg": "1",
@@ -933,61 +829,54 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
@@ -996,7 +885,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
@@ -1005,7 +893,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR6",
"PerPkg": "1",
@@ -1014,7 +901,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR7",
"PerPkg": "1",
@@ -1023,61 +909,54 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4",
"PerPkg": "1",
@@ -1086,7 +965,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5",
"PerPkg": "1",
@@ -1095,7 +973,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6",
"PerPkg": "1",
@@ -1104,7 +981,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7",
"PerPkg": "1",
@@ -1113,61 +989,54 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4",
"PerPkg": "1",
@@ -1176,7 +1045,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5",
"PerPkg": "1",
@@ -1185,7 +1053,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6",
"PerPkg": "1",
@@ -1194,7 +1061,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7",
"PerPkg": "1",
@@ -1203,43 +1069,38 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.E_STATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.F_STATE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Lines Victimized that Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.LOCAL",
"PerPkg": "1",
@@ -1248,16 +1109,14 @@
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.M_STATE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Lines Victimized that Does Not Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.REMOTE",
"PerPkg": "1",
@@ -1266,16 +1125,14 @@
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.S_STATE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_H_CLOCK",
"PerPkg": "1",
@@ -1283,313 +1140,278 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_H_EGRESS_HORZ_ADS_USED.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Bypass. AD ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
"EventName": "UNC_H_EGRESS_HORZ_BYPASS.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Bypass. AK ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
"EventName": "UNC_H_EGRESS_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Bypass. BL ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
"EventName": "UNC_H_EGRESS_HORZ_BYPASS.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Bypass. IV ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
"EventName": "UNC_H_EGRESS_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AD",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AK",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full BL",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full IV",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AD",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AK",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty BL",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty IV",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts AD",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_H_EGRESS_HORZ_INSERTS.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts AK",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_H_EGRESS_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts BL",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_H_EGRESS_HORZ_INSERTS.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts IV",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_H_EGRESS_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_H_EGRESS_HORZ_NACK.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_H_EGRESS_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_H_EGRESS_HORZ_NACK.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_H_EGRESS_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy AD",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy AK",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy BL",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy IV",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_H_EGRESS_HORZ_STARVED.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_H_EGRESS_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_H_EGRESS_HORZ_STARVED.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_H_EGRESS_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
- "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
- "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_UP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
@@ -1598,16 +1420,14 @@
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG1",
"PerPkg": "1",
@@ -1616,16 +1436,14 @@
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
@@ -1634,16 +1452,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
@@ -1652,16 +1468,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
@@ -1670,16 +1484,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
@@ -1688,25 +1500,22 @@
},
{
"BriefDescription": "CMS Vertical Egress Bypass. IV ring agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG1",
"PerPkg": "1",
@@ -1715,16 +1524,14 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG1",
"PerPkg": "1",
@@ -1733,16 +1540,14 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG1",
"PerPkg": "1",
@@ -1751,25 +1556,22 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full IV - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG1",
"PerPkg": "1",
@@ -1778,16 +1580,14 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG1",
"PerPkg": "1",
@@ -1796,16 +1596,14 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG1",
"PerPkg": "1",
@@ -1814,25 +1612,22 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty IV - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG1",
"PerPkg": "1",
@@ -1841,16 +1636,14 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG1",
"PerPkg": "1",
@@ -1859,16 +1652,14 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG1",
"PerPkg": "1",
@@ -1877,25 +1668,22 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations IV - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG1",
"PerPkg": "1",
@@ -1904,16 +1692,14 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG1",
"PerPkg": "1",
@@ -1922,16 +1708,14 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG1",
"PerPkg": "1",
@@ -1940,25 +1724,22 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG1",
"PerPkg": "1",
@@ -1967,16 +1748,14 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG1",
"PerPkg": "1",
@@ -1985,16 +1764,14 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG1",
"PerPkg": "1",
@@ -2003,25 +1780,22 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy IV - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG1",
"PerPkg": "1",
@@ -2030,16 +1804,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG1",
"PerPkg": "1",
@@ -2048,16 +1820,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG1",
"PerPkg": "1",
@@ -2066,25 +1836,22 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts cycles source throttling is adderted - horizontal",
- "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_H_FAST_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts cycles source throttling is adderted - vertical",
- "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_H_FAST_ASSERTED.VERT",
"PerPkg": "1",
@@ -2092,160 +1859,142 @@
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA9",
"EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA9",
"EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA9",
"EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA9",
"EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Left",
- "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Right",
- "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ Rejected",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.PRQ",
"PerPkg": "1",
@@ -2254,7 +2003,6 @@
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ Rejected",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.PRQ_REJ",
"PerPkg": "1",
@@ -2263,34 +2011,30 @@
},
{
"BriefDescription": "Cycles with the IPQ in Internal Starvation.",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_INGRESS_INT_STARVED.IPQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles with the IRQ in Internal Starvation.",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_INGRESS_INT_STARVED.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles with the ISMQ in Internal Starvation.",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_INGRESS_INT_STARVED.ISMQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress internal starvation cycles. Counts cycles in internal starvation. This occurs when one or more of the entries in the ingress queue are being starved out by other entries in the queue.",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_INGRESS_INT_STARVED.PRQ",
"PerPkg": "1",
@@ -2302,7 +2046,7 @@
"EventCode": "0x11",
"EventName": "UNC_H_INGRESS_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
@@ -2310,7 +2054,7 @@
"EventCode": "0x11",
"EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
@@ -2318,7 +2062,7 @@
"EventCode": "0x11",
"EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
@@ -2339,25 +2083,22 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
@@ -2366,7 +2107,6 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
@@ -2375,7 +2115,6 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
@@ -2384,25 +2123,22 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
@@ -2411,7 +2147,6 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
@@ -2420,16 +2155,14 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ANY_REJECT_IPQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.PA_MATCH",
"PerPkg": "1",
@@ -2438,16 +2171,14 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_WAY",
"PerPkg": "1",
@@ -2456,25 +2187,22 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
@@ -2483,7 +2211,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
@@ -2492,7 +2219,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
@@ -2501,25 +2227,22 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
@@ -2528,7 +2251,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
@@ -2537,16 +2259,14 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ANY_REJECT_IRQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
@@ -2555,16 +2275,14 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_WAY",
"PerPkg": "1",
@@ -2573,25 +2291,22 @@
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
@@ -2600,7 +2315,6 @@
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
@@ -2609,7 +2323,6 @@
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
@@ -2618,25 +2331,22 @@
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
@@ -2645,25 +2355,22 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AK_NON_UPI",
"PerPkg": "1",
@@ -2672,7 +2379,6 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
@@ -2681,7 +2387,6 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
@@ -2690,25 +2395,22 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.IV_NON_UPI",
"PerPkg": "1",
@@ -2717,25 +2419,22 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AK_NON_UPI",
"PerPkg": "1",
@@ -2744,7 +2443,6 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
@@ -2753,7 +2451,6 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
@@ -2762,25 +2459,22 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.IV_NON_UPI",
"PerPkg": "1",
@@ -2789,7 +2483,6 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ALLOW_SNP",
"PerPkg": "1",
@@ -2798,16 +2491,14 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ANY_REJECT_IRQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.PA_MATCH",
"PerPkg": "1",
@@ -2816,16 +2507,14 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_WAY",
"PerPkg": "1",
@@ -2834,25 +2523,22 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
@@ -2861,7 +2547,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
@@ -2870,7 +2555,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
@@ -2879,25 +2563,22 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
@@ -2906,7 +2587,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
@@ -2915,16 +2595,14 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ANY_REJECT_IRQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
@@ -2933,16 +2611,14 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_WAY",
"PerPkg": "1",
@@ -2951,25 +2627,22 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AK_NON_UPI",
"PerPkg": "1",
@@ -2978,7 +2651,6 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
@@ -2987,7 +2659,6 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
@@ -2996,25 +2667,22 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.IV_NON_UPI",
"PerPkg": "1",
@@ -3023,7 +2691,6 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ALLOW_SNP",
"PerPkg": "1",
@@ -3032,16 +2699,14 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ANY_REJECT_IRQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.PA_MATCH",
"PerPkg": "1",
@@ -3050,16 +2715,14 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_WAY",
"PerPkg": "1",
@@ -3068,7 +2731,6 @@
},
{
"BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.CV0_PREF_MISS",
"PerPkg": "1",
@@ -3077,7 +2739,6 @@
},
{
"BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Victim",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.CV0_PREF_VIC",
"PerPkg": "1",
@@ -3086,178 +2747,158 @@
},
{
"BriefDescription": "Miscellaneous events in the Cbo. RFO HitS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.RFO_HIT_S",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Miscellaneous events in the Cbo. Silent Snoop Eviction",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Miscellaneous events in the Cbo. Write Combining Aliasing",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.WC_ALIASING",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type.",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_H_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Acknowledgements to core",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_H_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Data Responses to core.",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_H_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Snoops of processor's cache.",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_H_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type.",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_H_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Acknowledgements to core",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_H_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Data Responses to core.",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_H_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Snoops of processor's cache.",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_H_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Horizontal ring sink starvation count - AD ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Horizontal ring sink starvation count - AK ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Horizontal ring sink starvation count - BL ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Horizontal ring sink starvation count - IV ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical ring sink starvation count - AD ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_H_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical ring sink starvation count - AK ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_H_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical ring sink starvation count - BL ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_H_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical ring sink starvation count - IV ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_H_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts cycles in throttle mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_H_RING_SRC_THRTL",
"PerPkg": "1",
@@ -3265,7 +2906,6 @@
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_SF_LOOKUP.ANY",
"PerPkg": "1",
@@ -3274,43 +2914,38 @@
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_SF_LOOKUP.DATA_READ",
"PerPkg": "1",
- "UMask": "0x03",
+ "UMask": "0x3",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_SF_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
- "UMask": "0x09",
+ "UMask": "0x9",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_SF_LOOKUP.WRITE",
"PerPkg": "1",
- "UMask": "0x05",
+ "UMask": "0x5",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
@@ -3319,16 +2954,14 @@
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
@@ -3337,16 +2970,14 @@
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.AD_CRD",
"PerPkg": "1",
@@ -3355,25 +2986,22 @@
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.BL_CRD",
"PerPkg": "1",
@@ -3382,25 +3010,22 @@
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_CRD",
"PerPkg": "1",
@@ -3409,25 +3034,22 @@
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_CRD",
"PerPkg": "1",
@@ -3436,7 +3058,6 @@
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IFV",
"PerPkg": "1",
@@ -3445,25 +3066,22 @@
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.AD_CRD",
"PerPkg": "1",
@@ -3472,25 +3090,22 @@
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.BL_CRD",
"PerPkg": "1",
@@ -3499,25 +3114,22 @@
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_CRD",
"PerPkg": "1",
@@ -3526,25 +3138,22 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_CRD",
"PerPkg": "1",
@@ -3553,16 +3162,14 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -SF/LLC Evictions",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -SF/LLC Evictions",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.EVICT",
"PerPkg": "1",
@@ -3570,17 +3177,15 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Hit (Not a Miss)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Hit (Not a Miss)",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.HIT",
"PerPkg": "1",
- "UMask": "0x1F",
+ "UMask": "0x1f",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.IPQ",
"PerPkg": "1",
@@ -3588,8 +3193,7 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.IRQ",
"PerPkg": "1",
@@ -3597,17 +3201,15 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Miss",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.MISS",
"PerPkg": "1",
- "UMask": "0x2F",
+ "UMask": "0x2f",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.PRQ",
"PerPkg": "1",
@@ -3627,7 +3229,7 @@
"EventCode": "0x36",
"EventName": "UNC_H_TOR_OCCUPANCY.HIT",
"PerPkg": "1",
- "UMask": "0x1F",
+ "UMask": "0x1f",
"Unit": "CHA"
},
{
@@ -3683,7 +3285,7 @@
"EventCode": "0x36",
"EventName": "UNC_H_TOR_OCCUPANCY.MISS",
"PerPkg": "1",
- "UMask": "0x2F",
+ "UMask": "0x2f",
"Unit": "CHA"
},
{
@@ -3712,167 +3314,148 @@
},
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventName": "UNC_H_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
"EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
"EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
"EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
"EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Down",
- "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_H_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Up",
- "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_H_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1",
"PerPkg": "1",
@@ -3881,16 +3464,14 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1",
"PerPkg": "1",
@@ -3899,34 +3480,30 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1",
"PerPkg": "1",
@@ -3935,16 +3512,14 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1",
"PerPkg": "1",
@@ -3953,16 +3528,14 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AD_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AD_1",
"PerPkg": "1",
@@ -3971,16 +3544,14 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_1",
"PerPkg": "1",
@@ -3989,16 +3560,14 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1",
"PerPkg": "1",
@@ -4007,16 +3576,14 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.BL_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.BL_1",
"PerPkg": "1",
@@ -4025,7 +3592,6 @@
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -4034,68 +3600,60 @@
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CAS All",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x03",
+ "UMask": "0x3",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "CAS Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "CAS Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "DCLK count",
- "Counter": "0,1,2,3",
"EventName": "UNC_M_D_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "UCLK count",
- "Counter": "0,1,2,3",
"EventName": "UNC_M_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC_UCLK"
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json
index 821cdd44a12f..99a8fa8f19cc 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
@@ -11,7 +10,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included.",
- "Counter": "0,1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.CYCLES",
"PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.",
@@ -20,7 +18,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included.",
- "Counter": "0,1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "200003",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted",
- "Counter": "0,1",
"EdgeDetect": "1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
@@ -37,7 +33,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included.",
- "Counter": "0,1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress.",
@@ -46,7 +41,6 @@
},
{
"BriefDescription": "Counts the total I-side page walks that are completed.",
- "Counter": "0,1",
"EdgeDetect": "1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
@@ -55,7 +49,6 @@
},
{
"BriefDescription": "Counts the total page walks that are completed (I-side and D-side)",
- "Counter": "0,1",
"EdgeDetect": "1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.WALKS",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 20/32] perf vendor events intel: Refresh meteorlake events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (9 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 19/32] perf vendor events intel: Refresh knightslanding events Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:54 ` [PATCH v1 21/32] perf vendor events intel: Refresh nehalemep events Ian Rogers
` (11 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the meteorlake events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but they are sorted and unused json values
are removed. This increases consistency across the json files. The
CPUID matching regular expression is updated to match the perfmon one.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
.../pmu-events/arch/x86/meteorlake/cache.json | 170 ++++----------
.../arch/x86/meteorlake/frontend.json | 6 -
.../arch/x86/meteorlake/memory.json | 77 ++----
.../pmu-events/arch/x86/meteorlake/other.json | 24 +-
.../arch/x86/meteorlake/pipeline.json | 222 ++++++------------
.../arch/x86/meteorlake/virtual-memory.json | 28 +--
7 files changed, 166 insertions(+), 363 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index de3f9dd4e6f7..84f74acf91d9 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -17,7 +17,7 @@ GenuineIntel-6-3A,v23,ivybridge,core
GenuineIntel-6-3E,v22,ivytown,core
GenuineIntel-6-2D,v21,jaketown,core
GenuineIntel-6-(57|85),v9,knightslanding,core
-GenuineIntel-6-AA,v1.00,meteorlake,core
+GenuineIntel-6-A[AC],v1.00,meteorlake,core
GenuineIntel-6-1[AEF],v3,nehalemep,core
GenuineIntel-6-2E,v3,nehalemex,core
GenuineIntel-6-2A,v17,sandybridge,core
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
index 32b2aa9b1475..0970724a2984 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
@@ -1,262 +1,196 @@
[
+ {
+ "BriefDescription": "L2 code requests",
+ "EventCode": "0x24",
+ "EventName": "L2_RQSTS.ALL_CODE_RD",
+ "SampleAfterValue": "200003",
+ "UMask": "0xe4",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Demand Data Read access L2 cache",
+ "EventCode": "0x24",
+ "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
+ "SampleAfterValue": "200003",
+ "UMask": "0xe1",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "200003",
"UMask": "0x41",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
+ "EventCode": "0x2e",
+ "EventName": "LONGEST_LAT_CACHE.MISS",
+ "SampleAfterValue": "100003",
+ "UMask": "0x41",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "200003",
"UMask": "0x4f",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
+ "EventCode": "0x2e",
+ "EventName": "LONGEST_LAT_CACHE.REFERENCE",
+ "SampleAfterValue": "100003",
+ "UMask": "0x4f",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Retired load instructions.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_INST_RETIRED.ALL_LOADS",
+ "PEBS": "1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x81",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Retired store instructions.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_INST_RETIRED.ALL_STORES",
+ "PEBS": "1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x82",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Counts the number of load ops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "200003",
"UMask": "0x81",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of store ops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "200003",
"UMask": "0x82",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "CollectPEBSRecord": "3",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "CollectPEBSRecord": "3",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "CollectPEBSRecord": "3",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "CollectPEBSRecord": "3",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "CollectPEBSRecord": "3",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "CollectPEBSRecord": "3",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "CollectPEBSRecord": "3",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "CollectPEBSRecord": "3",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
- "CollectPEBSRecord": "3",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x6",
"Unit": "cpu_atom"
- },
- {
- "BriefDescription": "L2 code requests",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "L2_RQSTS.ALL_CODE_RD",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "200003",
- "UMask": "0xe4",
- "Unit": "cpu_core"
- },
- {
- "BriefDescription": "Demand Data Read access L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "200003",
- "UMask": "0xe1",
- "Unit": "cpu_core"
- },
- {
- "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0x2e",
- "EventName": "LONGEST_LAT_CACHE.MISS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "100003",
- "UMask": "0x41",
- "Unit": "cpu_core"
- },
- {
- "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0x2e",
- "EventName": "LONGEST_LAT_CACHE.REFERENCE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "100003",
- "UMask": "0x4f",
- "Unit": "cpu_core"
- },
- {
- "BriefDescription": "Retired load instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "Data_LA": "1",
- "EventCode": "0xd0",
- "EventName": "MEM_INST_RETIRED.ALL_LOADS",
- "PEBS": "1",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x81",
- "Unit": "cpu_core"
- },
- {
- "BriefDescription": "Retired store instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "Data_LA": "1",
- "EventCode": "0xd0",
- "EventName": "MEM_INST_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
- "PEBS": "1",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x82",
- "Unit": "cpu_core"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
index 9657768fc95a..7de11819dd0d 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
@@ -1,22 +1,16 @@
[
{
"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "200003",
"UMask": "0x3",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "200003",
"UMask": "0x2",
"Unit": "cpu_atom"
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/memory.json b/tools/perf/pmu-events/arch/x86/meteorlake/memory.json
index 15b2294a8ae7..b7715cec1dbc 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/memory.json
@@ -1,157 +1,102 @@
[
- {
- "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xB7",
- "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FBFC00001",
- "SampleAfterValue": "100003",
- "UMask": "0x1",
- "Unit": "cpu_atom"
- },
- {
- "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xB7",
- "EventName": "OCR.DEMAND_RFO.L3_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FBFC00002",
- "SampleAfterValue": "100003",
- "UMask": "0x1",
- "Unit": "cpu_atom"
- },
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
- "CollectPEBSRecord": "2",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
@@ -160,9 +105,18 @@
"UMask": "0x2",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FBFC00001",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -171,9 +125,18 @@
"UMask": "0x1",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_RFO.L3_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FBFC00002",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/other.json b/tools/perf/pmu-events/arch/x86/meteorlake/other.json
index 14273ac54d2c..ae98e3d0e149 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts cacheable demand data reads Catch all value for any response types - this includes response types not define in the OCR. If this is set all other response types will be ignored",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -10,20 +9,8 @@
"UMask": "0x1",
"Unit": "cpu_atom"
},
- {
- "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR. If this is set all other response types will be ignored",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xB7",
- "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10002",
- "SampleAfterValue": "100003",
- "UMask": "0x1",
- "Unit": "cpu_atom"
- },
{
"BriefDescription": "Counts demand data reads that have any type of response.",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -32,9 +19,18 @@
"UMask": "0x1",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR. If this is set all other response types will be ignored",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10002",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
index 0a7981675b6c..7be7e40c03ac 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
@@ -1,254 +1,182 @@
[
{
"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "200003",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "All branch instructions retired.",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
+ "PEBS": "1",
+ "SampleAfterValue": "400009",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "200003",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "All mispredicted branch instructions retired.",
+ "EventCode": "0xc5",
+ "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
+ "PEBS": "1",
+ "SampleAfterValue": "400009",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
- "CollectPEBSRecord": "2",
- "Counter": "33",
"EventName": "CPU_CLK_UNHALTED.CORE",
- "PEBScounters": "33",
"SampleAfterValue": "2000003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
- "CollectPEBSRecord": "2",
- "Counter": "34",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PEBScounters": "34",
"SampleAfterValue": "2000003",
"UMask": "0x3",
"Unit": "cpu_atom"
},
- {
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
- "CollectPEBSRecord": "2",
- "Counter": "33",
- "EventName": "CPU_CLK_UNHALTED.THREAD",
- "PEBScounters": "33",
- "SampleAfterValue": "2000003",
- "UMask": "0x2",
- "Unit": "cpu_atom"
- },
- {
- "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0x3c",
- "EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "2000003",
- "Unit": "cpu_atom"
- },
- {
- "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
- "CollectPEBSRecord": "2",
- "Counter": "32",
- "EventName": "INST_RETIRED.ANY",
- "PEBS": "1",
- "PEBScounters": "32",
- "SampleAfterValue": "2000003",
- "UMask": "0x1",
- "Unit": "cpu_atom"
- },
- {
- "BriefDescription": "Counts the number of instructions retired",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xc0",
- "EventName": "INST_RETIRED.ANY_P",
- "PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "2000003",
- "Unit": "cpu_atom"
- },
- {
- "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0x73",
- "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "1000003",
- "Unit": "cpu_atom"
- },
- {
- "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0x74",
- "EventName": "TOPDOWN_BE_BOUND.ALL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "1000003",
- "Unit": "cpu_atom"
- },
- {
- "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0x71",
- "EventName": "TOPDOWN_FE_BOUND.ALL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "1000003",
- "Unit": "cpu_atom"
- },
- {
- "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0x72",
- "EventName": "TOPDOWN_RETIRING.ALL",
- "PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "1000003",
- "Unit": "cpu_atom"
- },
- {
- "BriefDescription": "All branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xc4",
- "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
- "PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "400009",
- "Unit": "cpu_core"
- },
- {
- "BriefDescription": "All mispredicted branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xc5",
- "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
- "PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "400009",
- "Unit": "cpu_core"
- },
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "CollectPEBSRecord": "2",
- "Counter": "34",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PEBScounters": "34",
"SampleAfterValue": "2000003",
"UMask": "0x3",
"Unit": "cpu_core"
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"UMask": "0x1",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "EventName": "CPU_CLK_UNHALTED.THREAD",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "33",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "PEBScounters": "33",
"SampleAfterValue": "2000003",
"UMask": "0x2",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]",
+ "EventCode": "0x3c",
+ "EventName": "CPU_CLK_UNHALTED.THREAD_P",
+ "SampleAfterValue": "2000003",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
+ "EventName": "INST_RETIRED.ANY",
+ "PEBS": "1",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "32",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
- "PEBScounters": "32",
"SampleAfterValue": "2000003",
"UMask": "0x1",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of instructions retired",
+ "EventCode": "0xc0",
+ "EventName": "INST_RETIRED.ANY_P",
+ "PEBS": "1",
+ "SampleAfterValue": "2000003",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"Unit": "cpu_core"
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"UMask": "0x82",
"Unit": "cpu_core"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "35",
"EventName": "TOPDOWN.SLOTS",
- "PEBScounters": "35",
"SampleAfterValue": "10000003",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.SLOTS_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "10000003",
"UMask": "0x1",
"Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
+ "EventCode": "0x73",
+ "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
+ "SampleAfterValue": "1000003",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.ALL",
+ "SampleAfterValue": "1000003",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.ALL",
+ "SampleAfterValue": "1000003",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL",
+ "EventCode": "0x72",
+ "EventName": "TOPDOWN_RETIRING.ALL",
+ "PEBS": "1",
+ "SampleAfterValue": "1000003",
+ "Unit": "cpu_atom"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json
index 3087730cca7b..0ee62378bf22 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json
@@ -1,44 +1,32 @@
[
- {
- "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0x85",
- "EventName": "ITLB_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "SampleAfterValue": "200003",
- "UMask": "0xe",
- "Unit": "cpu_atom"
- },
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"UMask": "0xe",
"Unit": "cpu_core"
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"UMask": "0xe",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
+ "EventCode": "0x85",
+ "EventName": "ITLB_MISSES.WALK_COMPLETED",
+ "SampleAfterValue": "200003",
+ "UMask": "0xe",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"UMask": "0xe",
"Unit": "cpu_core"
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 21/32] perf vendor events intel: Refresh nehalemep events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (10 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 20/32] perf vendor events intel: Refresh meteorlake events Ian Rogers
@ 2022-12-15 6:54 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 22/32] perf vendor events intel: Refresh nehalemex events Ian Rogers
` (10 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:54 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the nehalemep events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/nehalemep/cache.json | 524 ------------------
.../arch/x86/nehalemep/floating-point.json | 28 -
.../arch/x86/nehalemep/frontend.json | 3 -
.../pmu-events/arch/x86/nehalemep/memory.json | 134 -----
.../pmu-events/arch/x86/nehalemep/other.json | 18 -
.../arch/x86/nehalemep/pipeline.json | 127 +----
.../arch/x86/nehalemep/virtual-memory.json | 13 -
7 files changed, 5 insertions(+), 842 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json
index 1ee91300baf9..1a132fcda964 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles L1D locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Cycles L1D and L2 locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1D cache lines replaced in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_EVICT",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1D cache lines allocated in the M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_REPL",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1D snoop eviction of cache lines in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_SNOOP_EVICT",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1 data cache lines allocated",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.REPL",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "All references to the L1 data cache",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.ANY",
"SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "L1 data cacheable reads and writes",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.CACHEABLE",
"SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "L1 data cache read in E state",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.E_STATE",
"SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "L1 data cache read in I state (misses)",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.I_STATE",
"SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "L1 data cache reads",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.MESI",
"SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "L1 data cache read in M state",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.M_STATE",
"SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "L1 data cache read in S state",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.S_STATE",
"SampleAfterValue": "2000000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "L1 data cache load locks in E state",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.E_STATE",
"SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "L1 data cache load lock hits",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.HIT",
"SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "L1 data cache load locks in M state",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.M_STATE",
"SampleAfterValue": "2000000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "L1 data cache load locks in S state",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.S_STATE",
"SampleAfterValue": "2000000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "L1D load lock accepted in fill buffer",
- "Counter": "0,1",
"EventCode": "0x53",
"EventName": "L1D_CACHE_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -145,7 +127,6 @@
},
{
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
- "Counter": "0,1",
"EventCode": "0x52",
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -153,7 +134,6 @@
},
{
"BriefDescription": "L1 data cache stores in E state",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.E_STATE",
"SampleAfterValue": "2000000",
@@ -161,7 +141,6 @@
},
{
"BriefDescription": "L1 data cache stores in M state",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.M_STATE",
"SampleAfterValue": "2000000",
@@ -169,7 +148,6 @@
},
{
"BriefDescription": "L1 data cache stores in S state",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.S_STATE",
"SampleAfterValue": "2000000",
@@ -177,7 +155,6 @@
},
{
"BriefDescription": "L1D hardware prefetch misses",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.MISS",
"SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.REQUESTS",
"SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests triggered",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.TRIGGERS",
"SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.E_STATE",
"SampleAfterValue": "100000",
@@ -209,7 +183,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.I_STATE",
"SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
},
{
"BriefDescription": "All L1 writebacks to L2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.MESI",
"SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.M_STATE",
"SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.S_STATE",
"SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
},
{
"BriefDescription": "All L2 data requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.ANY",
"SampleAfterValue": "200000",
@@ -249,7 +218,6 @@
},
{
"BriefDescription": "L2 data demand loads in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -257,7 +225,6 @@
},
{
"BriefDescription": "L2 data demand loads in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -265,7 +232,6 @@
},
{
"BriefDescription": "L2 data demand requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -273,7 +239,6 @@
},
{
"BriefDescription": "L2 data demand loads in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
},
{
"BriefDescription": "L2 data demand loads in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
},
{
"BriefDescription": "L2 data prefetches in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
},
{
"BriefDescription": "L2 data prefetches in the I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
},
{
"BriefDescription": "All L2 data prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
},
{
"BriefDescription": "L2 data prefetches in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
},
{
"BriefDescription": "L2 data prefetches in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
},
{
"BriefDescription": "L2 lines alloacated",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ANY",
"SampleAfterValue": "100000",
@@ -337,7 +295,6 @@
},
{
"BriefDescription": "L2 lines allocated in the E state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E_STATE",
"SampleAfterValue": "100000",
@@ -345,7 +302,6 @@
},
{
"BriefDescription": "L2 lines allocated in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S_STATE",
"SampleAfterValue": "100000",
@@ -353,7 +309,6 @@
},
{
"BriefDescription": "L2 lines evicted",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.ANY",
"SampleAfterValue": "100000",
@@ -361,7 +316,6 @@
},
{
"BriefDescription": "L2 lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100000",
@@ -369,7 +323,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100000",
@@ -377,7 +330,6 @@
},
{
"BriefDescription": "L2 lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
"SampleAfterValue": "100000",
@@ -385,7 +337,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
"SampleAfterValue": "100000",
@@ -393,7 +344,6 @@
},
{
"BriefDescription": "L2 instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCHES",
"SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
},
{
"BriefDescription": "L2 instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_HIT",
"SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
},
{
"BriefDescription": "L2 instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_MISS",
"SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
},
{
"BriefDescription": "L2 load hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_HIT",
"SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
},
{
"BriefDescription": "L2 load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_MISS",
"SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
},
{
"BriefDescription": "L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LOADS",
"SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
},
{
"BriefDescription": "All L2 misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
},
{
"BriefDescription": "All L2 prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCHES",
"SampleAfterValue": "200000",
@@ -457,7 +400,6 @@
},
{
"BriefDescription": "L2 prefetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_HIT",
"SampleAfterValue": "200000",
@@ -465,7 +407,6 @@
},
{
"BriefDescription": "L2 prefetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_MISS",
"SampleAfterValue": "200000",
@@ -473,7 +414,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200000",
@@ -481,7 +421,6 @@
},
{
"BriefDescription": "L2 RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFOS",
"SampleAfterValue": "200000",
@@ -489,7 +428,6 @@
},
{
"BriefDescription": "L2 RFO hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200000",
@@ -497,7 +435,6 @@
},
{
"BriefDescription": "L2 RFO misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200000",
@@ -505,7 +442,6 @@
},
{
"BriefDescription": "All L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.ANY",
"SampleAfterValue": "200000",
@@ -513,7 +449,6 @@
},
{
"BriefDescription": "L2 fill transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.FILL",
"SampleAfterValue": "200000",
@@ -521,7 +456,6 @@
},
{
"BriefDescription": "L2 instruction fetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.IFETCH",
"SampleAfterValue": "200000",
@@ -529,7 +463,6 @@
},
{
"BriefDescription": "L1D writeback to L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.L1D_WB",
"SampleAfterValue": "200000",
@@ -537,7 +470,6 @@
},
{
"BriefDescription": "L2 Load transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.LOAD",
"SampleAfterValue": "200000",
@@ -545,7 +477,6 @@
},
{
"BriefDescription": "L2 prefetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.PREFETCH",
"SampleAfterValue": "200000",
@@ -553,7 +484,6 @@
},
{
"BriefDescription": "L2 RFO transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.RFO",
"SampleAfterValue": "200000",
@@ -561,7 +491,6 @@
},
{
"BriefDescription": "L2 writeback to LLC transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.WB",
"SampleAfterValue": "200000",
@@ -569,7 +498,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.E_STATE",
"SampleAfterValue": "100000",
@@ -577,7 +505,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.HIT",
"SampleAfterValue": "100000",
@@ -585,7 +512,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.I_STATE",
"SampleAfterValue": "100000",
@@ -593,7 +519,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.MESI",
"SampleAfterValue": "100000",
@@ -601,7 +526,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.M_STATE",
"SampleAfterValue": "100000",
@@ -609,7 +533,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.S_STATE",
"SampleAfterValue": "100000",
@@ -617,7 +540,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.HIT",
"SampleAfterValue": "100000",
@@ -625,7 +547,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.I_STATE",
"SampleAfterValue": "100000",
@@ -633,7 +554,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.MESI",
"SampleAfterValue": "100000",
@@ -641,7 +561,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.M_STATE",
"SampleAfterValue": "100000",
@@ -649,7 +568,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.S_STATE",
"SampleAfterValue": "100000",
@@ -657,7 +575,6 @@
},
{
"BriefDescription": "Longest latency cache miss",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100000",
@@ -665,7 +582,6 @@
},
{
"BriefDescription": "Longest latency cache reference",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200000",
@@ -673,18 +589,15 @@
},
{
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
"MSRIndex": "0x3F6",
- "MSRValue": "0x0",
"PEBS": "2",
"SampleAfterValue": "2000000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
"MSRIndex": "0x3F6",
@@ -695,7 +608,6 @@
},
{
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
"MSRIndex": "0x3F6",
@@ -706,7 +618,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
"MSRIndex": "0x3F6",
@@ -717,7 +628,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
"MSRIndex": "0x3F6",
@@ -728,7 +638,6 @@
},
{
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
"MSRIndex": "0x3F6",
@@ -739,7 +648,6 @@
},
{
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
"MSRIndex": "0x3F6",
@@ -750,7 +658,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
"MSRIndex": "0x3F6",
@@ -761,7 +668,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
"MSRIndex": "0x3F6",
@@ -772,7 +678,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
"MSRIndex": "0x3F6",
@@ -783,7 +688,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
"MSRIndex": "0x3F6",
@@ -794,7 +698,6 @@
},
{
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
"MSRIndex": "0x3F6",
@@ -805,7 +708,6 @@
},
{
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
"MSRIndex": "0x3F6",
@@ -816,7 +718,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
"MSRIndex": "0x3F6",
@@ -827,7 +728,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
"MSRIndex": "0x3F6",
@@ -838,7 +738,6 @@
},
{
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LOADS",
"PEBS": "1",
@@ -847,7 +746,6 @@
},
{
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.STORES",
"PEBS": "1",
@@ -856,7 +754,6 @@
},
{
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -865,7 +762,6 @@
},
{
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
"PEBS": "1",
@@ -874,7 +770,6 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
@@ -883,7 +778,6 @@
},
{
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -892,7 +786,6 @@
},
{
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
"PEBS": "1",
@@ -901,7 +794,6 @@
},
{
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
"PEBS": "1",
@@ -910,7 +802,6 @@
},
{
"BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
"PEBS": "1",
@@ -919,7 +810,6 @@
},
{
"BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
"PEBS": "1",
@@ -928,7 +818,6 @@
},
{
"BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
"PEBS": "1",
@@ -937,7 +826,6 @@
},
{
"BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
"PEBS": "1",
@@ -946,7 +834,6 @@
},
{
"BriefDescription": "Load instructions retired IO (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
"PEBS": "1",
@@ -955,7 +842,6 @@
},
{
"BriefDescription": "Offcore L1 data cache writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
"SampleAfterValue": "100000",
@@ -963,7 +849,6 @@
},
{
"BriefDescription": "Offcore requests blocked due to Super Queue full",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
"SampleAfterValue": "100000",
@@ -971,2240 +856,1833 @@
},
{
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore data reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x111",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x211",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x411",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x711",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4711",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x144",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x244",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x444",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x744",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4744",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7FFF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFFFF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x80FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x2FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x7FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x47FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x18FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x38FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x10FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x8FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore RFO requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x122",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x222",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x422",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x722",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4722",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore writebacks",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x108",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x408",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x708",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4708",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code or data read requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x177",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x277",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x477",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x777",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4777",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any cache_dram",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any location",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x133",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x233",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x433",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x733",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache or dram",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4733",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x103",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x203",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x403",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x703",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4703",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x101",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x201",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x401",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x701",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4701",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand code reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x104",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x204",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x404",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x704",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4704",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand RFO requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x102",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x202",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x402",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x702",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4702",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore other requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x180",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x280",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x480",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x780",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4780",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F30",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch data requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF30",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x130",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x230",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x430",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x730",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4730",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch data reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x110",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x210",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x410",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x710",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4710",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch code reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x140",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x240",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x440",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x740",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4740",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch RFO requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x120",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x220",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x420",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x720",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4720",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x170",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x270",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x470",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x770",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4770",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Super Queue lock splits across a cache line",
- "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "2000000",
@@ -3212,7 +2690,6 @@
},
{
"BriefDescription": "Loads delayed with at-Retirement block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.AT_RET",
"SampleAfterValue": "200000",
@@ -3220,7 +2697,6 @@
},
{
"BriefDescription": "Cacheable loads delayed with L1D block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.L1D_BLOCK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json
index 666e466d351c..c03f8990fa82 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "X87 Floating point assists (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.ALL",
"PEBS": "1",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.INPUT",
"PEBS": "1",
@@ -19,7 +17,6 @@
},
{
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.OUTPUT",
"PEBS": "1",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "MMX Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "SSE2 integer Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "SSE* FP double precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "SSE and SSE2 FP Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "SSE FP packed Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "SSE FP scalar Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "SSE* FP single precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Computational floating-point operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "All Floating Point to and from MMX transitions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Transitions from MMX to Floating Point instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Transitions from Floating Point to MMX instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "128 bit SIMD integer pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "128 bit SIMD integer arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "128 bit SIMD integer logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "128 bit SIMD integer multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "128 bit SIMD integer unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json
index c561ac24d91d..f7f28510e3ae 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Macro-fused instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Two Uop instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json
index 6e95de3f3409..f810880a295e 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json
@@ -1,738 +1,604 @@
[
{
"BriefDescription": "Offcore data reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x60FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF8FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x40FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x20FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any LLC miss",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/other.json b/tools/perf/pmu-events/arch/x86/nehalemep/other.json
index f6887b234b0e..fb706cb51832 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/other.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "ES segment renames",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "I/O transactions",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1I instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1I instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1I Instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "Large ITLB hit",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "All loads dispatched",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "Loads dispatched from the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "Loads dispatched that bypass the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "Loads dispatched from stage 305",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "False dependencies due to partial address aliasing",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "All Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "Segment rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "Thread responded HIT to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "Thread responded HITE to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "Thread responded HITM to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "Super Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json
index 6fc1a6efd8e8..c45f2ffa861e 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles the divider is busy",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Divide Operations executed",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -20,7 +18,6 @@
},
{
"BriefDescription": "Multiply operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.MUL",
"SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "BACLEAR asserted with bad target address",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.BAD_TARGET",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "BACLEAR asserted, regardless of cause",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.CLEAR",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "Instruction queue forced BACLEAR",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "BACLEAR_FORCE_IQ",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "Branch instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ANY",
"SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "Conditional branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.COND",
"SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT",
"SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Unconditional call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "Indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "Indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "Call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NEAR_CALLS",
"SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "All non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NON_CALLS",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "Indirect return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.RETURN_NEAR",
"SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "Taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "Retired branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -173,7 +152,6 @@
},
{
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -182,7 +160,6 @@
},
{
"BriefDescription": "Retired near call instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -191,7 +168,6 @@
},
{
"BriefDescription": "Mispredicted branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ANY",
"SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
},
{
"BriefDescription": "Mispredicted conditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.COND",
"SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
},
{
"BriefDescription": "Mispredicted unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT",
"SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
},
{
"BriefDescription": "Mispredicted indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
},
{
"BriefDescription": "Mispredicted indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
},
{
"BriefDescription": "Mispredicted call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
"SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NON_CALLS",
"SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
},
{
"BriefDescription": "Mispredicted return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
"SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
},
{
"BriefDescription": "Mispredicted taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN",
"SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
},
{
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -280,15 +246,11 @@
},
{
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 3",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.REF",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_P",
"SampleAfterValue": "100000",
@@ -296,33 +258,25 @@
},
{
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 2",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Total CPU cycles",
- "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
"Invert": "1",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Any Instruction Length Decoder stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.ANY",
"SampleAfterValue": "2000000",
@@ -330,7 +284,6 @@
},
{
"BriefDescription": "Instruction Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@@ -338,7 +291,6 @@
},
{
"BriefDescription": "Length Change Prefix stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000000",
@@ -346,7 +298,6 @@
},
{
"BriefDescription": "Stall cycles due to BPU MRU bypass",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.MRU",
"SampleAfterValue": "2000000",
@@ -354,7 +305,6 @@
},
{
"BriefDescription": "Regen stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.REGEN",
"SampleAfterValue": "2000000",
@@ -362,7 +312,6 @@
},
{
"BriefDescription": "Instructions that must be decoded by decoder 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "INST_DECODED.DEC0",
"SampleAfterValue": "2000000",
@@ -370,7 +319,6 @@
},
{
"BriefDescription": "Instructions written to instruction queue.",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INST_QUEUE_WRITES",
"SampleAfterValue": "2000000",
@@ -378,7 +326,6 @@
},
{
"BriefDescription": "Cycles instructions are written to the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "INST_QUEUE_WRITE_CYCLES",
"SampleAfterValue": "2000000",
@@ -386,15 +333,11 @@
},
{
"BriefDescription": "Instructions retired (fixed counter)",
- "Counter": "Fixed counter 1",
- "EventCode": "0x0",
"EventName": "INST_RETIRED.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@@ -403,7 +346,6 @@
},
{
"BriefDescription": "Retired MMX instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.MMX",
"PEBS": "1",
@@ -412,7 +354,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -423,7 +364,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -434,7 +374,6 @@
},
{
"BriefDescription": "Retired floating-point operations (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PEBS": "1",
@@ -443,7 +382,6 @@
},
{
"BriefDescription": "Load operations conflicting with software prefetches",
- "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE",
"SampleAfterValue": "200000",
@@ -451,7 +389,6 @@
},
{
"BriefDescription": "Cycles when uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.ACTIVE",
@@ -460,7 +397,6 @@
},
{
"BriefDescription": "Cycles no uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.INACTIVE",
@@ -470,7 +406,6 @@
},
{
"BriefDescription": "Loops that can't stream from the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "LSD_OVERFLOW",
"SampleAfterValue": "2000000",
@@ -478,7 +413,6 @@
},
{
"BriefDescription": "Cycles machine clear asserted",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "20000",
@@ -486,7 +420,6 @@
},
{
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEM_ORDER",
"SampleAfterValue": "20000",
@@ -494,7 +427,6 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20000",
@@ -502,7 +434,6 @@
},
{
"BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -510,7 +441,6 @@
},
{
"BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
@@ -518,7 +448,6 @@
},
{
"BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
@@ -526,7 +455,6 @@
},
{
"BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
@@ -534,7 +462,6 @@
},
{
"BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
@@ -542,7 +469,6 @@
},
{
"BriefDescription": "Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -550,7 +476,6 @@
},
{
"BriefDescription": "FPU control word write stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.FPCW",
"SampleAfterValue": "2000000",
@@ -558,7 +483,6 @@
},
{
"BriefDescription": "Load buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LOAD",
"SampleAfterValue": "2000000",
@@ -566,7 +490,6 @@
},
{
"BriefDescription": "MXCSR rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MXCSR",
"SampleAfterValue": "2000000",
@@ -574,7 +497,6 @@
},
{
"BriefDescription": "Other Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OTHER",
"SampleAfterValue": "2000000",
@@ -582,7 +504,6 @@
},
{
"BriefDescription": "ROB full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB_FULL",
"SampleAfterValue": "2000000",
@@ -590,7 +511,6 @@
},
{
"BriefDescription": "Reservation Station full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS_FULL",
"SampleAfterValue": "2000000",
@@ -598,7 +518,6 @@
},
{
"BriefDescription": "Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.STORE",
"SampleAfterValue": "2000000",
@@ -606,7 +525,6 @@
},
{
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
"PEBS": "1",
@@ -615,7 +533,6 @@
},
{
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
"PEBS": "1",
@@ -624,7 +541,6 @@
},
{
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
"PEBS": "1",
@@ -633,7 +549,6 @@
},
{
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
"PEBS": "1",
@@ -642,7 +557,6 @@
},
{
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
"PEBS": "1",
@@ -651,7 +565,6 @@
},
{
"BriefDescription": "Stack pointer instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_FOLDING",
"SampleAfterValue": "2000000",
@@ -659,7 +572,6 @@
},
{
"BriefDescription": "Stack pointer sync operations",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_SYNC",
"SampleAfterValue": "2000000",
@@ -667,7 +579,6 @@
},
{
"BriefDescription": "Uops decoded by Microcode Sequencer",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -676,7 +587,6 @@
},
{
"BriefDescription": "Cycles no Uops are decoded",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -687,7 +597,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -697,7 +606,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -707,7 +615,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -719,7 +626,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -731,7 +637,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -742,7 +647,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -752,7 +656,6 @@
},
{
"BriefDescription": "Uops executed on port 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT0",
"SampleAfterValue": "2000000",
@@ -760,7 +663,6 @@
},
{
"BriefDescription": "Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015",
"SampleAfterValue": "2000000",
@@ -768,7 +670,6 @@
},
{
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -778,7 +679,6 @@
},
{
"BriefDescription": "Uops executed on port 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT1",
"SampleAfterValue": "2000000",
@@ -787,7 +687,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops issued on ports 2, 3 or 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT234_CORE",
"SampleAfterValue": "2000000",
@@ -796,7 +695,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 2 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT2_CORE",
"SampleAfterValue": "2000000",
@@ -805,7 +703,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 3 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT3_CORE",
"SampleAfterValue": "2000000",
@@ -814,7 +711,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 4 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT4_CORE",
"SampleAfterValue": "2000000",
@@ -822,7 +718,6 @@
},
{
"BriefDescription": "Uops executed on port 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT5",
"SampleAfterValue": "2000000",
@@ -830,7 +725,6 @@
},
{
"BriefDescription": "Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000000",
@@ -839,7 +733,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops were issued on any thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -850,7 +743,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops were issued on either thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -859,7 +751,6 @@
},
{
"BriefDescription": "Fused Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.FUSED",
"SampleAfterValue": "2000000",
@@ -867,7 +758,6 @@
},
{
"BriefDescription": "Cycles no Uops were issued",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -877,7 +767,6 @@
},
{
"BriefDescription": "Cycles Uops are being retired",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -887,7 +776,6 @@
},
{
"BriefDescription": "Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "1",
@@ -896,7 +784,6 @@
},
{
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PEBS": "1",
@@ -905,7 +792,6 @@
},
{
"BriefDescription": "Retirement slots used (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -914,7 +800,6 @@
},
{
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -925,7 +810,6 @@
},
{
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -936,7 +820,6 @@
},
{
"BriefDescription": "Uop unfusions due to FP exceptions",
- "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UOP_UNFUSION",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json
index e88c0802e679..c434cd4ef4f1 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "DTLB load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "DTLB load miss caused by low part of address",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "DTLB second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "DTLB load miss page walks complete",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "DTLB misses",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "DTLB first level misses but second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "DTLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "ITLB flushes",
- "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "ITLB miss",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "ITLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
@@ -90,7 +79,6 @@
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
@@ -99,7 +87,6 @@
},
{
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 22/32] perf vendor events intel: Refresh nehalemex events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (11 preceding siblings ...)
2022-12-15 6:54 ` [PATCH v1 21/32] perf vendor events intel: Refresh nehalemep events Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 23/32] perf vendor events intel: Refresh sandybridge metrics and events Ian Rogers
` (9 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the nehalemex events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/nehalemex/cache.json | 519 ------------------
.../arch/x86/nehalemex/floating-point.json | 28 -
.../arch/x86/nehalemex/frontend.json | 3 -
.../pmu-events/arch/x86/nehalemex/memory.json | 134 -----
.../pmu-events/arch/x86/nehalemex/other.json | 18 -
.../arch/x86/nehalemex/pipeline.json | 127 +----
.../arch/x86/nehalemex/virtual-memory.json | 13 -
7 files changed, 5 insertions(+), 837 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json
index 01542c4ea678..a4142cd2ca86 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles L1D locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Cycles L1D and L2 locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1D cache lines replaced in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_EVICT",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1D cache lines allocated in the M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_REPL",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1D snoop eviction of cache lines in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_SNOOP_EVICT",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1 data cache lines allocated",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.REPL",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "All references to the L1 data cache",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.ANY",
"SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "L1 data cacheable reads and writes",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.CACHEABLE",
"SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "L1 data cache read in E state",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.E_STATE",
"SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "L1 data cache read in I state (misses)",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.I_STATE",
"SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "L1 data cache reads",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.MESI",
"SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "L1 data cache read in M state",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.M_STATE",
"SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "L1 data cache read in S state",
- "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.S_STATE",
"SampleAfterValue": "2000000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "L1 data cache load locks in E state",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.E_STATE",
"SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "L1 data cache load lock hits",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.HIT",
"SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "L1 data cache load locks in M state",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.M_STATE",
"SampleAfterValue": "2000000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "L1 data cache load locks in S state",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.S_STATE",
"SampleAfterValue": "2000000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "L1D load lock accepted in fill buffer",
- "Counter": "0,1",
"EventCode": "0x53",
"EventName": "L1D_CACHE_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -145,7 +127,6 @@
},
{
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
- "Counter": "0,1",
"EventCode": "0x52",
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -153,7 +134,6 @@
},
{
"BriefDescription": "L1 data cache stores in E state",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.E_STATE",
"SampleAfterValue": "2000000",
@@ -161,7 +141,6 @@
},
{
"BriefDescription": "L1 data cache stores in M state",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.M_STATE",
"SampleAfterValue": "2000000",
@@ -169,7 +148,6 @@
},
{
"BriefDescription": "L1 data cache stores in S state",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.S_STATE",
"SampleAfterValue": "2000000",
@@ -177,7 +155,6 @@
},
{
"BriefDescription": "L1D hardware prefetch misses",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.MISS",
"SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.REQUESTS",
"SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests triggered",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.TRIGGERS",
"SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.E_STATE",
"SampleAfterValue": "100000",
@@ -209,7 +183,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.I_STATE",
"SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
},
{
"BriefDescription": "All L1 writebacks to L2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.MESI",
"SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.M_STATE",
"SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.S_STATE",
"SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
},
{
"BriefDescription": "All L2 data requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.ANY",
"SampleAfterValue": "200000",
@@ -249,7 +218,6 @@
},
{
"BriefDescription": "L2 data demand loads in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -257,7 +225,6 @@
},
{
"BriefDescription": "L2 data demand loads in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -265,7 +232,6 @@
},
{
"BriefDescription": "L2 data demand requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -273,7 +239,6 @@
},
{
"BriefDescription": "L2 data demand loads in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
},
{
"BriefDescription": "L2 data demand loads in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
},
{
"BriefDescription": "L2 data prefetches in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
},
{
"BriefDescription": "L2 data prefetches in the I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
},
{
"BriefDescription": "All L2 data prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
},
{
"BriefDescription": "L2 data prefetches in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
},
{
"BriefDescription": "L2 data prefetches in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
},
{
"BriefDescription": "L2 lines alloacated",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ANY",
"SampleAfterValue": "100000",
@@ -337,7 +295,6 @@
},
{
"BriefDescription": "L2 lines allocated in the E state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E_STATE",
"SampleAfterValue": "100000",
@@ -345,7 +302,6 @@
},
{
"BriefDescription": "L2 lines allocated in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S_STATE",
"SampleAfterValue": "100000",
@@ -353,7 +309,6 @@
},
{
"BriefDescription": "L2 lines evicted",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.ANY",
"SampleAfterValue": "100000",
@@ -361,7 +316,6 @@
},
{
"BriefDescription": "L2 lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100000",
@@ -369,7 +323,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100000",
@@ -377,7 +330,6 @@
},
{
"BriefDescription": "L2 lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
"SampleAfterValue": "100000",
@@ -385,7 +337,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
"SampleAfterValue": "100000",
@@ -393,7 +344,6 @@
},
{
"BriefDescription": "L2 instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCHES",
"SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
},
{
"BriefDescription": "L2 instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_HIT",
"SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
},
{
"BriefDescription": "L2 instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_MISS",
"SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
},
{
"BriefDescription": "L2 load hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_HIT",
"SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
},
{
"BriefDescription": "L2 load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_MISS",
"SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
},
{
"BriefDescription": "L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LOADS",
"SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
},
{
"BriefDescription": "All L2 misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
},
{
"BriefDescription": "All L2 prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCHES",
"SampleAfterValue": "200000",
@@ -457,7 +400,6 @@
},
{
"BriefDescription": "L2 prefetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_HIT",
"SampleAfterValue": "200000",
@@ -465,7 +407,6 @@
},
{
"BriefDescription": "L2 prefetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_MISS",
"SampleAfterValue": "200000",
@@ -473,7 +414,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200000",
@@ -481,7 +421,6 @@
},
{
"BriefDescription": "L2 RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFOS",
"SampleAfterValue": "200000",
@@ -489,7 +428,6 @@
},
{
"BriefDescription": "L2 RFO hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200000",
@@ -497,7 +435,6 @@
},
{
"BriefDescription": "L2 RFO misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200000",
@@ -505,7 +442,6 @@
},
{
"BriefDescription": "All L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.ANY",
"SampleAfterValue": "200000",
@@ -513,7 +449,6 @@
},
{
"BriefDescription": "L2 fill transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.FILL",
"SampleAfterValue": "200000",
@@ -521,7 +456,6 @@
},
{
"BriefDescription": "L2 instruction fetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.IFETCH",
"SampleAfterValue": "200000",
@@ -529,7 +463,6 @@
},
{
"BriefDescription": "L1D writeback to L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.L1D_WB",
"SampleAfterValue": "200000",
@@ -537,7 +470,6 @@
},
{
"BriefDescription": "L2 Load transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.LOAD",
"SampleAfterValue": "200000",
@@ -545,7 +477,6 @@
},
{
"BriefDescription": "L2 prefetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.PREFETCH",
"SampleAfterValue": "200000",
@@ -553,7 +484,6 @@
},
{
"BriefDescription": "L2 RFO transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.RFO",
"SampleAfterValue": "200000",
@@ -561,7 +491,6 @@
},
{
"BriefDescription": "L2 writeback to LLC transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.WB",
"SampleAfterValue": "200000",
@@ -569,7 +498,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.E_STATE",
"SampleAfterValue": "100000",
@@ -577,7 +505,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.HIT",
"SampleAfterValue": "100000",
@@ -585,7 +512,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.I_STATE",
"SampleAfterValue": "100000",
@@ -593,7 +519,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.MESI",
"SampleAfterValue": "100000",
@@ -601,7 +526,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.M_STATE",
"SampleAfterValue": "100000",
@@ -609,7 +533,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.S_STATE",
"SampleAfterValue": "100000",
@@ -617,7 +540,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.HIT",
"SampleAfterValue": "100000",
@@ -625,7 +547,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.I_STATE",
"SampleAfterValue": "100000",
@@ -633,7 +554,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.MESI",
"SampleAfterValue": "100000",
@@ -641,7 +561,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.M_STATE",
"SampleAfterValue": "100000",
@@ -649,7 +568,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.S_STATE",
"SampleAfterValue": "100000",
@@ -657,7 +575,6 @@
},
{
"BriefDescription": "Longest latency cache miss",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100000",
@@ -665,7 +582,6 @@
},
{
"BriefDescription": "Longest latency cache reference",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200000",
@@ -673,18 +589,15 @@
},
{
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
"MSRIndex": "0x3F6",
- "MSRValue": "0x0",
"PEBS": "2",
"SampleAfterValue": "2000000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
"MSRIndex": "0x3F6",
@@ -695,7 +608,6 @@
},
{
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
"MSRIndex": "0x3F6",
@@ -706,7 +618,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
"MSRIndex": "0x3F6",
@@ -717,7 +628,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
"MSRIndex": "0x3F6",
@@ -728,7 +638,6 @@
},
{
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
"MSRIndex": "0x3F6",
@@ -739,7 +648,6 @@
},
{
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
"MSRIndex": "0x3F6",
@@ -750,7 +658,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
"MSRIndex": "0x3F6",
@@ -761,7 +668,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
"MSRIndex": "0x3F6",
@@ -772,7 +678,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
"MSRIndex": "0x3F6",
@@ -783,7 +688,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
"MSRIndex": "0x3F6",
@@ -794,7 +698,6 @@
},
{
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
"MSRIndex": "0x3F6",
@@ -805,7 +708,6 @@
},
{
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
"MSRIndex": "0x3F6",
@@ -816,7 +718,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
"MSRIndex": "0x3F6",
@@ -827,7 +728,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
"MSRIndex": "0x3F6",
@@ -838,7 +738,6 @@
},
{
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LOADS",
"PEBS": "1",
@@ -847,7 +746,6 @@
},
{
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.STORES",
"PEBS": "1",
@@ -856,7 +754,6 @@
},
{
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -865,7 +762,6 @@
},
{
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
"PEBS": "1",
@@ -874,7 +770,6 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
@@ -883,7 +778,6 @@
},
{
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -892,7 +786,6 @@
},
{
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
"PEBS": "1",
@@ -901,7 +794,6 @@
},
{
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
"PEBS": "1",
@@ -910,7 +802,6 @@
},
{
"BriefDescription": "Offcore L1 data cache writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
"SampleAfterValue": "100000",
@@ -918,7 +809,6 @@
},
{
"BriefDescription": "Offcore requests blocked due to Super Queue full",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
"SampleAfterValue": "100000",
@@ -926,2240 +816,1833 @@
},
{
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore data reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x111",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x211",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x411",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x711",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4711",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x144",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x244",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x444",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x744",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4744",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7FFF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFFFF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x80FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x2FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x7FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x47FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x18FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x38FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x10FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x8FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore RFO requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x122",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x222",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x422",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x722",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4722",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore writebacks",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x108",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x408",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x708",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4708",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code or data read requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x177",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x277",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x477",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x777",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4777",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any cache_dram",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any location",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x133",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x233",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x433",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x733",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache or dram",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4733",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x103",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x203",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x403",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x703",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4703",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x101",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x201",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x401",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x701",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4701",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand code reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x104",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x204",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x404",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x704",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4704",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand RFO requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x102",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x202",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x402",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x702",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4702",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore other requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x180",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x280",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x480",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x780",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4780",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F30",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch data requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF30",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x130",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x230",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x430",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x730",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4730",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch data reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x110",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x210",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x410",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x710",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4710",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch code reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x140",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x240",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x440",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x740",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4740",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch RFO requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x120",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x220",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x420",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x720",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4720",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x170",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x270",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x470",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x770",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4770",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Super Queue lock splits across a cache line",
- "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "2000000",
@@ -3167,7 +2650,6 @@
},
{
"BriefDescription": "Loads delayed with at-Retirement block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.AT_RET",
"SampleAfterValue": "200000",
@@ -3175,7 +2657,6 @@
},
{
"BriefDescription": "Cacheable loads delayed with L1D block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.L1D_BLOCK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
index 666e466d351c..c03f8990fa82 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "X87 Floating point assists (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.ALL",
"PEBS": "1",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.INPUT",
"PEBS": "1",
@@ -19,7 +17,6 @@
},
{
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.OUTPUT",
"PEBS": "1",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "MMX Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "SSE2 integer Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "SSE* FP double precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "SSE and SSE2 FP Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "SSE FP packed Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "SSE FP scalar Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "SSE* FP single precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Computational floating-point operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "All Floating Point to and from MMX transitions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Transitions from MMX to Floating Point instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Transitions from Floating Point to MMX instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "128 bit SIMD integer pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "128 bit SIMD integer arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "128 bit SIMD integer logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "128 bit SIMD integer multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "128 bit SIMD integer unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
index c561ac24d91d..f7f28510e3ae 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Macro-fused instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Two Uop instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json
index 6e95de3f3409..f810880a295e 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json
@@ -1,738 +1,604 @@
[
{
"BriefDescription": "Offcore data reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x60FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF8FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x40FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x20FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any LLC miss",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/other.json b/tools/perf/pmu-events/arch/x86/nehalemex/other.json
index f6887b234b0e..fb706cb51832 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/other.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "ES segment renames",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "I/O transactions",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1I instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1I instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1I Instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "Large ITLB hit",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "All loads dispatched",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "Loads dispatched from the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "Loads dispatched that bypass the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "Loads dispatched from stage 305",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "False dependencies due to partial address aliasing",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "All Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "Segment rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "Thread responded HIT to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "Thread responded HITE to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "Thread responded HITM to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "Super Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
index 6fc1a6efd8e8..c45f2ffa861e 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles the divider is busy",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Divide Operations executed",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -20,7 +18,6 @@
},
{
"BriefDescription": "Multiply operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.MUL",
"SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "BACLEAR asserted with bad target address",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.BAD_TARGET",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "BACLEAR asserted, regardless of cause",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.CLEAR",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "Instruction queue forced BACLEAR",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "BACLEAR_FORCE_IQ",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "Branch instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ANY",
"SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "Conditional branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.COND",
"SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT",
"SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Unconditional call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "Indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "Indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "Call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NEAR_CALLS",
"SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "All non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NON_CALLS",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "Indirect return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.RETURN_NEAR",
"SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "Taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "Retired branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -173,7 +152,6 @@
},
{
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -182,7 +160,6 @@
},
{
"BriefDescription": "Retired near call instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -191,7 +168,6 @@
},
{
"BriefDescription": "Mispredicted branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ANY",
"SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
},
{
"BriefDescription": "Mispredicted conditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.COND",
"SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
},
{
"BriefDescription": "Mispredicted unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT",
"SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
},
{
"BriefDescription": "Mispredicted indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
},
{
"BriefDescription": "Mispredicted indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
},
{
"BriefDescription": "Mispredicted call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
"SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NON_CALLS",
"SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
},
{
"BriefDescription": "Mispredicted return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
"SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
},
{
"BriefDescription": "Mispredicted taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN",
"SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
},
{
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -280,15 +246,11 @@
},
{
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 3",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.REF",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_P",
"SampleAfterValue": "100000",
@@ -296,33 +258,25 @@
},
{
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 2",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Total CPU cycles",
- "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
"Invert": "1",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Any Instruction Length Decoder stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.ANY",
"SampleAfterValue": "2000000",
@@ -330,7 +284,6 @@
},
{
"BriefDescription": "Instruction Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@@ -338,7 +291,6 @@
},
{
"BriefDescription": "Length Change Prefix stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000000",
@@ -346,7 +298,6 @@
},
{
"BriefDescription": "Stall cycles due to BPU MRU bypass",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.MRU",
"SampleAfterValue": "2000000",
@@ -354,7 +305,6 @@
},
{
"BriefDescription": "Regen stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.REGEN",
"SampleAfterValue": "2000000",
@@ -362,7 +312,6 @@
},
{
"BriefDescription": "Instructions that must be decoded by decoder 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "INST_DECODED.DEC0",
"SampleAfterValue": "2000000",
@@ -370,7 +319,6 @@
},
{
"BriefDescription": "Instructions written to instruction queue.",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INST_QUEUE_WRITES",
"SampleAfterValue": "2000000",
@@ -378,7 +326,6 @@
},
{
"BriefDescription": "Cycles instructions are written to the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "INST_QUEUE_WRITE_CYCLES",
"SampleAfterValue": "2000000",
@@ -386,15 +333,11 @@
},
{
"BriefDescription": "Instructions retired (fixed counter)",
- "Counter": "Fixed counter 1",
- "EventCode": "0x0",
"EventName": "INST_RETIRED.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@@ -403,7 +346,6 @@
},
{
"BriefDescription": "Retired MMX instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.MMX",
"PEBS": "1",
@@ -412,7 +354,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -423,7 +364,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -434,7 +374,6 @@
},
{
"BriefDescription": "Retired floating-point operations (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PEBS": "1",
@@ -443,7 +382,6 @@
},
{
"BriefDescription": "Load operations conflicting with software prefetches",
- "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE",
"SampleAfterValue": "200000",
@@ -451,7 +389,6 @@
},
{
"BriefDescription": "Cycles when uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.ACTIVE",
@@ -460,7 +397,6 @@
},
{
"BriefDescription": "Cycles no uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.INACTIVE",
@@ -470,7 +406,6 @@
},
{
"BriefDescription": "Loops that can't stream from the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "LSD_OVERFLOW",
"SampleAfterValue": "2000000",
@@ -478,7 +413,6 @@
},
{
"BriefDescription": "Cycles machine clear asserted",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "20000",
@@ -486,7 +420,6 @@
},
{
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEM_ORDER",
"SampleAfterValue": "20000",
@@ -494,7 +427,6 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20000",
@@ -502,7 +434,6 @@
},
{
"BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -510,7 +441,6 @@
},
{
"BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
@@ -518,7 +448,6 @@
},
{
"BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
@@ -526,7 +455,6 @@
},
{
"BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
@@ -534,7 +462,6 @@
},
{
"BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
@@ -542,7 +469,6 @@
},
{
"BriefDescription": "Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -550,7 +476,6 @@
},
{
"BriefDescription": "FPU control word write stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.FPCW",
"SampleAfterValue": "2000000",
@@ -558,7 +483,6 @@
},
{
"BriefDescription": "Load buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LOAD",
"SampleAfterValue": "2000000",
@@ -566,7 +490,6 @@
},
{
"BriefDescription": "MXCSR rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MXCSR",
"SampleAfterValue": "2000000",
@@ -574,7 +497,6 @@
},
{
"BriefDescription": "Other Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OTHER",
"SampleAfterValue": "2000000",
@@ -582,7 +504,6 @@
},
{
"BriefDescription": "ROB full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB_FULL",
"SampleAfterValue": "2000000",
@@ -590,7 +511,6 @@
},
{
"BriefDescription": "Reservation Station full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS_FULL",
"SampleAfterValue": "2000000",
@@ -598,7 +518,6 @@
},
{
"BriefDescription": "Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.STORE",
"SampleAfterValue": "2000000",
@@ -606,7 +525,6 @@
},
{
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
"PEBS": "1",
@@ -615,7 +533,6 @@
},
{
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
"PEBS": "1",
@@ -624,7 +541,6 @@
},
{
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
"PEBS": "1",
@@ -633,7 +549,6 @@
},
{
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
"PEBS": "1",
@@ -642,7 +557,6 @@
},
{
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
"PEBS": "1",
@@ -651,7 +565,6 @@
},
{
"BriefDescription": "Stack pointer instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_FOLDING",
"SampleAfterValue": "2000000",
@@ -659,7 +572,6 @@
},
{
"BriefDescription": "Stack pointer sync operations",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_SYNC",
"SampleAfterValue": "2000000",
@@ -667,7 +579,6 @@
},
{
"BriefDescription": "Uops decoded by Microcode Sequencer",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -676,7 +587,6 @@
},
{
"BriefDescription": "Cycles no Uops are decoded",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -687,7 +597,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -697,7 +606,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -707,7 +615,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -719,7 +626,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -731,7 +637,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -742,7 +647,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -752,7 +656,6 @@
},
{
"BriefDescription": "Uops executed on port 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT0",
"SampleAfterValue": "2000000",
@@ -760,7 +663,6 @@
},
{
"BriefDescription": "Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015",
"SampleAfterValue": "2000000",
@@ -768,7 +670,6 @@
},
{
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -778,7 +679,6 @@
},
{
"BriefDescription": "Uops executed on port 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT1",
"SampleAfterValue": "2000000",
@@ -787,7 +687,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops issued on ports 2, 3 or 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT234_CORE",
"SampleAfterValue": "2000000",
@@ -796,7 +695,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 2 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT2_CORE",
"SampleAfterValue": "2000000",
@@ -805,7 +703,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 3 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT3_CORE",
"SampleAfterValue": "2000000",
@@ -814,7 +711,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 4 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT4_CORE",
"SampleAfterValue": "2000000",
@@ -822,7 +718,6 @@
},
{
"BriefDescription": "Uops executed on port 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT5",
"SampleAfterValue": "2000000",
@@ -830,7 +725,6 @@
},
{
"BriefDescription": "Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000000",
@@ -839,7 +733,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops were issued on any thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -850,7 +743,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops were issued on either thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -859,7 +751,6 @@
},
{
"BriefDescription": "Fused Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.FUSED",
"SampleAfterValue": "2000000",
@@ -867,7 +758,6 @@
},
{
"BriefDescription": "Cycles no Uops were issued",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -877,7 +767,6 @@
},
{
"BriefDescription": "Cycles Uops are being retired",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -887,7 +776,6 @@
},
{
"BriefDescription": "Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "1",
@@ -896,7 +784,6 @@
},
{
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PEBS": "1",
@@ -905,7 +792,6 @@
},
{
"BriefDescription": "Retirement slots used (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -914,7 +800,6 @@
},
{
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -925,7 +810,6 @@
},
{
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -936,7 +820,6 @@
},
{
"BriefDescription": "Uop unfusions due to FP exceptions",
- "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UOP_UNFUSION",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
index e88c0802e679..c434cd4ef4f1 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "DTLB load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "DTLB load miss caused by low part of address",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "DTLB second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "DTLB load miss page walks complete",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "DTLB misses",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "DTLB first level misses but second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "DTLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "ITLB flushes",
- "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "ITLB miss",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "ITLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
@@ -90,7 +79,6 @@
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
@@ -99,7 +87,6 @@
},
{
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 23/32] perf vendor events intel: Refresh sandybridge metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (12 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 22/32] perf vendor events intel: Refresh nehalemex events Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 24/32] perf vendor events intel: Refresh sapphirerapids " Ian Rogers
` (8 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the sandybridge metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/sandybridge/cache.json | 441 ------------------
.../arch/x86/sandybridge/floating-point.json | 30 --
.../arch/x86/sandybridge/frontend.json | 64 ---
.../arch/x86/sandybridge/memory.json | 108 -----
.../arch/x86/sandybridge/other.json | 12 -
.../arch/x86/sandybridge/pipeline.json | 257 ----------
.../arch/x86/sandybridge/snb-metrics.json | 83 ++--
.../arch/x86/sandybridge/uncore-cache.json | 50 --
.../arch/x86/sandybridge/uncore-other.json | 28 +-
.../arch/x86/sandybridge/virtual-memory.json | 32 --
10 files changed, 57 insertions(+), 1048 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json
index a1d622352131..65696ea2a581 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Allocated L1D data cache lines in M state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.ALLOCATED_IN_M",
"SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.ALL_M_REPLACEMENT",
"SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
},
{
"BriefDescription": "L1D data cache lines in M state evicted due to replacement.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.EVICTION",
"SampleAfterValue": "2000003",
@@ -28,8 +22,6 @@
},
{
"BriefDescription": "L1D data line replacements.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xBF",
"EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES",
@@ -48,8 +38,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -58,8 +46,6 @@
},
{
"BriefDescription": "L1D miss oustandings duration in cycles.",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"SampleAfterValue": "2000003",
@@ -67,8 +53,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -78,8 +62,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -88,8 +70,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.ALL",
"SampleAfterValue": "200003",
@@ -97,8 +77,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_E",
"SampleAfterValue": "200003",
@@ -106,8 +84,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_M",
"SampleAfterValue": "200003",
@@ -115,8 +91,6 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_S",
"SampleAfterValue": "200003",
@@ -124,8 +98,6 @@
},
{
"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.MISS",
"SampleAfterValue": "200003",
@@ -133,8 +105,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
@@ -143,8 +113,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"SampleAfterValue": "100003",
@@ -152,8 +120,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"SampleAfterValue": "100003",
@@ -161,8 +127,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"SampleAfterValue": "100003",
@@ -170,8 +134,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100003",
@@ -179,8 +141,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100003",
@@ -188,8 +148,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines filling the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DIRTY_ALL",
"SampleAfterValue": "100003",
@@ -197,8 +155,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_CLEAN",
"SampleAfterValue": "100003",
@@ -206,8 +162,6 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_DIRTY",
"SampleAfterValue": "100003",
@@ -215,8 +169,6 @@
},
{
"BriefDescription": "L2 code requests.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"SampleAfterValue": "200003",
@@ -224,8 +176,6 @@
},
{
"BriefDescription": "Demand Data Read requests.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"SampleAfterValue": "200003",
@@ -233,8 +183,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"SampleAfterValue": "200003",
@@ -242,8 +190,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"SampleAfterValue": "200003",
@@ -251,8 +197,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
@@ -260,8 +204,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003",
@@ -269,8 +211,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"SampleAfterValue": "200003",
@@ -278,8 +218,6 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"SampleAfterValue": "200003",
@@ -287,8 +225,6 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"SampleAfterValue": "200003",
@@ -296,8 +232,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
@@ -305,8 +239,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003",
@@ -314,8 +246,6 @@
},
{
"BriefDescription": "RFOs that access cache lines in any state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.ALL",
"SampleAfterValue": "200003",
@@ -323,8 +253,6 @@
},
{
"BriefDescription": "RFOs that hit cache lines in E state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_E",
"SampleAfterValue": "200003",
@@ -332,8 +260,6 @@
},
{
"BriefDescription": "RFOs that hit cache lines in M state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
"SampleAfterValue": "200003",
@@ -341,8 +267,6 @@
},
{
"BriefDescription": "RFOs that miss cache lines.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.MISS",
"SampleAfterValue": "200003",
@@ -350,8 +274,6 @@
},
{
"BriefDescription": "L2 or LLC HW prefetches that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"SampleAfterValue": "200003",
@@ -359,8 +281,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"SampleAfterValue": "200003",
@@ -368,8 +288,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"SampleAfterValue": "200003",
@@ -377,8 +295,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"SampleAfterValue": "200003",
@@ -386,8 +302,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"SampleAfterValue": "200003",
@@ -395,8 +309,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"SampleAfterValue": "200003",
@@ -404,8 +316,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"SampleAfterValue": "200003",
@@ -413,8 +323,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"SampleAfterValue": "200003",
@@ -422,8 +330,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"SampleAfterValue": "2000003",
@@ -431,8 +337,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100003",
@@ -440,8 +344,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "100003",
@@ -449,8 +351,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
"PEBS": "1",
@@ -460,8 +360,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
@@ -471,8 +369,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
@@ -481,8 +377,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
@@ -491,8 +385,6 @@
},
{
"BriefDescription": "Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -502,8 +394,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -512,8 +402,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
@@ -522,8 +410,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
@@ -532,8 +418,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
"PEBS": "1",
@@ -543,8 +427,6 @@
},
{
"BriefDescription": "All retired load uops. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
@@ -554,8 +436,6 @@
},
{
"BriefDescription": "All retired store uops. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
@@ -565,8 +445,6 @@
},
{
"BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
@@ -575,8 +453,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
@@ -586,8 +462,6 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
@@ -597,8 +471,6 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
@@ -607,8 +479,6 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PEBS": "1",
@@ -617,8 +487,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"SampleAfterValue": "100003",
@@ -626,8 +494,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"SampleAfterValue": "100003",
@@ -635,8 +501,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"SampleAfterValue": "100003",
@@ -644,8 +508,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"SampleAfterValue": "100003",
@@ -653,8 +515,6 @@
},
{
"BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"SampleAfterValue": "2000003",
@@ -662,8 +522,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"SampleAfterValue": "2000003",
@@ -671,8 +529,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -681,8 +537,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -691,8 +545,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -701,8 +553,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"SampleAfterValue": "2000003",
@@ -710,8 +560,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6",
@@ -720,8 +568,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"SampleAfterValue": "2000003",
@@ -729,1148 +575,861 @@
},
{
"BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x000105B3",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch code reads that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0240",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0240",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0240",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0240",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0240",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch RFOs that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo references (demand & prefetch) .",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x000107F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c03f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch prefetch RFOs .",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "COREWB & ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10008",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10433",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data reads .",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data reads that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand rfo's .",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00010002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803c8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2380408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) data reads that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3f803c0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003c0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003c0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003c0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003c0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts non-temporal stores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json
index eb2ff2cfdf6b..8c2a246adef9 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles with any input/output SSE or FP assist.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"SampleAfterValue": "100003",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"SampleAfterValue": "100003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"SampleAfterValue": "100003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"SampleAfterValue": "100003",
@@ -47,8 +37,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@@ -56,8 +44,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"SampleAfterValue": "2000003",
@@ -65,8 +51,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
@@ -74,8 +58,6 @@
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"SampleAfterValue": "2000003",
@@ -83,8 +65,6 @@
},
{
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000003",
@@ -92,8 +72,6 @@
},
{
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"SampleAfterValue": "100003",
@@ -101,8 +79,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
@@ -110,8 +86,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
@@ -119,8 +93,6 @@
},
{
"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@@ -128,8 +100,6 @@
},
{
"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json
index e2c82e43a2de..69ab8d215f84 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.ALL_CANCEL",
"SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
},
{
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"SampleAfterValue": "2000003",
@@ -47,8 +37,6 @@
},
{
"BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.OTHER_CANCEL",
"SampleAfterValue": "2000003",
@@ -56,8 +44,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
@@ -65,8 +51,6 @@
},
{
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
@@ -75,8 +59,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -85,8 +67,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -95,8 +75,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -105,8 +83,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -115,8 +91,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -125,8 +99,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"SampleAfterValue": "2000003",
@@ -134,8 +106,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"SampleAfterValue": "2000003",
@@ -143,8 +113,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"SampleAfterValue": "2000003",
@@ -152,8 +120,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -162,8 +128,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"SampleAfterValue": "2000003",
@@ -171,8 +135,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -182,8 +144,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -192,8 +152,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -203,8 +161,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"SampleAfterValue": "2000003",
@@ -212,8 +168,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"SampleAfterValue": "2000003",
@@ -221,8 +175,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -232,8 +184,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"SampleAfterValue": "2000003",
@@ -241,8 +191,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
@@ -251,8 +199,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -261,8 +207,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -272,8 +216,6 @@
},
{
"BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
@@ -283,8 +225,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -293,8 +233,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -303,8 +241,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json
index 3c283ca309f3..0a6fc0136f4a 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -11,124 +9,94 @@
},
{
"BriefDescription": "Loads with latency value being above 128.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 16.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 32.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4 .",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 64.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8.",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
- "Counter": "3",
- "CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
"PEBS": "2",
- "PRECISE_STORE": "1",
"SampleAfterValue": "2000003",
- "TakenAlone": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"SampleAfterValue": "2000003",
@@ -136,8 +104,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"SampleAfterValue": "2000003",
@@ -145,298 +111,224 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400240",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400090",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3004003f7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80408fff",
- "Offcore": "1",
"PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts LLC replacements.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6004001b3",
- "Offcore": "1",
"PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x17004001b3",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x300400100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1f80400200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBE",
"EventName": "PAGE_WALKS.LLC_MISS",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/other.json b/tools/perf/pmu-events/arch/x86/sandybridge/other.json
index 2f873ab14156..9f96121baef8 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/other.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
@@ -30,8 +24,6 @@
},
{
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4E",
"EventName": "HW_PRE_REQ.DL1_MISS",
"SampleAfterValue": "2000003",
@@ -39,8 +31,6 @@
},
{
"BriefDescription": "Valid instructions written to IQ per cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x17",
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
"SampleAfterValue": "2000003",
@@ -48,8 +38,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
index 2c3b6c92aa6b..53ab5993e8b0 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB6",
"EventName": "AGU_BYPASS_CANCEL.COUNT",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Divide operations executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Cycles when divider is busy executing divide operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"SampleAfterValue": "2000003",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Speculative and retired branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
@@ -40,8 +32,6 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -49,8 +39,6 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"SampleAfterValue": "200003",
@@ -58,8 +46,6 @@
},
{
"BriefDescription": "Speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -67,8 +53,6 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -76,8 +60,6 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -85,8 +67,6 @@
},
{
"BriefDescription": "Not taken macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -94,8 +74,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -103,8 +81,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"SampleAfterValue": "200003",
@@ -112,8 +88,6 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -121,8 +95,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -130,8 +102,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -139,8 +109,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -148,16 +116,12 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -166,8 +130,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -176,8 +138,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"SampleAfterValue": "100007",
@@ -185,8 +145,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -195,8 +153,6 @@
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
@@ -205,8 +161,6 @@
},
{
"BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -215,8 +169,6 @@
},
{
"BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -225,8 +177,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"SampleAfterValue": "400009",
@@ -234,8 +184,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"SampleAfterValue": "200003",
@@ -243,8 +191,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -252,8 +198,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -261,8 +205,6 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -270,8 +212,6 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -279,8 +219,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
@@ -288,8 +226,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -297,8 +233,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
@@ -306,8 +240,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -315,8 +247,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"SampleAfterValue": "200003",
@@ -324,27 +254,20 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
- "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
"SampleAfterValue": "400009",
"UMask": "0x4"
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -353,8 +276,6 @@
},
{
"BriefDescription": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -363,8 +284,6 @@
},
{
"BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NOT_TAKEN",
"PEBS": "1",
@@ -373,8 +292,6 @@
},
{
"BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN",
"PEBS": "1",
@@ -383,8 +300,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -392,8 +307,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "2000003",
@@ -402,8 +315,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -411,8 +322,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -420,8 +329,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -429,19 +336,14 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
- "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -449,8 +351,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -459,16 +359,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003"
@@ -476,16 +372,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -494,8 +386,6 @@
},
{
"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -504,8 +394,6 @@
},
{
"BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",
@@ -514,8 +402,6 @@
},
{
"BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -524,8 +410,6 @@
},
{
"BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -534,8 +418,6 @@
},
{
"BriefDescription": "Stall cycles because IQ is full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000003",
@@ -543,8 +425,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000003",
@@ -552,8 +432,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
"SampleAfterValue": "2000003",
@@ -561,27 +439,20 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Instructions retired. (Precise Event - PEBS).",
- "Counter": "1",
- "CounterHTOff": "1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "2",
"SampleAfterValue": "2000003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RAT_STALL_CYCLES",
"SampleAfterValue": "2000003",
@@ -589,8 +460,6 @@
},
{
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -600,8 +469,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -610,8 +477,6 @@
},
{
"BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x0D",
@@ -621,8 +486,6 @@
},
{
"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"SampleAfterValue": "100003",
@@ -630,8 +493,6 @@
},
{
"BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"SampleAfterValue": "100003",
@@ -639,8 +500,6 @@
},
{
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003",
@@ -648,8 +507,6 @@
},
{
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
@@ -658,8 +515,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.",
@@ -668,8 +523,6 @@
},
{
"BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",
"SampleAfterValue": "100003",
@@ -677,8 +530,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"SampleAfterValue": "100003",
@@ -686,8 +537,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"SampleAfterValue": "100003",
@@ -695,8 +544,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -705,8 +552,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -715,8 +560,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
@@ -724,8 +567,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
@@ -735,8 +576,6 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -745,8 +584,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
@@ -755,8 +592,6 @@
},
{
"BriefDescription": "Retired instructions experiencing ITLB misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",
"SampleAfterValue": "100003",
@@ -764,8 +599,6 @@
},
{
"BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",
"SampleAfterValue": "2000003",
@@ -773,8 +606,6 @@
},
{
"BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",
@@ -784,8 +615,6 @@
},
{
"BriefDescription": "Multiply packed/scalar single precision uops allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",
"SampleAfterValue": "2000003",
@@ -793,8 +622,6 @@
},
{
"BriefDescription": "Cycles with at least one slow LEA uop being allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",
"PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
@@ -803,8 +630,6 @@
},
{
"BriefDescription": "Resource-related stall cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000003",
@@ -812,8 +637,6 @@
},
{
"BriefDescription": "Counts the cycles of stall due to lack of load buffers.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LB",
"SampleAfterValue": "2000003",
@@ -821,8 +644,6 @@
},
{
"BriefDescription": "Resource stalls due to load or store buffers all being in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LB_SB",
"SampleAfterValue": "2000003",
@@ -830,8 +651,6 @@
},
{
"BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MEM_RS",
"SampleAfterValue": "2000003",
@@ -839,8 +658,6 @@
},
{
"BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OOO_RSRC",
"SampleAfterValue": "2000003",
@@ -848,8 +665,6 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
@@ -857,8 +672,6 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
@@ -866,8 +679,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"SampleAfterValue": "2000003",
@@ -875,8 +686,6 @@
},
{
"BriefDescription": "Cycles with either free list is empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",
"SampleAfterValue": "2000003",
@@ -884,8 +693,6 @@
},
{
"BriefDescription": "Resource stalls2 control structures full for physical registers.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",
"SampleAfterValue": "2000003",
@@ -893,8 +700,6 @@
},
{
"BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.BOB_FULL",
"SampleAfterValue": "2000003",
@@ -902,8 +707,6 @@
},
{
"BriefDescription": "Resource stalls out of order resources full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5B",
"EventName": "RESOURCE_STALLS2.OOO_RSRC",
"SampleAfterValue": "2000003",
@@ -911,8 +714,6 @@
},
{
"BriefDescription": "Count cases of saving new LBR.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"SampleAfterValue": "2000003",
@@ -920,8 +721,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"SampleAfterValue": "2000003",
@@ -929,8 +728,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -941,8 +738,6 @@
},
{
"BriefDescription": "Uops dispatched from any thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_DISPATCHED.CORE",
"SampleAfterValue": "2000003",
@@ -950,8 +745,6 @@
},
{
"BriefDescription": "Uops dispatched per thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_DISPATCHED.THREAD",
"SampleAfterValue": "2000003",
@@ -959,8 +752,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"SampleAfterValue": "2000003",
@@ -969,8 +760,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
@@ -978,8 +767,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"SampleAfterValue": "2000003",
@@ -988,8 +775,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
@@ -997,8 +782,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue": "2000003",
@@ -1007,8 +790,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -1016,8 +797,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue": "2000003",
@@ -1026,8 +805,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
@@ -1035,8 +812,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue": "2000003",
@@ -1045,8 +820,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
@@ -1054,8 +827,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue": "2000003",
@@ -1064,8 +835,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
@@ -1073,8 +842,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1083,8 +850,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1093,8 +858,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1103,8 +866,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1113,8 +874,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
@@ -1123,8 +882,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
@@ -1134,8 +891,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1145,8 +900,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1156,8 +909,6 @@
},
{
"BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@@ -1167,8 +918,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1178,8 +927,6 @@
},
{
"BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -1189,8 +936,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1200,8 +945,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
index 5d5a6d6f3bda..a7b3c835b03d 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
@@ -65,7 +65,7 @@
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -73,7 +73,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -97,7 +97,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+ "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -113,7 +113,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -121,7 +121,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+ "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -169,7 +169,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS",
+ "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -233,7 +233,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -284,19 +284,19 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
+ "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_DISPATCHED.THREAD / ((cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
+ "MetricExpr": "UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
@@ -314,25 +314,25 @@
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1000000000) / duration_time",
+ "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -345,7 +345,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@@ -363,68 +363,87 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+ "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+ "MetricExpr": "MEM_Parallel_Requests",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Request_Latency"
},
{
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+ "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests"
},
+ {
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "UNC_CLOCK.SOCKET",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
+ },
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
+ {
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
+ },
{
"BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
index 6b0639944d78..c538557ba4c0 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
@@ -1,251 +1,201 @@
[
{
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"UMask": "0x86",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"UMask": "0x8f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
"UMask": "0x46",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
"UMask": "0x41",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
"UMask": "0x4f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"UMask": "0x16",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"UMask": "0x18",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
"UMask": "0x11",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"UMask": "0x1f",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"UMask": "0x26",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
- "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"UMask": "0x2f",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
"UMask": "0x88",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"PerPkg": "1",
- "PublicDescription": "An external snoop hits a modified line in some processor core.",
"UMask": "0x28",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
"UMask": "0x84",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"PerPkg": "1",
- "PublicDescription": "An external snoop hits a non-modified line in some processor core.",
"UMask": "0x24",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"UMask": "0x44",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "An external snoop misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"PerPkg": "1",
- "PublicDescription": "An external snoop misses in some processor core.",
"UMask": "0x21",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"UMask": "0x41",
"Unit": "CBO"
}
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json
index 88f1e326205f..c3252c094a9c 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json
@@ -4,18 +4,15 @@
"EventCode": "0x83",
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
- "Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
- "PublicDescription": "Number of requests allocated in Coherency Tracker.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
@@ -23,69 +20,56 @@
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "Counter": "0,1",
"CounterMask": "10",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
"PerPkg": "1",
- "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "Counter": "0,1",
"CounterMask": "1",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
- "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
- "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of LLC evictions allocated.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
"PerPkg": "1",
- "PublicDescription": "Counts the number of LLC evictions allocated.",
"UMask": "0x80",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
- "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
"UMask": "0x20",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
- "Counter": "Fixed",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",
- "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Unit": "ARB"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
index 98362abba1a7..fa08d355b97e 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -29,8 +23,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
@@ -39,8 +31,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
@@ -48,8 +38,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -57,8 +45,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -66,8 +52,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
@@ -75,8 +59,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
@@ -84,8 +66,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"SampleAfterValue": "100007",
@@ -93,8 +73,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
@@ -102,8 +80,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -111,8 +87,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
@@ -120,8 +94,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
@@ -130,8 +102,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"SampleAfterValue": "100007",
@@ -139,8 +109,6 @@
},
{
"BriefDescription": "STLB flush attempts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"SampleAfterValue": "100007",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 24/32] perf vendor events intel: Refresh sapphirerapids metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (13 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 23/32] perf vendor events intel: Refresh sandybridge metrics and events Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 25/32] perf vendor events intel: Refresh silvermont events Ian Rogers
` (7 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the sapphirerapids metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated to 1.09,
in particular uncore, with fixes to uncore events and improved
descriptions. The formatting changes increase consistency across the
json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
.../arch/x86/sapphirerapids/cache.json | 350 +-
.../x86/sapphirerapids/floating-point.json | 63 -
.../arch/x86/sapphirerapids/frontend.json | 144 -
.../arch/x86/sapphirerapids/memory.json | 125 +-
.../arch/x86/sapphirerapids/other.json | 91 +-
.../arch/x86/sapphirerapids/pipeline.json | 424 +-
.../arch/x86/sapphirerapids/spr-metrics.json | 2309 +++---
.../x86/sapphirerapids/uncore-memory.json | 526 +-
.../arch/x86/sapphirerapids/uncore-other.json | 6606 ++++++++---------
.../arch/x86/sapphirerapids/uncore-power.json | 84 +-
.../x86/sapphirerapids/virtual-memory.json | 80 -
12 files changed, 4483 insertions(+), 6321 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 84f74acf91d9..a5de68bcebcd 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -21,7 +21,7 @@ GenuineIntel-6-A[AC],v1.00,meteorlake,core
GenuineIntel-6-1[AEF],v3,nehalemep,core
GenuineIntel-6-2E,v3,nehalemex,core
GenuineIntel-6-2A,v17,sandybridge,core
-GenuineIntel-6-8F,v1.06,sapphirerapids,core
+GenuineIntel-6-8F,v1.09,sapphirerapids,core
GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core
GenuineIntel-6-55-[01234],v1.28,skylakex,core
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
index c05c741e22db..92a605ecac6e 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
@@ -1,1192 +1,898 @@
[
{
"BriefDescription": "L1D.HWPF_MISS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.HWPF_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
+ "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "Deprecated": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALLS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of L1D misses that are outstanding",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "L2 cache lines filling L2",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "L2_LINES_IN.ALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1f"
},
{
"BriefDescription": "L2_LINES_OUT.NON_SILENT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.NON_SILENT",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SILENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.USELESS_HWPF",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.ALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.REFERENCES]",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xff"
},
{
"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.MISS]",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x3f"
},
{
"BriefDescription": "L2 code requests",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of L2 code requests.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe4"
},
{
"BriefDescription": "Demand Data Read access L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe1"
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand requests that miss L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x27"
},
{
"BriefDescription": "Demand requests to L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand requests to L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe7"
},
{
"BriefDescription": "L2_RQSTS.ALL_HWPF",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_HWPF",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xf0"
},
{
"BriefDescription": "RFO requests to L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe2"
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc4"
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x24"
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc1"
},
{
"BriefDescription": "Demand Data Read miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x21"
},
{
"BriefDescription": "L2_RQSTS.HWPF_MISS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.HWPF_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x30"
},
{
"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.MISS]",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x3f"
},
{
"BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.ALL]",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xff"
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc2"
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x22"
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc8"
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x28"
},
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x41"
},
{
"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4f"
},
{
"BriefDescription": "Retired load instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
"SampleAfterValue": "1000003",
"UMask": "0x81"
},
{
"BriefDescription": "Retired store instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired store instructions.",
"SampleAfterValue": "1000003",
"UMask": "0x82"
},
{
"BriefDescription": "All retired memory instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ANY",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired memory instructions - loads and stores.",
"SampleAfterValue": "1000003",
"UMask": "0x83"
},
{
"BriefDescription": "Retired load instructions with locked access.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with locked access.",
"SampleAfterValue": "100007",
"UMask": "0x21"
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x41"
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x11"
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x12"
},
{
"BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0xfd"
},
{
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
"SampleAfterValue": "20011",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
- "PEBScounters": "0,1,2,3",
+ "PEBS": "1",
"PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
- "PEBScounters": "0,1,2,3",
+ "PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
- "PEBScounters": "0,1,2,3",
+ "PEBS": "1",
"PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
- "PEBScounters": "0,1,2,3",
+ "PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
- "BriefDescription": "Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches.",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3.",
+ "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3.",
"SampleAfterValue": "100007",
"UMask": "0x10"
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).",
"SampleAfterValue": "100007",
"UMask": "0x4"
},
{
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
"SampleAfterValue": "100021",
"UMask": "0x10"
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
"SampleAfterValue": "100021",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
"SampleAfterValue": "50021",
"UMask": "0x20"
},
{
- "BriefDescription": "Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches.",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3.",
+ "PEBS": "1",
+ "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3.",
"SampleAfterValue": "1000003",
"UMask": "0x80"
},
{
"BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "MEM_STORE_RETIRED.L2_HIT",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Retired memory uops for any access",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe5",
"EventName": "MEM_UOP_RETIRED.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",
"SampleAfterValue": "1000003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80082380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F003C4477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C4477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C4477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C4477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1830004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.RFO_TO_CORE.L3_HIT_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F80040022",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Demand and prefetch data reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "Deprecated": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
+ {
+ "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
+ "CounterMask": "1",
+ "EventCode": "0x20",
+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
+ {
+ "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
+ "EventCode": "0x20",
+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
+ "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.NTA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.T0",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json
index 32074d455691..01baea3df562 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json
@@ -1,222 +1,159 @@
[
{
"BriefDescription": "ARITH.FPDIV_ACTIVE",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb0",
"EventName": "ARITH.FPDIV_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all microcode FP assists.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.FP",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all microcode Floating Point assists.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "ASSISTS.SSE_AVX_MIX",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.SSE_AVX_MIX",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_0",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_5",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
"SampleAfterValue": "100003",
"UMask": "0x3"
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
"SampleAfterValue": "100003",
"UMask": "0x1c"
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json
index ff0d47ce8e9a..2c7c617f27ed 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json
@@ -1,498 +1,354 @@
[
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "DECODE.LCP",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles the Microcode Sequencer is busy.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "DECODE.MS_BUSY",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x11",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x14",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x600106",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
"MSRValue": "0x608006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
"MSRValue": "0x601006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x600206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
"MSRValue": "0x610006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x100206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
"MSRValue": "0x602006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
"MSRValue": "0x600406",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
"MSRValue": "0x620006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x604006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
"MSRValue": "0x600806",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.MS_FLOWS",
"MSRIndex": "0x3F7",
"MSRValue": "0x8",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x15",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
"MSRIndex": "0x3F7",
"MSRValue": "0x17",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE_DATA.STALLS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_TAG.STALLS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles DSB is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Number of switches from DSB or MITE to the MS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Uops delivered to IDQ while MS is busy",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS).",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json
index 6e761b628ca4..b72a36999930 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json
@@ -1,207 +1,150 @@
[
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x6"
},
{
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x3"
},
{
"BriefDescription": "MEMORY_ACTIVITY.STALLS_L2_MISS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x5"
},
{
"BriefDescription": "MEMORY_ACTIVITY.STALLS_L3_MISS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "9",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x9"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
- "CollectPEBSRecord": "2",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
@@ -212,225 +155,187 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94002380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84002380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC04477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F04C04477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70CC04477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts demand data read requests that miss the L3 cache.",
+ "EventCode": "0x21",
+ "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
+ "SampleAfterValue": "100003",
+ "UMask": "0x10"
+ },
+ {
+ "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
+ "EventCode": "0x20",
+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
+ "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x10"
+ },
{
"BriefDescription": "Number of times an RTM execution aborted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM abort was triggered.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM commit succeeded.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_READ",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json
index 95dbef8ae80a..5d4c15dbf4d3 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json
@@ -1,428 +1,341 @@
[
{
"BriefDescription": "ASSISTS.PAGE_FAULT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.PAGE_FAULT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb7",
"EventName": "EXE.AMX_BUSY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data load hardware prefetch requests to the L1 data cache that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L1D.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches (which bring data to L2) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L2.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10070",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x12380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90002380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10808",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC4477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70C004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700C04477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F33004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x733004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708004477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.WRITE_ESTIMATE.MEMORY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFBFF80822",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa5",
"EventName": "RS.EMPTY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xa5",
"EventName": "RS.EMPTY_COUNT",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
+ "Deprecated": "1",
"EdgeDetect": "1",
"EventCode": "0xa5",
"EventName": "RS_EMPTY.COUNT",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
+ "Deprecated": "1",
"EventCode": "0xa5",
"EventName": "RS_EMPTY.CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "XQ.FULL_CYCLES",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x2d",
"EventName": "XQ.FULL_CYCLES",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json
index b2f0d9393d3c..ceb14181ebc8 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json
@@ -15,1357 +15,945 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
+ "Deprecated": "1",
"EventCode": "0xb0",
"EventName": "ARITH.DIVIDER_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x9"
},
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb0",
"EventName": "ARITH.DIV_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x9"
},
{
"BriefDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
+ "Deprecated": "1",
"EventCode": "0xb0",
"EventName": "ARITH.FP_DIVIDER_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "This event counts the cycles the integer divider is busy.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb0",
"EventName": "ARITH.IDIV_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
+ "Deprecated": "1",
"EventCode": "0xb0",
"EventName": "ARITH.INT_DIVIDER_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1b"
},
{
"BriefDescription": "All branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all branch instructions retired.",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x11"
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts not taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x10"
},
{
"BriefDescription": "Taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x1"
},
{
"BriefDescription": "Far branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts far branch instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Indirect near branch instructions retired (excluding returns)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts both direct and indirect near call instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"BriefDescription": "Return instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts return instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"BriefDescription": "Taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x20"
},
{
"BriefDescription": "All mispredicted branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts mispredicted conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x11"
},
{
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
"SampleAfterValue": "400009",
"UMask": "0x10"
},
{
"BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x1"
},
{
"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Mispredicted indirect CALL retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
"SampleAfterValue": "400009",
"UMask": "0x2"
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
"SampleAfterValue": "400009",
"UMask": "0x20"
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.C01",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.C02",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.C0_WAIT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x70"
},
{
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"SampleAfterValue": "25003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "CPU_CLK_UNHALTED.PAUSE",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.PAUSE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.PAUSE_INST",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PEBScounters": "34",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x3"
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
- "SampleAfterValue": "2000003",
- "Speculative": "1"
+ "SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "8",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "12",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0xc"
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x5"
},
{
"BriefDescription": "Total execution stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.BOUND_ON_LOADS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x21"
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "INST_DECODED.DECODERS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "INST_RETIRED.MACRO_FUSED",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.MACRO_FUSED",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Retired NOP instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.NOP",
- "PEBScounters": "1,2,3,4,5,6,7",
"PublicDescription": "Counts all retired NOP or ENDBR32/64 instructions",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Precise instruction retired with PEBS precise-distribution",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "INST_RETIRED.REP_ITERATION",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.REP_ITERATION",
- "PEBScounters": "1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "INT_MISC.MBA_STALLS",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.MBA_STALLS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.RECOVERY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
"MSRIndex": "0x3F7",
"MSRValue": "0x7",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
- "TakenAlone": "1",
"UMask": "0x40"
},
{
"BriefDescription": "TMA slots where uops got dropped",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.UOP_DROPPING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "INT_VEC_RETIRED.128BIT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.128BIT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x13"
},
{
"BriefDescription": "INT_VEC_RETIRED.256BIT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.256BIT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0xac"
},
{
"BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.ADD_128",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.",
"SampleAfterValue": "1000003",
"UMask": "0x3"
},
{
"BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.ADD_256",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.",
"SampleAfterValue": "1000003",
"UMask": "0xc"
},
{
"BriefDescription": "INT_VEC_RETIRED.MUL_256",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.MUL_256",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x80"
},
{
"BriefDescription": "INT_VEC_RETIRED.SHUFFLES",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.SHUFFLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "INT_VEC_RETIRED.VNNI_128",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.VNNI_128",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "INT_VEC_RETIRED.VNNI_256",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.VNNI_256",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x20"
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ADDRESS_ALIAS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x88"
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x82"
},
{
"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_OK",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.COUNT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of machine clears (nukes) of any type.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "MISC2_RETIRED.LFENCE",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe0",
"EventName": "MISC2_RETIRED.LFENCE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "400009",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.LBR_INSERTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SB",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SCOREBOARD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "TMA slots wasted due to incorrect speculations.",
- "CollectPEBSRecord": "2",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BAD_SPEC_SLOTS",
"PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
- "CollectPEBSRecord": "2",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
"PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of specualtive operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.MEMORY_BOUND_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 3",
"EventName": "TOPDOWN.SLOTS",
- "PEBScounters": "35",
"PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.SLOTS_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "UOPS_DECODED.DEC0_UOPS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UOPS_DECODED.DEC0_UOPS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Uops executed on port 0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_0",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of uops dispatch to execution port 0.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Uops executed on port 1",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of uops dispatch to execution port 1.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Uops executed on ports 2, 3 and 10",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_2_3_10",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Uops executed on ports 4 and 9",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_4_9",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of uops dispatch to execution ports 4 and 9",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Uops executed on ports 5 and 11",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_5_11",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of uops dispatch to execution ports 5 and 11",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Uops executed on port 6",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_6",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of uops dispatch to execution port 6.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Uops executed on ports 7 and 8",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_7_8",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of uops dispatch to execution ports 7 and 8.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Number of uops executed on the core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops executed from any thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.STALLS",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
+ "Deprecated": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.THREAD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.X87",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of x87 uops executed.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Uops that RAT issues to RS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xae",
"EventName": "UOPS_ISSUED.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with retired uop(s).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles where at least one uop has retired.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Retired uops except the last uop of each instruction.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.HEAVY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "UOPS_RETIRED.MS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MS",
"MSRIndex": "0x3F7",
"MSRValue": "0x8",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "TakenAlone": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Retirement slots used.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the retirement slots used each cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.STALLS",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts cycles without actually retired uops.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
+ "Deprecated": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x2"
}
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
index 9ec42a68c160..ce18fc458e37 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
@@ -1,1643 +1,1616 @@
[
{
- "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
- "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS",
- "MetricGroup": "PGO;TopdownL1;tma_L1_group",
- "MetricName": "tma_frontend_bound",
- "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+ "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "Mispredictions"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
- "MetricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS)",
- "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_latency",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "Memory_Bandwidth"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
- "MetricExpr": "ICACHE_DATA.STALLS / CLKS",
- "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_icache_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))",
+ "MetricGroup": "Mem;MemoryLat;Offcore",
+ "MetricName": "Memory_Latency"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
- "MetricExpr": "ICACHE_TAG.STALLS / CLKS",
- "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_itlb_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
+ "MetricGroup": "Mem;MemoryTLB;Offcore",
+ "MetricName": "Memory_Data_TLBs"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
- "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_branch_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
+ "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
+ "MetricGroup": "Ret",
+ "MetricName": "Branching_Overhead"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
- "MetricExpr": "(tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_mispredicts_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+ "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+ "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
+ "MetricName": "Big_Code"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
- "MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_clears_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+ "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
+ "MetricGroup": "Fed;FetchBW;Frontend",
+ "MetricName": "Instruction_Fetch_BW"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
- "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / CLKS",
- "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_unknown_branches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+ "MetricExpr": "INST_RETIRED.ANY / CLKS",
+ "MetricGroup": "Ret;Summary",
+ "MetricName": "IPC"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
- "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_dsb_switches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uops Per Instruction",
+ "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "UPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
- "MetricExpr": "DECODE.LCP / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_lcp",
- "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW",
+ "MetricName": "UpTB"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
- "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS",
- "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_ms_switches",
- "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+ "MetricExpr": "1 / IPC",
+ "MetricGroup": "Mem;Pipeline",
+ "MetricName": "CPI"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
- "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
- "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_bandwidth",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "Pipeline",
+ "MetricName": "CLKS"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
- "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_mite",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+ "MetricExpr": "TOPDOWN.SLOTS",
+ "MetricGroup": "tma_L1_group",
+ "MetricName": "SLOTS"
},
{
- "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
- "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
- "MetricName": "tma_decoder0_alone",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
+ "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
+ "MetricGroup": "SMT;tma_L1_group",
+ "MetricName": "Slots_Utilization"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
- "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2",
- "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_dsb",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of Executed- by Issued-Uops",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+ "MetricGroup": "Cor;Pipeline",
+ "MetricName": "Execute_per_Issue",
+ "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
},
{
- "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_bad_speculation",
- "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+ "MetricGroup": "Ret;SMT;tma_L1_group",
+ "MetricName": "CoreIPC"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_branch_mispredicts",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Floating Point Operations Per Cycle",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / CORE_CLKS",
+ "MetricGroup": "Flops;Ret",
+ "MetricName": "FLOPc"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
- "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
- "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_machine_clears",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+ "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * CORE_CLKS)",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "FP_Arith_Utilization",
+ "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
- "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_backend_bound",
- "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+ "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+ "MetricName": "ILP"
},
{
- "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
- "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_memory_bound",
- "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+ "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "Core_Bound_Likely"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
- "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l1_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+ "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "SMT",
+ "MetricName": "CORE_CLKS"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
- "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_dtlb_load",
- "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+ "MetricGroup": "InsType",
+ "MetricName": "IpLoad"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+ "MetricGroup": "InsType",
+ "MetricName": "IpStore"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Fed;InsType",
+ "MetricName": "IpBranch"
},
{
- "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
- "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_store_fwd_blk",
- "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "IpCall"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
- "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_lock_latency",
- "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+ "MetricName": "IpTB"
},
{
- "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
- "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_split_loads",
- "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch instructions per taken branch. ",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "BpTkBranch"
},
{
- "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
- "MetricExpr": "L1D_PEND_MISS.FB_FULL / CLKS",
- "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_fb_full",
- "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16)",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpFLOP"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l2_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR))",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpArith",
+ "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l3_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_SP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "((25 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (24 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_contested_accesses",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_DP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "(24 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_data_sharing",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX128",
+ "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "(9 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_l3_hit_latency",
- "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX256",
+ "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_sq_full",
- "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX512",
+ "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "((MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS) - tma_pmm_bound)",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_dram_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.BF16",
+ "MetricGroup": "Flops;FpVector;InsType;Server",
+ "MetricName": "IpArith_AMX_F16",
+ "PublicDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions."
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_bandwidth",
- "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.INT8",
+ "MetricGroup": "InsType;IntVector;Server",
+ "MetricName": "IpArith_AMX_Int8",
+ "PublicDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions."
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).",
- "MetricExpr": "INT_MISC.MBA_STALLS / CLKS",
- "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_mem_bandwidth_group",
- "MetricName": "tma_mba_stalls",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+ "MetricGroup": "Prefetches",
+ "MetricName": "IpSWPF"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_latency",
- "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+ "MetricExpr": "INST_RETIRED.ANY",
+ "MetricGroup": "Summary;tma_L1_group",
+ "MetricName": "Instructions"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
- "MetricExpr": "(54.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_local_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+ "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "Retire"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
- "MetricExpr": "(119 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
+ "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "Strings_Cycles"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
- "MetricExpr": "((108 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (108 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_cache",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / cpu@ASSISTS.ANY\\,umask\\=0x1B@",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "IpAssist"
},
{
- "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
- "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) / ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))))) * (MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS)) if (1000000 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS) else 0)",
- "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_pmm_bound",
- "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
- "ScaleUnit": "100%"
+ "BriefDescription": "",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+ "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+ "MetricName": "Execute"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
- "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_store_bound",
- "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+ "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "Fetch_UpC"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((MEM_STORE_RETIRED.L2_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_store_latency",
- "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+ "MetricGroup": "DSB;Fed;FetchBW",
+ "MetricName": "DSB_Coverage"
},
{
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "(28 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
+ "MetricGroup": "DSBmiss",
+ "MetricName": "DSB_Switch_Cost"
+ },
+ {
+ "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
+ "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "DSB_Misses"
},
{
- "BriefDescription": "This metric represents rate of split store accesses",
- "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
- "MetricGroup": "TopdownL4;tma_store_bound_group",
- "MetricName": "tma_split_stores",
- "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "IpDSB_Miss_Ret"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
- "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_streaming_stores",
- "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "IpMispredict"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
- "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_dtlb_store",
- "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "Branch_Misprediction_Cost"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are non-taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_NT"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_TK"
},
{
- "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
- "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
- "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_core_bound",
- "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are CALL or RET",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "CallRet"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
- "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS",
- "MetricGroup": "TopdownL3;tma_core_bound_group",
- "MetricName": "tma_divider",
- "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "Jump"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
- "MetricName": "tma_ports_utilization",
- "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
+ "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "Other_Branches"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_0",
- "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY",
+ "MetricGroup": "Mem;MemoryBound;MemoryLat",
+ "MetricName": "Load_Miss_Real_Latency"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
- "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_serializing_operation",
- "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD",
- "ScaleUnit": "100%"
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+ "MetricGroup": "Mem;MemoryBW;MemoryBound",
+ "MetricName": "MLP"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions",
- "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / CLKS",
- "MetricGroup": "TopdownL6;tma_serializing_operation_group",
- "MetricName": "tma_slow_pause",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.",
- "MetricExpr": "13 * MISC2_RETIRED.LFENCE / CLKS",
- "MetricGroup": "TopdownL6;tma_serializing_operation_group",
- "MetricName": "tma_memory_fence",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI_Load"
},
{
- "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
- "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_mixing_vectors",
- "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Backend;CacheMisses;Mem",
+ "MetricName": "L2MPKI"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix Extensions (AMX) execution engine was busy with tile (arithmetic) operations",
- "MetricExpr": "EXE.AMX_BUSY / CORE_CLKS",
- "MetricGroup": "Compute;HPC;Server;TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_amx_busy",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem;Offcore",
+ "MetricName": "L2MPKI_All"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_1",
- "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2MPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_2",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_All"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_3m",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_Load"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_alu_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L3MPKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED.PORT_0",
- "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CORE_CLKS",
- "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_0",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "FB_HPKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED.PORT_1",
- "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_1",
- "ScaleUnit": "100%"
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+ "MetricConstraint": "NO_NMI_WATCHDOG",
+ "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * CORE_CLKS)",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "Page_Walks_Utilization"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED.PORT_6",
- "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_6",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3_10",
- "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_load_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8",
- "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_store_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW"
},
{
- "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_retiring",
- "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
- "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_light_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+ "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_Silent_PKI"
},
{
- "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
- "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector + tma_fp_amx",
- "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_fp_arith",
- "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+ "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_NonSilent_PKI"
},
{
- "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
- "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
- "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_x87_use",
- "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "L1D_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_scalar",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "L2_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_vector",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_128b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Access_BW",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW_1T"
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_256b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average CPU Utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricGroup": "HPC;Summary",
+ "MetricName": "CPU_Utilization"
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_512b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+ "MetricGroup": "Power;Summary",
+ "MetricName": "Average_Frequency"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine)",
- "MetricExpr": "cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=1@ / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;HPC;Pipeline;Server;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_amx",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine). Refer to AMX_Busy and GFLOPs metrics for actual AMX utilization and FP performance, resp.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Giga Floating Point Operations Per Second",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / 1e9 / duration_time",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "GFLOPs",
+ "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
},
{
- "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)",
- "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b + tma_shuffles",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_int_operations",
- "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Tera Integer (matrix) Operations Per Second",
+ "MetricExpr": "8 * AMX_OPS_RETIRED.INT8 / 1e12 / duration_time",
+ "MetricGroup": "Cor;HPC;IntVector;Server",
+ "MetricName": "TIOPS"
},
{
- "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.",
- "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_int_operations_group",
- "MetricName": "tma_int_vector_128b",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+ "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricGroup": "Power",
+ "MetricName": "Turbo_Utilization"
},
{
- "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.",
- "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_int_operations_group",
- "MetricName": "tma_int_vector_256b",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
+ "MetricGroup": "SMT",
+ "MetricName": "SMT_2T_Utilization"
},
{
- "BriefDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine)",
- "MetricExpr": "cpu@AMX_OPS_RETIRED.INT8\\,cmask\\=1@ / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;HPC;IntVector;Pipeline;Server;TopdownL4;tma_int_operations_group",
- "MetricName": "tma_int_amx",
- "PublicDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine). Refer to AMX_Busy and TIOPs metrics for actual AMX utilization and Int performance, resp.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_Utilization"
},
{
- "BriefDescription": "This metric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.",
- "MetricExpr": "INT_VEC_RETIRED.SHUFFLES / (tma_retiring * SLOTS)",
- "MetricGroup": "HPC;Pipeline;TopdownL4;tma_int_operations_group",
- "MetricName": "tma_shuffles",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_CPI"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
- "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * SLOTS)",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_memory_operations",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "DRAM_BW_Use"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
- "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (tma_retiring * SLOTS)",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_fused_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
- "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (tma_retiring * SLOTS)",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_non_fused_branches",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
- "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * SLOTS)",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_nop_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=0x1@",
+ "MetricGroup": "Mem;MemoryLat;Server;SoC",
+ "MetricName": "MEM_PMM_Read_Latency"
},
{
- "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
- "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_other_light_ops",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\\=0x1@",
+ "MetricGroup": "Mem;MemoryLat;Server;SoC",
+ "MetricName": "MEM_DRAM_Read_Latency"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
- "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_heavy_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
+ "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Server;SoC",
+ "MetricName": "PMM_Read_BW"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
- "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
- "MetricGroup": "TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_few_uops_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Server;SoC",
+ "MetricName": "PMM_Write_BW"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "UOPS_RETIRED.MS / SLOTS",
- "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_microcode_sequencer",
- "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;Mem;Server;SoC",
+ "MetricName": "IO_Write_BW"
},
{
- "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
- "MetricExpr": "100 * cpu@ASSISTS.ANY\\,umask\\=0x1B@ / SLOTS",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_assists",
- "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "uncore_cha_0@event\\=0x1@",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
},
{
- "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults",
- "MetricExpr": "99 * ASSISTS.PAGE_FAULT / SLOTS",
- "MetricGroup": "TopdownL5;tma_assists_group",
- "MetricName": "tma_page_faults",
- "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+ "MetricGroup": "Branches;OS",
+ "MetricName": "IpFarBranch"
},
{
- "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists",
- "MetricExpr": "30 * ASSISTS.FP / SLOTS",
- "MetricGroup": "HPC;TopdownL5;tma_assists_group",
- "MetricName": "tma_fp_assists",
- "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called denormals).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
},
{
- "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ",
- "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / SLOTS",
- "MetricGroup": "HPC;TopdownL5;tma_assists_group",
- "MetricName": "tma_avx_assists",
+ "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricName": "cpu_utilization",
"ScaleUnit": "100%"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
- "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_cisc",
- "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS",
- "ScaleUnit": "100%"
+ "BriefDescription": "CPU operating frequency (in GHz)",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+ "MetricName": "cpu_operating_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
- "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "Mispredictions"
+ "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+ "MetricName": "cpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "Memory_Bandwidth"
+ "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+ "MetricName": "loads_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)))",
- "MetricGroup": "Mem;MemoryLat;Offcore",
- "MetricName": "Memory_Latency"
+ "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+ "MetricName": "stores_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
- "MetricGroup": "Mem;MemoryTLB;Offcore",
- "MetricName": "Memory_Data_TLBs"
+ "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+ "MetricName": "l1d_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
- "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
- "MetricGroup": "Ret",
- "MetricName": "Branching_Overhead"
+ "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+ "MetricName": "l1d_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
- "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
- "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
- "MetricName": "Big_Code"
+ "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+ "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
- "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
- "MetricGroup": "Fed;FetchBW;Frontend",
- "MetricName": "Instruction_Fetch_BW"
+ "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
- "MetricExpr": "INST_RETIRED.ANY / CLKS",
- "MetricGroup": "Ret;Summary",
- "MetricName": "IPC"
+ "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+ "MetricName": "l2_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Uops Per Instruction",
- "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;Ret;Retire",
- "MetricName": "UPI"
+ "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW",
- "MetricName": "UpTB"
+ "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_code_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
- "MetricExpr": "1 / IPC",
- "MetricGroup": "Mem;Pipeline",
- "MetricName": "CPI"
+ "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY",
+ "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "Pipeline",
- "MetricName": "CLKS"
+ "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY",
+ "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
- "MetricExpr": "TOPDOWN.SLOTS",
- "MetricGroup": "tma_L1_group",
- "MetricName": "SLOTS"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
- "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
- "MetricGroup": "SMT;tma_L1_group",
- "MetricName": "Slots_Utilization"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "The ratio of Executed- by Issued-Uops",
- "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
- "MetricGroup": "Cor;Pipeline",
- "MetricName": "Execute_per_Issue",
- "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
- "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
- "MetricGroup": "Ret;SMT;tma_L1_group",
- "MetricName": "CoreIPC"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF) + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / CORE_CLKS",
- "MetricGroup": "Flops;Ret",
- "MetricName": "FLOPc"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_to_dram_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * CORE_CLKS)",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "FP_Arith_Utilization",
- "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "itlb_2nd_level_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
- "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
- "MetricName": "ILP"
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "itlb_2nd_level_large_page_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
- "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
- "MetricGroup": "Cor;SMT",
- "MetricName": "Core_Bound_Likely"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
- "MetricGroup": "SMT",
- "MetricName": "CORE_CLKS"
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
- "MetricGroup": "InsType",
- "MetricName": "IpLoad"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_store_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
- "MetricGroup": "InsType",
- "MetricName": "IpStore"
+ "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+ "MetricName": "numa_reads_addressed_to_local_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Branches;Fed;InsType",
- "MetricName": "IpBranch"
+ "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+ "MetricName": "numa_reads_addressed_to_remote_dram",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Uncore operating frequency in GHz",
+ "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
+ "MetricName": "uncore_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "IpCall"
+ "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+ "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+ "MetricName": "upi_data_transmit_bw",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
- "MetricName": "IpTB"
+ "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Branch instructions per taken branch. ",
- "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "BpTkBranch"
+ "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF) + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16)",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpFLOP"
+ "BriefDescription": "DDR memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR))",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpArith",
- "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_SP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_DP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX128",
- "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_writes",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX256",
- "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_reads",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX512",
- "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_decoded_icache",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.BF16",
- "MetricGroup": "Flops;FpVector;InsType;Server",
- "MetricName": "IpArith_AMX_F16",
- "PublicDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions."
+ "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.INT8",
- "MetricGroup": "InsType;IntVector;Server",
- "MetricName": "IpArith_AMX_Int8",
- "PublicDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions."
+ "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
- "MetricGroup": "Prefetches",
- "MetricName": "IpSWPF"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
- "MetricExpr": "INST_RETIRED.ANY",
- "MetricGroup": "Summary;tma_L1_group",
- "MetricName": "Instructions"
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "(tma_retiring * SLOTS) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
- "MetricGroup": "Pipeline;Ret",
- "MetricName": "Retire"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
- "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
- "MetricGroup": "Pipeline;Ret",
- "MetricName": "Strings_Cycles"
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / cpu@ASSISTS.ANY\\,umask\\=0x1B@",
- "MetricGroup": "Pipeline;Ret;Retire",
- "MetricName": "IpAssist"
+ "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+ "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots",
+ "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_frontend_bound",
+ "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "",
- "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
- "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
- "MetricName": "Execute"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+ "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots",
+ "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_latency",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of Uops issued by front-end when it issued something",
- "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
- "MetricGroup": "Fed;FetchBW",
- "MetricName": "Fetch_UpC"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+ "MetricExpr": "ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_icache_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
- "MetricGroup": "DSB;Fed;FetchBW",
- "MetricName": "DSB_Coverage"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+ "MetricExpr": "ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_itlb_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
- "MetricGroup": "DSBmiss",
- "MetricName": "DSB_Switch_Cost"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+ "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_branch_resteers",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
- "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "DSB_Misses"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+ "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) / max(1 - (tma_frontend_bound + topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_mispredicts_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "IpDSB_Miss_Ret"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+ "MetricExpr": "(1 - topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) / max(1 - (tma_frontend_bound + topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_clears_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "IpMispredict"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+ "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_unknown_branches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BrMispredicts",
- "MetricName": "Branch_Misprediction_Cost"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_dsb_switches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are non-taken conditionals",
- "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_NT"
+ "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+ "MetricExpr": "DECODE.LCP / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_lcp",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are taken conditionals",
- "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_TK"
+ "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+ "MetricExpr": "3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_ms_switches",
+ "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are CALL or RET",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "CallRet"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+ "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
+ "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_bandwidth",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "Jump"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+ "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_mite",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
- "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
- "MetricGroup": "Bad;Branches",
- "MetricName": "Other_Branches"
+ "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+ "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+ "MetricName": "tma_decoder0_alone",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY",
- "MetricGroup": "Mem;MemoryBound;MemoryLat",
- "MetricName": "Load_Miss_Real_Latency"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+ "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_dsb",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
- "MetricGroup": "Mem;MemoryBW;MemoryBound",
- "MetricName": "MLP"
+ "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+ "MetricExpr": "max(1 - (tma_frontend_bound + topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_bad_speculation",
+ "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+ "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_branch_mispredicts",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI_Load"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+ "MetricExpr": "max(0, tma_bad_speculation - topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound))",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_machine_clears",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "Backend;CacheMisses;Mem",
- "MetricName": "L2MPKI"
+ "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+ "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_backend_bound",
+ "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem;Offcore",
- "MetricName": "L2MPKI_All"
+ "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+ "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+ "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_memory_bound",
+ "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2MPKI_Load"
+ "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+ "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l1_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_All"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+ "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_dtlb_load",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_Load"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L3MPKI"
+ "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "FB_HPKI"
+ "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+ "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_store_fwd_blk",
+ "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
- "MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * CORE_CLKS)",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "Page_Walks_Utilization"
+ "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+ "MetricExpr": "min((16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_lock_latency",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW"
+ "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+ "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_split_loads",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW"
+ "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+ "MetricExpr": "L1D_PEND_MISS.FB_FULL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_fb_full",
+ "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+ "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l2_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+ "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l3_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
- "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_Silent_PKI"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+ "MetricExpr": "min(((28 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (27 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_contested_accesses",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
- "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_NonSilent_PKI"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+ "MetricExpr": "min((27 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_data_sharing",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "L1D_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+ "MetricExpr": "min((12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_l3_hit_latency",
+ "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "L2_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+ "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_sq_full",
+ "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+ "MetricExpr": "min(MEMORY_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD - tma_pmm_bound, 1)",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_dram_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Access_BW",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW_1T"
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_bandwidth",
+ "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
- "MetricGroup": "HPC;Summary",
- "MetricName": "CPU_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).",
+ "MetricExpr": "INT_MISC.MBA_STALLS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group",
+ "MetricName": "tma_mba_stalls",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
- "MetricGroup": "Power;Summary",
- "MetricName": "Average_Frequency"
+ "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_latency",
+ "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF) + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / 1000000000) / duration_time",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "GFLOPs",
- "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+ "MetricExpr": "min((66.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_local_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Tera Integer (matrix) Operations Per Second",
- "MetricExpr": "(8 * AMX_OPS_RETIRED.INT8 / 1e12) / duration_time",
- "MetricGroup": "Cor;HPC;IntVector;Server",
- "MetricName": "TIOPS"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+ "MetricExpr": "min((131 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average Frequency Utilization relative nominal frequency",
- "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
- "MetricGroup": "Power",
- "MetricName": "Turbo_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+ "MetricExpr": "min(((120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_cache",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
- "MetricGroup": "SMT",
- "MetricName": "SMT_2T_Utilization"
+ "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
+ "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (MEMORY_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)",
+ "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_pmm_bound",
+ "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "OS",
- "MetricName": "Kernel_Utilization"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+ "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_store_bound",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
- "MetricGroup": "OS",
- "MetricName": "Kernel_CPI"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+ "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_store_latency",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC",
- "MetricName": "DRAM_BW_Use"
+ "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+ "MetricExpr": "min(28 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_false_sharing",
+ "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
- "MetricGroup": "Mem;MemoryLat;SoC",
- "MetricName": "MEM_Read_Latency"
+ "BriefDescription": "This metric represents rate of split store accesses",
+ "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_split_stores",
+ "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD\\,thresh\\=1@",
- "MetricGroup": "Mem;MemoryBW;SoC",
- "MetricName": "MEM_Parallel_Reads"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
+ "MetricExpr": "min(9 * OCR.STREAMING_WR.ANY_RESPONSE / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_streaming_stores",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
- "MetricExpr": "(1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=0x1@)",
- "MetricGroup": "Mem;MemoryLat;Server;SoC",
- "MetricName": "MEM_PMM_Read_Latency"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+ "MetricExpr": "min((7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CPU_CLK_UNHALTED.DISTRIBUTED, 1)",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_dtlb_store",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
- "MetricExpr": " 1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\\=0x1@",
- "MetricGroup": "Mem;MemoryLat;Server;SoC",
- "MetricName": "MEM_DRAM_Read_Latency"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
- "MetricExpr": "((64 * UNC_M_PMM_RPQ_INSERTS / 1000000000) / duration_time)",
- "MetricGroup": "Mem;MemoryBW;Server;SoC",
- "MetricName": "PMM_Read_BW"
+ "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
- "MetricExpr": "((64 * UNC_M_PMM_WPQ_INSERTS / 1000000000) / duration_time)",
- "MetricGroup": "Mem;MemoryBW;Server;SoC",
- "MetricName": "PMM_Write_BW"
+ "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+ "MetricExpr": "max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) + 0 * slots",
+ "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_core_bound",
+ "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
- "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000000 / duration_time",
- "MetricGroup": "IoBW;Mem;Server;SoC",
- "MetricName": "IO_Write_BW"
+ "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+ "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_divider",
+ "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Socket actual clocks when any core is active on that socket",
- "MetricExpr": "uncore_cha_0@event\\=0x1@",
- "MetricGroup": "SoC",
- "MetricName": "Socket_CLKS"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+ "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CPU_CLK_UNHALTED.THREAD) + 0 * slots",
+ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_ports_utilization",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
- "MetricGroup": "Branches;OS",
- "MetricName": "IpFarBranch"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CPU_CLK_UNHALTED.THREAD + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_0",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C1 residency percent per core",
- "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C1_Core_Residency"
+ "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+ "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_serializing_operation",
+ "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.",
+ "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group",
+ "MetricName": "tma_slow_pause",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.",
+ "MetricExpr": "min(13 * MISC2_RETIRED.LFENCE / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group",
+ "MetricName": "tma_memory_fence",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
+ "MetricExpr": "min(160 * ASSISTS.SSE_AVX_MIX / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_mixing_vectors",
+ "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix Extensions (AMX) execution engine was busy with tile (arithmetic) operations",
+ "MetricExpr": "EXE.AMX_BUSY / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "Compute;HPC;Server;TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_amx_busy",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "CPU operating frequency (in GHz)",
- "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "cpu_operating_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_1",
+ "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "loads_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_2",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "stores_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+ "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_3m",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+ "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_alu_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_0",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_1",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_6",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_load_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+ "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_store_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_code_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_retiring",
+ "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+ "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) + 0 * slots",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_light_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector + tma_fp_amx",
+ "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fp_arith",
+ "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + 0 * slots",
+ "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_x87_use",
+ "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_scalar",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_vector",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_128b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_to_dram_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_256b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_2nd_level_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_512b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_2nd_level_large_page_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine)",
+ "MetricExpr": "cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=0x1@ / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Compute;Flops;HPC;Pipeline;Server;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_amx",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine). Refer to AMX_Busy and GFLOPs metrics for actual AMX utilization and FP performance, resp.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2nd_level_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)",
+ "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b + tma_shuffles",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_int_operations",
+ "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.",
+ "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group",
+ "MetricName": "tma_int_vector_128b",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2nd_level_store_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.",
+ "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group",
+ "MetricName": "tma_int_vector_256b",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_local_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine)",
+ "MetricExpr": "cpu@AMX_OPS_RETIRED.INT8\\,cmask\\=0x1@ / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Compute;HPC;IntVector;Pipeline;Server;TopdownL4;tma_L4_group;tma_int_operations_group",
+ "MetricName": "tma_int_amx",
+ "PublicDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine). Refer to AMX_Busy and TIOPs metrics for actual AMX utilization and Int performance, resp.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_remote_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.",
+ "MetricExpr": "INT_VEC_RETIRED.SHUFFLES / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group",
+ "MetricName": "tma_shuffles",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore operating frequency in GHz",
- "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "uncore_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+ "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * MEM_UOP_RETIRED.ANY / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_memory_operations",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
- "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "upi_data_transmit_bw",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
+ "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * INST_RETIRED.MACRO_FUSED / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fused_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
+ "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_non_fused_branches",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+ "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * INST_RETIRED.NOP / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_nop_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+ "MetricExpr": "max(0, max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_other_light_ops",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+ "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_heavy_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+ "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - tma_microcode_sequencer",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_few_uops_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+ "MetricExpr": "UOPS_RETIRED.MS / slots",
+ "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_microcode_sequencer",
+ "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
- "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_writes",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+ "MetricExpr": "min(100 * cpu@ASSISTS.ANY\\,umask\\=0x1B@ / slots, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_assists",
+ "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
- "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_reads",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults",
+ "MetricExpr": "99 * ASSISTS.PAGE_FAULT / slots",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group",
+ "MetricName": "tma_page_faults",
+ "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_decoded_icache",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists",
+ "MetricExpr": "30 * ASSISTS.FP / slots",
+ "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group",
+ "MetricName": "tma_fp_assists",
+ "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called denormals).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ",
+ "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / slots",
+ "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group",
+ "MetricName": "tma_avx_assists",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_microcode_sequencer",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+ "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_cisc",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C1 residency percent per core",
+ "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C1_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C6 residency percent per core",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_remote_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C2 residency percent per package",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_remote_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C6 residency percent per package",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json
index 41d7cd4958a1..b77fd0f7ab50 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json
@@ -1,499 +1,461 @@
[
{
- "BriefDescription": "IMC Clockticks at DCLK frequency",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M_CLOCKTICKS",
+ "BriefDescription": "Activate due to read, write, underfill, or bypass",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_ACT_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0xff",
"Unit": "iMC"
},
{
- "BriefDescription": "IMC Clockticks at HCLK frequency",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M_HCLOCKTICKS",
+ "BriefDescription": "All DRAM CAS commands issued",
+ "EventCode": "0x05",
+ "EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel.",
+ "UMask": "0xff",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0",
"EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.RD_REG",
+ "EventName": "UNC_M_CAS_COUNT.PCH0",
"PerPkg": "1",
- "UMask": "0x00000000c1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM underfill read CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1",
"EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "EventName": "UNC_M_CAS_COUNT.PCH1",
"PerPkg": "1",
- "UMask": "0x00000000c4",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "All DRAM read CAS commands issued (including underfills)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x00000000cf",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel. This includes underfills.",
+ "UMask": "0xcf",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM write CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
"EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.WR",
+ "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
"PerPkg": "1",
- "UMask": "0x00000000f0",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0xc2",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS.PCH0",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+ "EventCode": "0x05",
+ "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0xc8",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS.PCH1",
+ "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
+ "EventCode": "0x05",
+ "EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0xc1",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS.PCH0",
+ "BriefDescription": "DRAM underfill read CAS commands issued",
+ "EventCode": "0x05",
+ "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Underfill Read Issued : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0xc4",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS.PCH1",
+ "BriefDescription": "All DRAM write CAS commands issued",
+ "EventCode": "0x05",
+ "EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel.",
+ "UMask": "0xf0",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
+ "EventCode": "0x05",
+ "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0xd0",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+ "EventCode": "0x05",
+ "EventName": "UNC_M_CAS_COUNT.WR_PRE",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0xe0",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
+ "BriefDescription": "IMC Clockticks at DCLK frequency",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Number of DRAM DCLK clock cycles while the event is enabled",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
+ "BriefDescription": "IMC Clockticks at HCLK frequency",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_HCLOCKTICKS",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Number of DRAM HCLK clock cycles while the event is enabled",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PMM Read Pending Queue inserts",
+ "EventCode": "0xe3",
+ "EventName": "UNC_M_PMM_RPQ_INSERTS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of read requests allocated in the PMM Read Pending Queue.",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Read Pending Queue occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Read Pending Queue occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe3",
- "EventName": "UNC_M_PMM_RPQ_INSERTS",
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1",
+ "PerPkg": "1",
+ "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x20",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xe0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xe0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Write Pending Queue inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe7",
"EventName": "UNC_M_PMM_WPQ_INSERTS",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Counts number of write requests allocated in the PMM Write Pending Queue.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PMM Write Pending Queue Occupancy",
+ "EventCode": "0xe4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM.",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Activate due to read, write, underfill, or bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_ACT_COUNT.ALL",
+ "BriefDescription": "Channel PPD Cycles",
+ "EventCode": "0x85",
+ "EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
- "UMask": "0x00000000ff",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Unit": "iMC"
},
{
- "BriefDescription": "Precharge due to read on page miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.RD",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
"PerPkg": "1",
- "UMask": "0x0000000011",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Precharge due to write on page miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.WR",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
"PerPkg": "1",
- "UMask": "0x0000000022",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to (?)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.PGT",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
"PerPkg": "1",
- "UMask": "0x0000000088",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Precharge due to read, write, underfill, or PGT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.ALL",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
"PerPkg": "1",
- "UMask": "0x00000000ff",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.ALL",
+ "BriefDescription": "Clock-Enabled Self-Refresh",
+ "EventCode": "0x43",
+ "EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
- "UMask": "0x00000000ff",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
+ "BriefDescription": "Precharge due to read, write, underfill, or PGT.",
+ "EventCode": "0x03",
+ "EventName": "UNC_M_PRE_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x00000000c2",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0xff",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to (?)",
+ "EventCode": "0x03",
+ "EventName": "UNC_M_PRE_COUNT.PGT",
"PerPkg": "1",
- "UMask": "0x00000000c8",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x88",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.WR_PRE",
+ "BriefDescription": "DRAM Precharge commands. : Prechages from Page Table",
+ "EventCode": "0x03",
+ "EventName": "UNC_M_PRE_COUNT.PGT_PCH0",
"PerPkg": "1",
- "UMask": "0x00000000e0",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Prechages from Page Table : Counts the number of DRAM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0",
+ "BriefDescription": "DRAM Precharge commands.",
+ "EventCode": "0x03",
+ "EventName": "UNC_M_PRE_COUNT.PGT_PCH1",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1",
+ "BriefDescription": "Precharge due to read on page miss",
+ "EventCode": "0x03",
+ "EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x0000000008",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to read",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.RD_PCH0",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM Precharge commands.",
"EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.WR_PCH0",
+ "EventName": "UNC_M_PRE_COUNT.RD_PCH1",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM Precharge commands.",
"EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.UFILL_PCH0",
+ "EventName": "UNC_M_PRE_COUNT.UFILL",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x44",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Prechages from Page Table",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM Precharge commands.",
"EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.PGT_PCH0",
+ "EventName": "UNC_M_PRE_COUNT.UFILL_PCH0",
"PerPkg": "1",
- "UMask": "0x0000000008",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM Precharge commands.",
"EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.RD_PCH1",
+ "EventName": "UNC_M_PRE_COUNT.UFILL_PCH1",
"PerPkg": "1",
- "UMask": "0x0000000010",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Precharge due to write on page miss",
"EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.WR_PCH1",
+ "EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
- "UMask": "0x0000000020",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x22",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
"EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.UFILL_PCH1",
+ "EventName": "UNC_M_PRE_COUNT.WR_PCH0",
"PerPkg": "1",
- "UMask": "0x0000000040",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM Precharge commands.",
"EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.PGT_PCH1",
+ "EventName": "UNC_M_PRE_COUNT.WR_PCH1",
"PerPkg": "1",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_M_PRE_COUNT.UFILL",
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS.PCH0",
"PerPkg": "1",
- "UMask": "0x0000000044",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS.PCH1",
"PerPkg": "1",
- "UMask": "0x00000000D0",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.PCH0",
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x80",
+ "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
- "UMask": "0x0000000040",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M_CAS_COUNT.PCH1",
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x81",
+ "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0",
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS.PCH0",
"PerPkg": "1",
- "UMask": "0x0000000010",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1",
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS.PCH1",
+ "PerPkg": "1",
+ "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x82",
+ "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
+ "PerPkg": "1",
+ "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x83",
+ "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
- "UMask": "0x0000000020",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
"Unit": "iMC"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json
index 495ceee21071..fd253e3276df 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json
@@ -1,5141 +1,4465 @@
[
{
- "BriefDescription": "UPI Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CHA Clockticks",
"EventCode": "0x01",
- "EventName": "UNC_UPI_CLOCKTICKS",
+ "EventName": "UNC_CHA_CLOCKTICKS",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CHA clock cycles while the event is enabled",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : All Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_CHA_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x000000000f",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "IRP Clockticks",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_I_CLOCKTICKS",
+ "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "IRP"
+ "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2P Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M2P_CLOCKTICKS",
+ "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "M2PCIe"
+ "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "IIO Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_IIO_CLOCKTICKS",
+ "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.HA",
"PerPkg": "1",
- "PortMask": "0x0000",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.TOR",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x1bc1ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
+ "UMask": "0x1c19ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "All LLC lines in E state that are victimized on a fill",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "All LLC lines in M state that are victimized on a fill",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "All LLC lines in S state that are victimized on a fill",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Local Rd",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.LOCAL_READ",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Requests for exclusive ownership of a cache line without receiving data",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x30",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Read requests made into the CHA",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .",
+ "UMask": "0x3",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Read requests from a unit on this socket",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Read requests from a remote socket",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Write requests made into the CHA",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0xc",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Write Requests from a unit on this socket",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Read and Write Requests; Writes Remote",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0xc001ffff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DDR Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.DDR",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DDR Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : SF/LLC Evictions",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Just Hits",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.HIT",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; All from Local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores",
+ "UMask": "0xc001ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts;CLFlush from Local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core",
+ "UMask": "0xc8c7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts;CLFlushOpt from Local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlushOpt events that are initiated from the Core",
+ "UMask": "0xc8d7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; CRd from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter",
+ "UMask": "0xc80fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M2M_CLOCKTICKS",
+ "BriefDescription": "TOR Inserts; CRd Pref from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M3UPI Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M3UPI_CLOCKTICKS",
+ "BriefDescription": "TOR Inserts; DRd from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "M3UPI"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc817ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read requests from a unit on this socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Read requests from a remote socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
+ "BriefDescription": "TOR Inserts; DRd Opt from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter",
+ "UMask": "0xc827ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Write Requests from a unit on this socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
+ "BriefDescription": "TOR Inserts; DRd Opt Pref from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc8a7ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Read and Write Requests; Writes Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
+ "BriefDescription": "TOR Inserts; DRd Pref from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
"PerPkg": "1",
- "UMask": "0x0000000008",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc897ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Requests for exclusive ownership of a cache line without receiving data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE",
+ "BriefDescription": "TOR Inserts; Hits from Local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
"PerPkg": "1",
- "UMask": "0x0000000030",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0xc001fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_CHA_CLOCKTICKS",
+ "BriefDescription": "TOR Inserts; CRd hits from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Inserts; Code read from local IA that hits in the snoop filter",
+ "UMask": "0xc80ffd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for CRd misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts; CRd Pref hits from local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x00c80ffe01",
- "UMaskExt": "0x00c80ffe",
+ "PublicDescription": "TOR Inserts; Code read prefetch from local IA that hits in the snoop filter",
+ "UMask": "0xc88ffd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for DRd misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts; DRd hits from local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
"PerPkg": "1",
- "UMask": "0x00c817fe01",
- "UMaskExt": "0x00c817fe",
+ "PublicDescription": "TOR Inserts; Data read from local IA that hits in the snoop filter",
+ "UMask": "0xc817fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for DRd Pref misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
"PerPkg": "1",
- "UMask": "0x00c897fe01",
- "UMaskExt": "0x00c897fe",
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for ItoM from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts; DRd Opt hits from local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x00cc43ff04",
- "UMaskExt": "0x00cc43ff",
+ "PublicDescription": "TOR Inserts; Data read opt from local IA that hits in the snoop filter",
+ "UMask": "0xc827fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for DRd misses from local IA targeting local memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts; DRd Opt Pref hits from local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x00c816fe01",
- "UMaskExt": "0x00c816fe",
+ "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that hits in the snoop filter",
+ "UMask": "0xc8a7fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for DRd misses from local IA targeting remote memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts; DRd Pref hits from local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
"PerPkg": "1",
- "UMask": "0x00c8177e01",
- "UMaskExt": "0x00c8177e",
+ "PublicDescription": "TOR Inserts; Data read prefetch from local IA that hits in the snoop filter",
+ "UMask": "0xc897fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting local memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x00C896FE01",
- "UMaskExt": "0x00C896FE",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting remote memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts; LLCPrefCode hits from local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0x00C8977E01",
- "UMaskExt": "0x00C8977E",
+ "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that hits in the snoop filter",
+ "UMask": "0xcccffd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy for DRd misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+ "BriefDescription": "TOR Inserts; LLCPrefData hits from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x00c817fe01",
- "UMaskExt": "0x00c817fe",
+ "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that hits in the snoop filter",
+ "UMask": "0xccd7fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting local memory",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
+ "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x00c816fe01",
- "UMaskExt": "0x00c816fe",
+ "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter",
+ "UMask": "0xccc7fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting remote memory",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
+ "BriefDescription": "TOR Inserts; RFO hits from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x00c8177e01",
- "UMaskExt": "0x00c8177e",
+ "PublicDescription": "TOR Inserts; Read for ownership from local IA that hits in the snoop filter",
+ "UMask": "0xc807fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts; RFO Pref hits from local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x00c8178a01",
- "UMaskExt": "0x00c8178a",
+ "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter",
+ "UMask": "0xc887fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts;ItoM from Local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
"PerPkg": "1",
- "UMask": "0x00c8178601",
- "UMaskExt": "0x00c81786",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; ItoM events that are initiated from the Core",
+ "UMask": "0xcc47ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x00c8178601",
- "UMaskExt": "0x00c81786",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd47ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
+ "BriefDescription": "TOR Inserts; LLCPrefCode from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0x00c8178a01",
- "UMaskExt": "0x00c8178a",
+ "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA.",
+ "UMask": "0xcccfff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for RdCur from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts; LLCPrefData from local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x00c8f3ff04",
- "UMaskExt": "0x00c8f3ff",
+ "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA.",
+ "UMask": "0xccd7ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts for ItoMCacheNears from IO devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA",
"EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x00cd43ff04",
- "UMaskExt": "0x00cd43ff",
+ "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xccc7ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+ "BriefDescription": "TOR Inserts; misses from Local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+ "BriefDescription": "TOR Inserts for CRd misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd",
+ "UMask": "0xc80ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+ "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.DATA",
+ "BriefDescription": "TOR Inserts; CRd Pref misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x0000000008",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x0000000010",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.NULL",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x0000000020",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : LLCTRL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+ "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
"PerPkg": "1",
- "UMask": "0x0000000040",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : Protocol Header",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+ "BriefDescription": "TOR Inserts for DRd misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
"PerPkg": "1",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd",
+ "UMask": "0xc817fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : All Non Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
"PerPkg": "1",
- "UMask": "0x0000000097",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : Idle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.IDLE",
+ "BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
"PerPkg": "1",
- "UMask": "0x0000000047",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory",
+ "UMask": "0xc8178601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "All Null Flits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
+ "BriefDescription": "TOR Inserts for DRd misses from local IA targeting local memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
- "UMask": "0x0000000027",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory",
+ "UMask": "0xc816fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+ "BriefDescription": "TOR Inserts; DRd Opt misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter",
+ "UMask": "0xc827fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.DATA",
+ "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x0000000008",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc8a7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+ "BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
"PerPkg": "1",
- "UMask": "0x0000000010",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory",
+ "UMask": "0xc8178a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.NULL",
+ "BriefDescription": "TOR Inserts for DRd Pref misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
"PerPkg": "1",
- "UMask": "0x0000000020",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF",
+ "UMask": "0xc897fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : LLCTRL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
"PerPkg": "1",
- "UMask": "0x0000000040",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : Protocol Header",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+ "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting local memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory",
+ "UMask": "0xc896fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : All Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x000000000f",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : All Non Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x0000000097",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : Idle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.IDLE",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
"PerPkg": "1",
- "UMask": "0x0000000047",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Null FLITs received from any slot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
+ "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting remote memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x0000000027",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory",
+ "UMask": "0xc8977e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x000000000e",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x000000010e",
- "UMaskExt": "0x00000001",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": "TOR Inserts for DRd misses from local IA targeting remote memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
- "UMask": "0x000000000f",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory",
+ "UMask": "0xc8177e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x000000010f",
- "UMaskExt": "0x00000001",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x000000000e",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x000000010e",
- "UMaskExt": "0x00000001",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": "TOR Inserts; LLCPrefCode misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0x000000000f",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that misses in the snoop filter",
+ "UMask": "0xcccffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x000000010f",
- "UMaskExt": "0x00000001",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter",
+ "UMask": "0xccd7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Direct packet attempts : D2C",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+ "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xccc7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles in L1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_UPI_L1_POWER_CYCLES",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+ "BriefDescription": "TOR Inserts; RFO misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xc807fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+ "BriefDescription": "TOR Inserts RFO misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xc806fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_UPI_TxL_INSERTS",
+ "BriefDescription": "TOR Inserts; RFO pref misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc887fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_UPI_TxL_BYPASSED",
+ "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc886fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_UPI_TxL_OCCUPANCY",
+ "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "UPI LL"
+ "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc8877e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FAF allocation -- sent to ADQ",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_I_FAF_TRANSACTIONS",
+ "BriefDescription": "TOR Inserts; RFO misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts Read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xc8077e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FAF - request insert from TC",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_I_FAF_INSERTS",
+ "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc877de01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FAF occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_I_FAF_OCCUPANCY",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+ "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound write (fast path) requests received by the IRP",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x0000000008",
- "UMaskExt": "0x00000000",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M2P_CMS_CLOCKTICKS",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by IIO Part1 to Memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by IIO Part2 to Memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc87fde01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by IIO Part3 to Memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; RFO from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xc807ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; RFO pref from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc887ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts;SpecItoM from Local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core",
+ "UMask": "0xcc57ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc3fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc27ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; All from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; Hits from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; ItoM hits from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; RFO hits from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts for ItoM from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Inserts into the TOR from local IO with the opcode ItoM",
+ "UMask": "0xcc43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts for ItoMCacheNears from IO devices.",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Inserts into the TOR from local IO devices with the opcode ItoMCacheNears. This event indicates a partial write request.",
+ "UMask": "0xcd43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; Misses from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; ItoM misses from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; RdCur and FsRdCur misses from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; RFO misses from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts for RdCur from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Inserts into the TOR from local IO with the opcode RdCur",
+ "UMask": "0xc8f3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; RFO from local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc23ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : IPQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : IRQ - iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From an iA Core",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : IRQ - Non iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Just ISOC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Just Local Targets",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All from Local iA and IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests",
+ "UMask": "0xc000ff05",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All from Local iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests from iA Cores",
+ "UMask": "0xc000ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally generated IO traffic",
+ "UMask": "0xc000ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Just Misses",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MISS",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : MMCFG Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : MMIO Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MMIO",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : MMIO Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Just NonCoherent",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : PMM Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PMM",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : PM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : PRQ - IOSF",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From a PCIe Device",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Just Remote Targets",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All from Remote",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All remote requests (e.g. snoops, writebacks) that came from remote sockets",
+ "UMask": "0xc001ffc8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All Snoops from Remote",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All Snoops from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All snoops to this LLC that came from remote sockets",
+ "UMask": "0xc001ff08",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : RRQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; All Snoops from Remote",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.SNPS_FROM_REM",
"PerPkg": "1",
- "PortMask": "0x0001",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets.",
+ "UMask": "0xc001ff08",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WBQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
"PerPkg": "1",
- "PortMask": "0x0002",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy : All",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0xc001ffff",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy : DDR Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : DDR Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy : Just Hits",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; All from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c7ff01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8d7ff01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; CRd from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter",
+ "UMask": "0xc80fff01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88fff01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; DRd from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc817ff01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; DRd Opt from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter",
+ "UMask": "0xc827ff01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; DRd Opt Pref from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc8a7ff01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; DRd Pref from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc897ff01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; Hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; CRd hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy; Code read from local IA that hits in the snoop filter",
+ "UMask": "0xc80ffd01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter",
+ "UMask": "0xc88ffd01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; DRd hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy; Data read from local IA that hits in the snoop filter",
+ "UMask": "0xc817fd01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; DRd Opt hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
"PerPkg": "1",
- "PortMask": "0x0004",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Data read opt from local IA that hits in the snoop filter",
+ "UMask": "0xc827fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; DRd Opt Pref hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
"PerPkg": "1",
- "PortMask": "0x0008",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that hits in the snoop filter",
+ "UMask": "0xc8a7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
"PerPkg": "1",
- "PortMask": "0x0010",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter",
+ "UMask": "0xc897fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
"PerPkg": "1",
- "PortMask": "0x0020",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; LLCPrefCode hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
"PerPkg": "1",
- "PortMask": "0x0040",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that hits in the snoop filter",
+ "UMask": "0xcccffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; LLCPrefData hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
"PerPkg": "1",
- "PortMask": "0x0080",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that hits in the snoop filter",
+ "UMask": "0xccd7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter",
+ "UMask": "0xccc7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; RFO hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Read for ownership from local IA that hits in the snoop filter",
+ "UMask": "0xc807fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter",
+ "UMask": "0xc887fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; LLCPrefCode from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA.",
+ "UMask": "0xcccfff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; LLCPrefData from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter",
+ "UMask": "0xccd7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xccc7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
- "FCMask": "0x04",
+ "BriefDescription": "TOR Occupancy; Misses from Local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
"PerPkg": "1",
- "UMask": "0x00000000ff",
- "UMaskExt": "0x00000000",
- "Unit": "IIO"
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M2M_RxC_AD_INSERTS",
+ "BriefDescription": "TOR Occupancy; CRd misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter",
+ "UMask": "0xc80ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+ "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
+ "BriefDescription": "TOR Occupancy; CRd Pref misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to core transaction were overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages sent direct to the Intel UPI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
+ "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles when direct to Intel UPI was disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "TOR Occupancy for DRd misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd",
+ "UMask": "0xc817fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+ "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory",
+ "UMask": "0xc8178601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1c",
- "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+ "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting local memory",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory",
+ "UMask": "0xc816fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+ "BriefDescription": "TOR Occupancy; DRd Opt misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter",
+ "UMask": "0xc827fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+ "BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc8a7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from A to I",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
+ "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
"PerPkg": "1",
- "UMask": "0x0320",
- "UMaskExt": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory",
+ "UMask": "0xc8178a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from A to S",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
+ "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
"PerPkg": "1",
- "UMask": "0x0340",
- "UMaskExt": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc897fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
"PerPkg": "1",
- "UMask": "0x0301",
- "UMaskExt": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from I to A",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
+ "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x0304",
- "UMaskExt": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc896fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from I to S",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x0302",
- "UMaskExt": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from S to A",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x0310",
- "UMaskExt": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from S to I",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
"PerPkg": "1",
- "UMask": "0x0308",
- "UMaskExt": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x0000000104",
- "UMaskExt": "0x00000001",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc8977e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x0000000204",
- "UMaskExt": "0x00000002",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting remote memory",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory",
+ "UMask": "0xc8177e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Prefetches Dropped",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Prefetches Dropped",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Prefetches Dropped",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Prefetches Dropped",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
+ "BriefDescription": "TOR Occupancy; LLCPrefCode misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0x0000000008",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that misses in the snoop filter",
+ "UMask": "0xcccffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
+ "BriefDescription": "TOR Occupancy; LLCPrefData misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x000000000a",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter",
+ "UMask": "0xccd7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
+ "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x0000000005",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xccc7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Prefetches Dropped",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x0000000005",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": UPI - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5d",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x000000000a",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5d",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x0000000005",
- "UMaskExt": "0x00000000",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FlowQ Generated Prefetch",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "M3UPI"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "D2U Sent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2a",
- "EventName": "UNC_M3UPI_D2U_SENT",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "M3UPI"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "D2C Sent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2b",
- "EventName": "UNC_M3UPI_D2C_SENT",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
- "Unit": "M3UPI"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M3UPI CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
"PerPkg": "1",
- "Unit": "M3UPI"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x0000000010",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0a01",
"Unit": "CHA"
},
{
- "BriefDescription": "Read requests made into the CHA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS",
+ "BriefDescription": "TOR Occupancy; RFO misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x0000000003",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xc807fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Write requests made into the CHA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES",
+ "BriefDescription": "TOR Occupancy; RFO misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
"PerPkg": "1",
- "UMask": "0x000000000c",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xc806fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+ "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc887fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+ "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc886fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.HA",
+ "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc8877e01",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.TOR",
+ "BriefDescription": "TOR Occupancy; RFO misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xc8077e01",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
+ "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc877de01",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Local Rd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.LOCAL_READ",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86ffe01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+ "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x00001bc1ff",
- "UMaskExt": "0x00001bc1",
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678601",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x00001c19ff",
- "UMaskExt": "0x00001c19",
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678a01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; All Snoops from Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.SNPS_FROM_REM",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x00c001ff08",
- "UMaskExt": "0x00c001ff",
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8601",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x00C001FFff",
- "UMaskExt": "0x00C001FF",
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8a01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; All from Local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA",
+ "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
"PerPkg": "1",
- "UMask": "0x00c001ff01",
- "UMaskExt": "0x00c001ff",
+ "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc87fde01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Hits from Local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+ "BriefDescription": "TOR Occupancy; RFO from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
"PerPkg": "1",
- "UMask": "0x00c001fd01",
- "UMaskExt": "0x00c001fd",
+ "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter",
+ "UMask": "0xc807ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; CRd hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+ "BriefDescription": "TOR Occupancy; RFO prefetch from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x00c80ffd01",
- "UMaskExt": "0x00c80ffd",
+ "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc887ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; DRd hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
+ "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
"PerPkg": "1",
- "UMask": "0x00c817fd01",
- "UMaskExt": "0x00c817fd",
+ "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
+ "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
"PerPkg": "1",
- "UMask": "0x00ccc7fd01",
- "UMaskExt": "0x00ccc7fd",
+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc27ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; RFO hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
"PerPkg": "1",
- "UMask": "0x00c807fd01",
- "UMaskExt": "0x00c807fd",
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86fff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; misses from Local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
"PerPkg": "1",
- "UMask": "0x00c001fe01",
- "UMaskExt": "0x00c001fe",
+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
+ "BriefDescription": "TOR Occupancy; All from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
"PerPkg": "1",
- "UMask": "0x00ccc7fe01",
- "UMaskExt": "0x00ccc7fe",
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; RFO misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+ "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x00c807fe01",
- "UMaskExt": "0x00c807fe",
+ "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c3ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; All from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO",
+ "BriefDescription": "TOR Occupancy; Hits from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
"PerPkg": "1",
- "UMask": "0x00c001ff04",
- "UMaskExt": "0x00c001ff",
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Hits from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+ "BriefDescription": "TOR Occupancy; ITOM hits from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x00c001fd04",
- "UMaskExt": "0x00c001fd",
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Misses from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x00c001fe04",
- "UMaskExt": "0x00c001fe",
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; ItoM misses from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+ "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x00cc43fe04",
- "UMaskExt": "0x00cc43fe",
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; RFO misses from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+ "BriefDescription": "TOR Occupancy; RFO hits from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x00c803fe04",
- "UMaskExt": "0x00c803fe",
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : IRQ - iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
+ "BriefDescription": "TOR Occupancy; ITOM from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : SF/LLC Evictions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+ "BriefDescription": "TOR Occupancy; Misses from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PRQ - IOSF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
+ "BriefDescription": "TOR Occupancy; ITOM misses from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : IPQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x0000000008",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : IRQ - Non iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
+ "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x0000000010",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
+ "BriefDescription": "TOR Occupancy; RFO misses from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x0000000020",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
+ "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x0000000040",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : WBQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
+ "BriefDescription": "TOR Occupancy; ItoM from local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
"PerPkg": "1",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All from Local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
+ "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
"PerPkg": "1",
- "UMask": "0x00C000FF04",
- "UMaskExt": "0x00C000FF",
+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc23ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All from Local iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
+ "BriefDescription": "TOR Occupancy : IPQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x00c000ff01",
- "UMaskExt": "0x00c000ff",
+ "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All from Local iA and IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+ "BriefDescription": "TOR Occupancy : IRQ - iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
"PerPkg": "1",
- "UMask": "0x00C000FF05",
- "UMaskExt": "0x00C000FF",
+ "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From an iA Core",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All Snoops from Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS",
+ "BriefDescription": "TOR Occupancy : IRQ - Non iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
"PerPkg": "1",
- "UMask": "0x00C001FF08",
- "UMaskExt": "0x00C001FF",
+ "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All from Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
+ "BriefDescription": "TOR Occupancy : Just ISOC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
"PerPkg": "1",
- "UMask": "0x00C001FFC8",
- "UMaskExt": "0x00C001FF",
+ "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just Hits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+ "BriefDescription": "TOR Occupancy : Just Local Targets",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
"PerPkg": "1",
- "UMaskExt": "0x00000001",
+ "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+ "BriefDescription": "TOR Occupancy : All from Local iA and IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
"PerPkg": "1",
- "UMaskExt": "0x00000002",
+ "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests",
+ "UMask": "0xc000ff05",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : MMCFG Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
+ "BriefDescription": "TOR Occupancy : All from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
"PerPkg": "1",
- "UMaskExt": "0x00000020",
+ "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests from iA Cores",
+ "UMask": "0xc000ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : MMIO Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MMIO",
+ "BriefDescription": "TOR Occupancy : All from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
"PerPkg": "1",
- "UMaskExt": "0x00000040",
+ "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally generated IO traffic",
+ "UMask": "0xc000ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just Local Targets",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
+ "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
"PerPkg": "1",
- "UMaskExt": "0x00000080",
+ "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just Remote Targets",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
+ "BriefDescription": "TOR Occupancy : Just Misses",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
"PerPkg": "1",
- "UMaskExt": "0x00000100",
+ "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
+ "BriefDescription": "TOR Occupancy : MMCFG Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
"PerPkg": "1",
- "UMaskExt": "0x00000200",
+ "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
+ "BriefDescription": "TOR Occupancy : MMIO Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MMIO",
"PerPkg": "1",
- "UMaskExt": "0x00000400",
+ "PublicDescription": "TOR Occupancy : MMIO Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just NonCoherent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
+ "BriefDescription": "TOR Occupancy : Just NonCoherent",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
"PerPkg": "1",
- "UMaskExt": "0x01000000",
+ "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just ISOC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
+ "BriefDescription": "TOR Occupancy : PMM Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
"PerPkg": "1",
- "UMaskExt": "0x02000000",
+ "PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; CRd Pref hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
+ "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
"PerPkg": "1",
- "UMask": "0x00c88ffd01",
- "UMaskExt": "0x00c88ffd",
+ "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; DRd Pref hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
+ "BriefDescription": "TOR Occupancy : PRQ - IOSF",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
"PerPkg": "1",
- "UMask": "0x00c897fd01",
- "UMaskExt": "0x00c897fd",
+ "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From a PCIe Device",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; DRd Opt hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
+ "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
"PerPkg": "1",
- "UMask": "0x00c827fd01",
- "UMaskExt": "0x00c827fd",
+ "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x20",
"Unit": "CHA"
},
- {
- "BriefDescription": "TOR Inserts; DRd Opt Pref hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
+ {
+ "BriefDescription": "TOR Occupancy : Just Remote Targets",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
"PerPkg": "1",
- "UMask": "0x00c8a7fd01",
- "UMaskExt": "0x00c8a7fd",
+ "PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; RFO Pref hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
+ "BriefDescription": "TOR Occupancy : All from Remote",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL",
"PerPkg": "1",
- "UMask": "0x00c887fd01",
- "UMaskExt": "0x00c887fd",
+ "PublicDescription": "TOR Occupancy : All from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All remote requests (e.g. snoops, writebacks) that came from remote sockets",
+ "UMask": "0xc001ffc8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; CRd Pref misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
+ "BriefDescription": "TOR Occupancy : All Snoops from Remote",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS",
"PerPkg": "1",
- "UMask": "0x00c88ffe01",
- "UMaskExt": "0x00c88ffe",
+ "PublicDescription": "TOR Occupancy : All Snoops from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All snoops to this LLC that came from remote sockets",
+ "UMask": "0xc001ff08",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; DRd Opt misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
+ "BriefDescription": "TOR Occupancy : RRQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ",
"PerPkg": "1",
- "UMask": "0x00c827fe01",
- "UMaskExt": "0x00c827fe",
+ "PublicDescription": "TOR Occupancy : RRQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
+ "BriefDescription": "TOR Occupancy; All Snoops from Remote",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.SNPS_FROM_REM",
"PerPkg": "1",
- "UMask": "0x00c8a7fe01",
- "UMaskExt": "0x00c8a7fe",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets.",
+ "UMask": "0xc001ff08",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; RFO pref misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
+ "BriefDescription": "TOR Occupancy : WBQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.WBQ",
"PerPkg": "1",
- "UMask": "0x00c887fe01",
- "UMaskExt": "0x00c887fe",
+ "PublicDescription": "TOR Occupancy : WBQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; ItoM hits from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
+ "BriefDescription": "IIO Clockticks",
+ "EventCode": "0x01",
+ "EventName": "UNC_IIO_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x00cc43fd04",
- "UMaskExt": "0x00cc43fd",
- "Unit": "CHA"
+ "PortMask": "0x0000",
+ "PublicDescription": "Number of IIO clock cycles while the event is enabled",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RFO hits from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c803fd04",
- "UMaskExt": "0x00c803fd",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RFO from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c803ff04",
- "UMaskExt": "0x00c803ff",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RFO pref from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c887ff01",
- "UMaskExt": "0x00c887ff",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RFO from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c807ff01",
- "UMaskExt": "0x00c807ff",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00ccc7ff01",
- "UMaskExt": "0x00ccc7ff",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; DRd from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c817ff01",
- "UMaskExt": "0x00c817ff",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; DRd Pref from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c897ff01",
- "UMaskExt": "0x00c897ff",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; DRd Opt from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c827ff01",
- "UMaskExt": "0x00c827ff",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; DRd Opt Pref from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
+ "BriefDescription": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x00c8a7ff01",
- "UMaskExt": "0x00c8a7ff",
- "Unit": "CHA"
+ "UMask": "0xff",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; CRd Pref from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00C88FFF01",
- "UMaskExt": "0x00C88FFF",
- "Unit": "CHA"
+ "PortMask": "0x0100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; CRd from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c80fff01",
- "UMaskExt": "0x00c80fff",
- "Unit": "CHA"
+ "PortMask": "0x0200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts RFO misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
+ "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c806fe01",
- "UMaskExt": "0x00c806fe",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RFO misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
+ "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8077e01",
- "UMaskExt": "0x00c8077e",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
+ "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c886fe01",
- "UMaskExt": "0x00c886fe",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
+ "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8877e01",
- "UMaskExt": "0x00c8877e",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts;CLFlush from Local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8c7ff01",
- "UMaskExt": "0x00c8c7ff",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts;CLFlushOpt from Local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8d7ff01",
- "UMaskExt": "0x00c8d7ff",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts;ItoM from Local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00cc47ff01",
- "UMaskExt": "0x00cc47ff",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts;SpecItoM from Local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00cc57ff01",
- "UMaskExt": "0x00cc57ff",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; All Snoops from Remote",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.SNPS_FROM_REM",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c001ff08",
- "UMaskExt": "0x00c001ff",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00C001FFff",
- "UMaskExt": "0x00C001FF",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; All from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c001ff01",
- "UMaskExt": "0x00c001ff",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; Hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c001fd01",
- "UMaskExt": "0x00c001fd",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; CRd hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c80ffd01",
- "UMaskExt": "0x00c80ffd",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c817fd01",
- "UMaskExt": "0x00c817fd",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00ccc7fd01",
- "UMaskExt": "0x00ccc7fd",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c807fd01",
- "UMaskExt": "0x00c807fd",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; Misses from Local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+ "BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c001fe01",
- "UMaskExt": "0x00c001fe",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; CRd misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+ "BriefDescription": "Read request for 4 bytes made by IIO Part1 to Memory",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c80ffe01",
- "UMaskExt": "0x00c80ffe",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
+ "BriefDescription": "Read request for 4 bytes made by IIO Part2 to Memory",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00ccc7fe01",
- "UMaskExt": "0x00ccc7fe",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+ "BriefDescription": "Read request for 4 bytes made by IIO Part3 to Memory",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c807fe01",
- "UMaskExt": "0x00c807fe",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; All from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+ "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c001ff04",
- "UMaskExt": "0x00c001ff",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; Hits from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c001fd04",
- "UMaskExt": "0x00c001fd",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; Misses from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c001fe04",
- "UMaskExt": "0x00c001fe",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO misses from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+ "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c803fe04",
- "UMaskExt": "0x00c803fe",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; ITOM misses from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+ "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00cc43fe04",
- "UMaskExt": "0x00cc43fe",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : IRQ - iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
+ "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : PRQ - IOSF",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : IPQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000008",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : IRQ - Non iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
+ "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000010",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
+ "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000020",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : RRQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ",
+ "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000040",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : WBQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.WBQ",
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000080",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00C000FF04",
- "UMaskExt": "0x00C000FF",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Local iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00C000FF01",
- "UMaskExt": "0x00C000FF",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Local iA and IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00C000FF05",
- "UMaskExt": "0x00C000FF",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All Snoops from Remote",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00C001FF08",
- "UMaskExt": "0x00C001FF",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Remote",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00C001FFC8",
- "UMaskExt": "0x00C001FF",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Hits",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x00000001",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Misses",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x00000002",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : MMCFG Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
+ "BriefDescription": ": Context cache hits",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
"PerPkg": "1",
- "UMaskExt": "0x00000020",
- "Unit": "CHA"
+ "PortMask": "0x0000",
+ "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : MMIO Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MMIO",
+ "BriefDescription": ": Context cache lookups",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
"PerPkg": "1",
- "UMaskExt": "0x00000040",
- "Unit": "CHA"
+ "PortMask": "0x0000",
+ "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Local Targets",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
+ "BriefDescription": ": IOTLB lookups first",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
"PerPkg": "1",
- "UMaskExt": "0x00000080",
- "Unit": "CHA"
+ "PortMask": "0x0000",
+ "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Remote Targets",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
+ "BriefDescription": "IOTLB Fills (same as IOTLB miss)",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.MISSES",
"PerPkg": "1",
- "UMaskExt": "0x00000100",
- "Unit": "CHA"
+ "PortMask": "0x0000",
+ "PublicDescription": "IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
+ "BriefDescription": ": IOMMU memory access",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
"PerPkg": "1",
- "UMaskExt": "0x00000200",
- "Unit": "CHA"
+ "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel",
+ "UMask": "0xc0",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
+ "BriefDescription": ": PWC Hit to a 2M page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
"PerPkg": "1",
- "UMaskExt": "0x00000400",
- "Unit": "CHA"
+ "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just NonCoherent",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
+ "BriefDescription": ": PWT Hit to a 256T page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_256T_HITS",
"PerPkg": "1",
- "UMaskExt": "0x01000000",
- "Unit": "CHA"
+ "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just ISOC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
+ "BriefDescription": ": PWC Hit to a 4K page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
"PerPkg": "1",
- "UMaskExt": "0x02000000",
- "Unit": "CHA"
+ "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+ "BriefDescription": ": PWC Hit to a 1G page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
"PerPkg": "1",
- "UMask": "0x00c88ffd01",
- "UMaskExt": "0x00c88ffd",
- "Unit": "CHA"
+ "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
+ "BriefDescription": ": Global IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.PWT_OCCUPANCY_MSB",
"PerPkg": "1",
- "UMask": "0x00c897fd01",
- "UMaskExt": "0x00c897fd",
- "Unit": "CHA"
+ "PortMask": "0x0000",
+ "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Opt hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
+ "BriefDescription": "PWT occupancy. Does not include 9th bit of occupancy (will undercount if PWT is greater than 255 per cycle).",
+ "EventCode": "0x42",
+ "EventName": "UNC_IIO_PWT_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x00c827fd01",
- "UMaskExt": "0x00c827fd",
- "Unit": "CHA"
+ "PortMask": "0x0000",
+ "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.",
+ "UMask": "0xff",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Opt Pref hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8a7fd01",
- "UMaskExt": "0x00c8a7fd",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c887fd01",
- "UMaskExt": "0x00c887fd",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; CRd Pref misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c88ffe01",
- "UMaskExt": "0x00c88ffe",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c897fe01",
- "UMaskExt": "0x00c897fe",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Opt misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c827fe01",
- "UMaskExt": "0x00c827fe",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8a7fe01",
- "UMaskExt": "0x00c8a7fe",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c887fe01",
- "UMaskExt": "0x00c887fe",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; ITOM hits from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00cc43fd04",
- "UMaskExt": "0x00cc43fd",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO hits from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c803fd04",
- "UMaskExt": "0x00c803fd",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; ItoM from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c803ff04",
- "UMaskExt": "0x00c803ff",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; ITOM from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00cc43ff04",
- "UMaskExt": "0x00cc43ff",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c807ff01",
- "UMaskExt": "0x00c807ff",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO prefetch from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c887ff01",
- "UMaskExt": "0x00c887ff",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00ccc7ff01",
- "UMaskExt": "0x00ccc7ff",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c817ff01",
- "UMaskExt": "0x00c817ff",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Opt from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c827ff01",
- "UMaskExt": "0x00c827ff",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Opt Pref from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8a7ff01",
- "UMaskExt": "0x00c8a7ff",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; CRd from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c80fff01",
- "UMaskExt": "0x00c80fff",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c88fff01",
- "UMaskExt": "0x00c88fff",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Pref from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c897ff01",
- "UMaskExt": "0x00c897ff",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00C896FE01",
- "UMaskExt": "0x00C896FE",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00C8977E01",
- "UMaskExt": "0x00C8977E",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c806fe01",
- "UMaskExt": "0x00c806fe",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8077e01",
- "UMaskExt": "0x00c8077e",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c886fe01",
- "UMaskExt": "0x00c886fe",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8877e01",
- "UMaskExt": "0x00c8877e",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "All LLC lines in E state that are victimized on a fill",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000002",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "All LLC lines in M state that are victimized on a fill",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000001",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "All LLC lines in S state that are victimized on a fill",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0000000004",
- "UMaskExt": "0x00000000",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00cd43fd04",
- "UMaskExt": "0x00cd43fd",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00cd43fe04",
- "UMaskExt": "0x00cd43fe",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c837fe01",
- "UMaskExt": "0x00c837fe",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c837fd01",
- "UMaskExt": "0x00c837fd",
- "Unit": "CHA"
+ "PortMask": "0x0001",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c837ff01",
- "UMaskExt": "0x00c837ff",
- "Unit": "CHA"
+ "PortMask": "0x0002",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xcc3fff01",
- "UMaskExt": "0xcc3fff",
- "Unit": "CHA"
+ "PortMask": "0x0004",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8f3fd04",
- "UMaskExt": "0x00c8f3fd",
- "Unit": "CHA"
+ "PortMask": "0x0008",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RdCur and FsRdCur misses from local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8f3fe04",
- "UMaskExt": "0x00c8f3fe",
- "Unit": "CHA"
+ "PortMask": "0x0010",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8f3fd04",
- "UMaskExt": "0x00c8f3fd",
- "Unit": "CHA"
+ "PortMask": "0x0020",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8f3fe04",
- "UMaskExt": "0x00c8f3fe",
- "Unit": "CHA"
+ "PortMask": "0x0040",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x00c8f3ff04",
- "UMaskExt": "0x00c8f3ff",
- "Unit": "CHA"
+ "PortMask": "0x0080",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
- {
- "BriefDescription": "TOR Inserts; LLCPrefCode hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+ {
+ "BriefDescription": "IRP Clockticks",
+ "EventCode": "0x01",
+ "EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x00cccffd01",
- "UMaskExt": "0x00cccffd",
- "Unit": "CHA"
+ "PublicDescription": "Number of IRP clock cycles while the event is enabled",
+ "Unit": "IRP"
},
{
- "BriefDescription": "TOR Inserts; LLCPrefData hits from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+ "BriefDescription": "FAF - request insert from TC.",
+ "EventCode": "0x18",
+ "EventName": "UNC_I_FAF_INSERTS",
"PerPkg": "1",
- "UMask": "0x00ccd7fd01",
- "UMaskExt": "0x00ccd7fd",
- "Unit": "CHA"
+ "Unit": "IRP"
},
{
- "BriefDescription": "TOR Inserts; LLCPrefData from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
+ "BriefDescription": "FAF occupancy",
+ "EventCode": "0x19",
+ "EventName": "UNC_I_FAF_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x00ccd7ff01",
- "UMaskExt": "0x00ccd7ff",
- "Unit": "CHA"
+ "Unit": "IRP"
},
{
- "BriefDescription": "TOR Inserts; LLCPrefCode misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
+ "BriefDescription": "FAF allocation -- sent to ADQ",
+ "EventCode": "0x16",
+ "EventName": "UNC_I_FAF_TRANSACTIONS",
"PerPkg": "1",
- "UMask": "0x00cccffe01",
- "UMaskExt": "0x00cccffe",
- "Unit": "CHA"
+ "Unit": "IRP"
},
{
- "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
+ "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
"PerPkg": "1",
- "UMask": "0x00ccd7fe01",
- "UMaskExt": "0x00ccd7fe",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "TOR Occupancy; LLCPrefCode hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
+ "BriefDescription": "Misc Events - Set 1 : Lost Forward",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
- "UMask": "0x00cccffd01",
- "UMaskExt": "0x00cccffd",
- "Unit": "CHA"
+ "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "TOR Occupancy; LLCPrefData hits from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
+ "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
- "UMask": "0x00ccd7fd01",
- "UMaskExt": "0x00ccd7fd",
- "Unit": "CHA"
+ "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "TOR Occupancy; LLCPrefData from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
+ "BriefDescription": "M2M Clockticks",
+ "EventCode": "0x01",
+ "EventName": "UNC_M2M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x00ccd7ff01",
- "UMaskExt": "0x00ccd7ff",
- "Unit": "CHA"
+ "PublicDescription": "Clockticks of the mesh to memory (M2M)",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Occupancy; LLCPrefCode misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
+ "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
"PerPkg": "1",
- "UMask": "0x00cccffe01",
- "UMaskExt": "0x00cccffe",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Occupancy; LLCPrefData misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
+ "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
"PerPkg": "1",
- "UMask": "0x00ccd7fe01",
- "UMaskExt": "0x00ccd7fe",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts; LLCPrefCode from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
+ "BriefDescription": "Number of reads in which direct to core transaction were overridden",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
- "UMask": "0x00cccfff01",
- "UMaskExt": "0x00cccfff",
- "Unit": "CHA"
+ "UMask": "0x3",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Occupancy; LLCPrefCode from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
+ "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
"PerPkg": "1",
- "UMask": "0x00cccfff01",
- "UMaskExt": "0x00cccfff",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
+ "BriefDescription": "Cycles when direct to Intel UPI was disabled",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
"PerPkg": "1",
- "UMask": "0x00c8168a01",
- "UMaskExt": "0x00c8168a",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
+ "BriefDescription": "Messages sent direct to the Intel UPI",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
"PerPkg": "1",
- "UMask": "0x00c8170a01",
- "UMaskExt": "0x00c8170a",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
+ "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+ "EventCode": "0x1c",
+ "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
"PerPkg": "1",
- "UMask": "0x00c8168601",
- "UMaskExt": "0x00c81686",
- "Unit": "CHA"
+ "UMask": "0x3",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
+ "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
"PerPkg": "1",
- "UMask": "0x00c8170601",
- "UMaskExt": "0x00c81706",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
+ "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
"PerPkg": "1",
- "UMask": "0x00C8978A01",
- "UMaskExt": "0x00C8978A",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
"PerPkg": "1",
- "UMask": "0x00C8968A01",
- "UMaskExt": "0x00C8968A",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
"PerPkg": "1",
- "UMask": "0x00C8970A01",
- "UMaskExt": "0x00C8970A",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
+ "BriefDescription": "Multi-socket cacheline Directory update from A to I",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
"PerPkg": "1",
- "UMask": "0x00C8978601",
- "UMaskExt": "0x00C89786",
- "Unit": "CHA"
+ "UMask": "0x320",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "BriefDescription": "Multi-socket cacheline Directory update from A to S",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
"PerPkg": "1",
- "UMask": "0x00C8968601",
- "UMaskExt": "0x00C89686",
- "Unit": "CHA"
+ "UMask": "0x340",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
- "UMask": "0x00C8970601",
- "UMaskExt": "0x00C89706",
- "Unit": "CHA"
+ "UMask": "0x301",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
+ "BriefDescription": "Multi-socket cacheline Directory update from I to A",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
"PerPkg": "1",
- "UMask": "0x00C80EFE01",
- "UMaskExt": "0x00C80EFE",
- "Unit": "CHA"
+ "UMask": "0x304",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
+ "BriefDescription": "Multi-socket cacheline Directory update from I to S",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
"PerPkg": "1",
- "UMask": "0x00C80F7E01",
- "UMaskExt": "0x00C80F7E",
- "Unit": "CHA"
+ "UMask": "0x302",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
+ "BriefDescription": "Multi-socket cacheline Directory update from S to A",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
"PerPkg": "1",
- "UMask": "0x00C88EFE01",
- "UMaskExt": "0x00C88EFE",
- "Unit": "CHA"
+ "UMask": "0x310",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
+ "BriefDescription": "Multi-socket cacheline Directory update from S to I",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
"PerPkg": "1",
- "UMask": "0x00C88F7E01",
- "UMaskExt": "0x00C88F7E",
- "Unit": "CHA"
+ "UMask": "0x308",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
+ "BriefDescription": "UNC_M2M_IMC_READS.TO_PMM",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2M_IMC_READS.TO_PMM",
"PerPkg": "1",
- "UMask": "0x00CD47FF01",
- "UMaskExt": "0x00CD47FF",
- "Unit": "CHA"
+ "UMask": "0x320",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
+ "BriefDescription": "PMM - All Channels",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
"PerPkg": "1",
- "UMask": "0x00cc27ff01",
- "UMaskExt": "0x00cc27ff",
- "Unit": "CHA"
+ "UMask": "0x1880",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
+ "BriefDescription": "Data Prefetches Dropped",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
"PerPkg": "1",
- "UMask": "0x00CC47FD01",
- "UMaskExt": "0x00CC47FD",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
+ "BriefDescription": "Data Prefetches Dropped",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
"PerPkg": "1",
- "UMask": "0x00CC47FE01",
- "UMaskExt": "0x00CC47FE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
+ "BriefDescription": "Data Prefetches Dropped",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
"PerPkg": "1",
- "UMask": "0x00C877DE01",
- "UMaskExt": "0x00C877DE",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
+ "BriefDescription": "Data Prefetches Dropped",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
"PerPkg": "1",
- "UMask": "0x00C87FDE01",
- "UMaskExt": "0x00C87FDE",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
+ "BriefDescription": "Data Prefetches Dropped",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x00C867FF01",
- "UMaskExt": "0x00C867FF",
- "Unit": "CHA"
+ "UMask": "0x5",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
+ "BriefDescription": ": UPI - All Channels",
+ "EventCode": "0x5d",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x00C867FE01",
- "UMaskExt": "0x00C867FE",
- "Unit": "CHA"
+ "UMask": "0xa",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
+ "BriefDescription": ": XPT - All Channels",
+ "EventCode": "0x5d",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x00C8678A01",
- "UMaskExt": "0x00C8678A",
- "Unit": "CHA"
+ "UMask": "0x5",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
+ "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x00C8668A01",
- "UMaskExt": "0x00C8668A",
- "Unit": "CHA"
+ "UMask": "0xa",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x00C8670A01",
- "UMaskExt": "0x00C8670A",
- "Unit": "CHA"
+ "PublicDescription": "Prefetch CAM Inserts : XPT -All Channels",
+ "UMask": "0x5",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+ "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations",
+ "EventCode": "0x02",
+ "EventName": "UNC_M2M_RxC_AD_INSERTS",
"PerPkg": "1",
- "UMask": "0x00C8678601",
- "UMaskExt": "0x00C86786",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+ "BriefDescription": "AD Ingress (from CMS) Occupancy",
+ "EventCode": "0x03",
+ "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x00C8668601",
- "UMaskExt": "0x00C86686",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "BriefDescription": "Tracker Inserts : Channel 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x00C8670601",
- "UMaskExt": "0x00C86706",
- "Unit": "CHA"
+ "UMask": "0x104",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
+ "BriefDescription": "Tracker Inserts : Channel 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x00C86FFF01",
- "UMaskExt": "0x00C86FFF",
- "Unit": "CHA"
+ "UMask": "0x204",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
+ "BriefDescription": "Tracker Occupancy : Channel 0",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x00C86FFE01",
- "UMaskExt": "0x00C86FFE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
+ "BriefDescription": "Tracker Occupancy : Channel 1",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x00C86F8A01",
- "UMaskExt": "0x00C86F8A",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
+ "BriefDescription": "M2P Clockticks",
+ "EventCode": "0x01",
+ "EventName": "UNC_M2P_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x00C86E8A01",
- "UMaskExt": "0x00C86E8A",
- "Unit": "CHA"
+ "PublicDescription": "Number of M2P clock cycles while the event is enabled",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M2P_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x00C86F0A01",
- "UMaskExt": "0x00C86F0A",
- "Unit": "CHA"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+ "BriefDescription": "M3UPI Clockticks",
+ "EventCode": "0x01",
+ "EventName": "UNC_M3UPI_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x00C86F8601",
- "UMaskExt": "0x00C86F86",
- "Unit": "CHA"
+ "PublicDescription": "Number of M2UPI clock cycles while the event is enabled",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+ "BriefDescription": "M3UPI CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x00C86E8601",
- "UMaskExt": "0x00C86E86",
- "Unit": "CHA"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+ "BriefDescription": "D2C Sent",
+ "EventCode": "0x2b",
+ "EventName": "UNC_M3UPI_D2C_SENT",
"PerPkg": "1",
- "UMask": "0x00C86F0601",
- "UMaskExt": "0x00C86F06",
- "Unit": "CHA"
+ "PublicDescription": "D2C Sent : Count cases BL sends direct to core",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
+ "BriefDescription": "D2U Sent",
+ "EventCode": "0x2a",
+ "EventName": "UNC_M3UPI_D2U_SENT",
"PerPkg": "1",
- "UMask": "0x00CC23FF04",
- "UMaskExt": "0x00CC23FF",
- "Unit": "CHA"
+ "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
+ "BriefDescription": "FlowQ Generated Prefetch",
+ "EventCode": "0x29",
+ "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
"PerPkg": "1",
- "UMask": "0x00C8C3FF04",
- "UMaskExt": "0x00C8C3FF",
- "Unit": "CHA"
+ "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
+ "BriefDescription": "UPI Clockticks",
+ "EventCode": "0x01",
+ "EventName": "UNC_UPI_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x00c8168a01",
- "UMaskExt": "0x00c8168a",
- "Unit": "CHA"
+ "PublicDescription": "Number of UPI LL clock cycles while the event is enabled",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
+ "BriefDescription": "Direct packet attempts : D2C",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
"PerPkg": "1",
- "UMask": "0x00c8170a01",
- "UMaskExt": "0x00c8170a",
- "Unit": "CHA"
+ "PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
+ "BriefDescription": "Cycles in L1",
+ "EventCode": "0x21",
+ "EventName": "UNC_UPI_L1_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x00c8168601",
- "UMaskExt": "0x00c81686",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x00c8170601",
- "UMaskExt": "0x00c81706",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMask": "0x00c8978a01",
- "UMaskExt": "0x00c8978a",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x00c8968a01",
- "UMaskExt": "0x00c8968a",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0x00c8970a01",
- "UMaskExt": "0x00c8970a",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
+ "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
"PerPkg": "1",
- "UMask": "0x00c8978601",
- "UMaskExt": "0x00c89786",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
"PerPkg": "1",
- "UMask": "0x00c8968601",
- "UMaskExt": "0x00c89686",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
"PerPkg": "1",
- "UMask": "0x00c8970601",
- "UMaskExt": "0x00c89706",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
+ "BriefDescription": "Valid Flits Received : All Data",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0x00c80efe01",
- "UMaskExt": "0x00c80efe",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
+ "BriefDescription": "Null FLITs received from any slot",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0x00c80f7e01",
- "UMaskExt": "0x00c80f7e",
- "Unit": "CHA"
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
+ "BriefDescription": "Valid Flits Received : Data",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0x00c88efe01",
- "UMaskExt": "0x00c88efe",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
+ "BriefDescription": "Valid Flits Received : Idle",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0x00c88f7e01",
- "UMaskExt": "0x00c88f7e",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+ "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
"PerPkg": "1",
- "UMask": "0x00c8c7ff01",
- "UMaskExt": "0x00c8c7ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+ "BriefDescription": "Valid Flits Received : LLCTRL",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0x00c8d7ff01",
- "UMaskExt": "0x00c8d7ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
+ "BriefDescription": "Valid Flits Received : All Non Data",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0x00cd47ff01",
- "UMaskExt": "0x00cd47ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
+ "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0x00cc57ff01",
- "UMaskExt": "0x00cc57ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
+ "BriefDescription": "Valid Flits Received : Protocol Header",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0x00cc27ff01",
- "UMaskExt": "0x00cc27ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
+ "BriefDescription": "Valid Flits Received : Slot 0",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0x00cc47ff01",
- "UMaskExt": "0x00cc47ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
+ "BriefDescription": "Valid Flits Received : Slot 1",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMask": "0x00cc47fd01",
- "UMaskExt": "0x00cc47fd",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
+ "BriefDescription": "Valid Flits Received : Slot 2",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
"PerPkg": "1",
- "UMask": "0x00cc47fe01",
- "UMaskExt": "0x00cc47fe",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
"PerPkg": "1",
- "UMask": "0x00c877de01",
- "UMaskExt": "0x00c877de",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
"PerPkg": "1",
- "UMask": "0x00c87fde01",
- "UMaskExt": "0x00c87fde",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
"PerPkg": "1",
- "UMask": "0x00c867ff01",
- "UMaskExt": "0x00c867ff",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
"PerPkg": "1",
- "UMask": "0x00c867fe01",
- "UMaskExt": "0x00c867fe",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
"PerPkg": "1",
- "UMask": "0x00c8678a01",
- "UMaskExt": "0x00c8678a",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
"PerPkg": "1",
- "UMask": "0x00c8668a01",
- "UMaskExt": "0x00c8668a",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
+ "BriefDescription": "Cycles in L0p",
+ "EventCode": "0x27",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x00c8670a01",
- "UMaskExt": "0x00c8670a",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x00c8678601",
- "UMaskExt": "0x00c86786",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMask": "0x00c8668601",
- "UMaskExt": "0x00c86686",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x00c8670601",
- "UMaskExt": "0x00c86706",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0x00c86fff01",
- "UMaskExt": "0x00c86fff",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
+ "BriefDescription": "Tx Flit Buffer Bypassed",
+ "EventCode": "0x41",
+ "EventName": "UNC_UPI_TxL_BYPASSED",
"PerPkg": "1",
- "UMask": "0x00c86ffe01",
- "UMaskExt": "0x00c86ffe",
- "Unit": "CHA"
+ "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
+ "BriefDescription": "Valid Flits Sent : All Data",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0x00c86f8a01",
- "UMaskExt": "0x00c86f8a",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
+ "BriefDescription": "All Null Flits",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0x00c86e8a01",
- "UMaskExt": "0x00c86e8a",
- "Unit": "CHA"
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
+ "BriefDescription": "Valid Flits Sent : Data",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0x00c86f0a01",
- "UMaskExt": "0x00c86f0a",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
+ "BriefDescription": "Valid Flits Sent : Idle",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0x00c86f8601",
- "UMaskExt": "0x00c86f86",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
+ "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
"PerPkg": "1",
- "UMask": "0x00c86e8601",
- "UMaskExt": "0x00c86e86",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
+ "BriefDescription": "Valid Flits Sent : LLCTRL",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0x00c86f0601",
- "UMaskExt": "0x00c86f06",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
+ "BriefDescription": "Valid Flits Sent : All Non Data",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0x00cc23ff04",
- "UMaskExt": "0x00cc23ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
+ "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0x00c8c3ff04",
- "UMaskExt": "0x00c8c3ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
+ "BriefDescription": "Valid Flits Sent : Protocol Header",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0x00cd43fd04",
- "UMaskExt": "0x00cd43fd",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
+ "BriefDescription": "Valid Flits Sent : Slot 0",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0x00cd43fe04",
- "UMaskExt": "0x00cd43fe",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : PMM Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
+ "BriefDescription": "Valid Flits Sent : Slot 1",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMaskExt": "0x00000008",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : PMM Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PMM",
+ "BriefDescription": "Valid Flits Sent : Slot 2",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
"PerPkg": "1",
- "UMaskExt": "0x00000008",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DDR Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+ "BriefDescription": "Tx Flit Buffer Allocations",
+ "EventCode": "0x40",
+ "EventName": "UNC_UPI_TxL_INSERTS",
"PerPkg": "1",
- "UMaskExt": "0x00000004",
- "Unit": "CHA"
+ "PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DDR Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.DDR",
+ "BriefDescription": "Tx Flit Buffer Occupancy",
+ "EventCode": "0x42",
+ "EventName": "UNC_UPI_TxL_OCCUPANCY",
"PerPkg": "1",
- "UMaskExt": "0x00000004",
- "Unit": "CHA"
+ "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+ "Unit": "UPI LL"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json
index 6299afe544cb..b1d5a605e0a7 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json
@@ -1,12 +1,90 @@
[
{
"BriefDescription": "PCU PCLK Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x01",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
- "UMaskExt": "0x00000000",
+ "PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Thermal Strongest Upper Limit Cycles",
+ "EventCode": "0x04",
+ "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Power Strongest Upper Limit Cycles",
+ "EventCode": "0x05",
+ "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Cycles spent changing Frequency",
+ "EventCode": "0x74",
+ "EventName": "UNC_P_FREQ_TRANS_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Package C State Residency - C2E",
+ "EventCode": "0x2b",
+ "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Package C State Residency - C6",
+ "EventCode": "0x2d",
+ "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Number of cores in C0",
+ "EventCode": "0x35",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Number of cores in C3",
+ "EventCode": "0x36",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Number of cores in C6",
+ "EventCode": "0x37",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "External Prochot",
+ "EventCode": "0x0a",
+ "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Internal Prochot",
+ "EventCode": "0x09",
+ "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json
index f591f4fedc0b..a1e3b8d2ebe7 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json
@@ -1,245 +1,165 @@
[
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
}
]
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 25/32] perf vendor events intel: Refresh silvermont events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (14 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 24/32] perf vendor events intel: Refresh sapphirerapids " Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 26/32] perf vendor events intel: Refresh skylake metrics and events Ian Rogers
` (6 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the silvermont events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/silvermont/cache.json | 133 ------------------
.../arch/x86/silvermont/floating-point.json | 1 -
.../arch/x86/silvermont/frontend.json | 8 --
.../arch/x86/silvermont/memory.json | 1 -
.../pmu-events/arch/x86/silvermont/other.json | 2 -
.../arch/x86/silvermont/pipeline.json | 35 -----
.../arch/x86/silvermont/virtual-memory.json | 7 -
7 files changed, 187 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/perf/pmu-events/arch/x86/silvermont/cache.json
index 7959504dff29..818e0664a3a6 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ALL",
"PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
- "Counter": "0,1",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.",
@@ -18,7 +16,6 @@
},
{
"BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
- "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_XQ.ALL",
"PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).",
@@ -26,7 +23,6 @@
},
{
"BriefDescription": "L2 cache request misses",
- "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.",
@@ -35,7 +31,6 @@
},
{
"BriefDescription": "L2 cache requests from this core",
- "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "All Loads",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PublicDescription": "This event counts the number of load ops retired.",
@@ -53,7 +47,6 @@
},
{
"BriefDescription": "All Stores",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PublicDescription": "This event counts the number of store ops retired.",
@@ -62,7 +55,6 @@
},
{
"BriefDescription": "Cross core or cross module hitm",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.HITM",
"PEBS": "1",
@@ -72,7 +64,6 @@
},
{
"BriefDescription": "Loads missed L1",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS",
"PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.",
@@ -81,7 +72,6 @@
},
{
"BriefDescription": "Loads hit L2",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS",
"PEBS": "1",
@@ -91,7 +81,6 @@
},
{
"BriefDescription": "Loads missed L2",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS",
"PEBS": "1",
@@ -101,7 +90,6 @@
},
{
"BriefDescription": "Loads missed UTLB",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.UTLB_MISS",
"PublicDescription": "This event counts the number of load ops retired that had UTLB miss.",
@@ -110,7 +98,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -119,623 +106,510 @@
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that have any response type.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that have any response type.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000013091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that have any response type.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000018008",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000008008",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400008008",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200008008",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that have any response type.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts writeback (modified to exclusive) that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000008",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080000008",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response type.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that have any response type.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads of partial cache lines (including UC and WC) that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Countsof demand RFO requests to write to partial cache lines that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that have any response type.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000012000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000010",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000010",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000010",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000010",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming store that miss L2.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680004800",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Any reissued load uops",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.ANY_LD",
"PublicDescription": "This event counts the number of load uops reissued from Rehabq.",
@@ -744,7 +618,6 @@
},
{
"BriefDescription": "Any reissued store uops",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.ANY_ST",
"PublicDescription": "This event counts the number of store uops reissued from Rehabq.",
@@ -753,7 +626,6 @@
},
{
"BriefDescription": "Loads blocked due to store data not ready",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.LD_BLOCK_STD_NOTREADY",
"PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time.",
@@ -762,7 +634,6 @@
},
{
"BriefDescription": "Loads blocked due to store forward restriction",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.LD_BLOCK_ST_FORWARD",
"PEBS": "1",
@@ -772,7 +643,6 @@
},
{
"BriefDescription": "Load uops that split cache line boundary",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.LD_SPLITS",
"PEBS": "1",
@@ -782,7 +652,6 @@
},
{
"BriefDescription": "Uops with lock semantics",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.LOCK",
"PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0).",
@@ -791,7 +660,6 @@
},
{
"BriefDescription": "Store address buffer full",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.STA_FULL",
"PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available.",
@@ -800,7 +668,6 @@
},
{
"BriefDescription": "Store uops that split cache line boundary",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.ST_SPLITS",
"PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json
index aa4faf110512..f2b1e8f08d68 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Stalls due to FP assists",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PublicDescription": "This event counts the number of times that pipeline stalled due to FP operations needing assists.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json
index 43e5e48f7212..c35da10f7133 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of baclears",
- "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.ALL",
"PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch.",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "Counts the number of JCC baclears",
- "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.COND",
"PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears.",
@@ -19,7 +17,6 @@
},
{
"BriefDescription": "Counts the number of RETURN baclears",
- "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.RETURN",
"PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears.",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction",
- "Counter": "0,1",
"EventCode": "0xE9",
"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
"PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction.",
@@ -37,7 +33,6 @@
},
{
"BriefDescription": "Instruction fetches",
- "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\nfetches.",
@@ -46,7 +41,6 @@
},
{
"BriefDescription": "Instruction fetches from Icache",
- "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "This event counts all instruction fetches from the instruction cache.",
@@ -55,7 +49,6 @@
},
{
"BriefDescription": "Icache miss",
- "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
@@ -64,7 +57,6 @@
},
{
"BriefDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count.",
- "Counter": "0,1",
"EventCode": "0xE7",
"EventName": "MS_DECODED.MS_ENTRY",
"PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/memory.json b/tools/perf/pmu-events/arch/x86/silvermont/memory.json
index 0f5fba43da4c..15ea45187210 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/memory.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Stalls due to Memory ordering",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/other.json b/tools/perf/pmu-events/arch/x86/silvermont/other.json
index 4db59d84c144..cff113adb823 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/other.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles code-fetch stalled due to any reason.",
- "Counter": "0,1",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ALL",
"PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.",
- "Counter": "0,1",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json
index e42a37eabc17..59f6116a7eae 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of branch instructions retired...",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -10,18 +9,15 @@
},
{
"BriefDescription": "Counts the number of taken branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
"PEBS": "2",
- "PEBScounters": "0,1",
"PublicDescription": "ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of near CALL branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CALL",
"PEBS": "1",
@@ -31,7 +27,6 @@
},
{
"BriefDescription": "Counts the number of far branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "1",
@@ -51,7 +45,6 @@
},
{
"BriefDescription": "Counts the number of JCC branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.JCC",
"PEBS": "1",
@@ -61,7 +54,6 @@
},
{
"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PEBS": "1",
@@ -71,7 +63,6 @@
},
{
"BriefDescription": "Counts the number of near relative CALL branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "1",
@@ -81,7 +72,6 @@
},
{
"BriefDescription": "Counts the number of near RET branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.RETURN",
"PEBS": "1",
@@ -91,7 +81,6 @@
},
{
"BriefDescription": "Counts the number of taken JCC branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PEBS": "1",
@@ -101,7 +90,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -110,7 +98,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PEBS": "1",
@@ -120,7 +107,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted JCC branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.JCC",
"PEBS": "1",
@@ -130,7 +116,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS": "1",
@@ -140,7 +125,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "1",
@@ -150,7 +134,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted taken JCC branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PEBS": "1",
@@ -160,7 +143,6 @@
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.CORE",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.",
"SampleAfterValue": "2000003",
@@ -168,7 +150,6 @@
},
{
"BriefDescription": "Core cycles when core is not halted",
- "Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"PublicDescription": "This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.",
@@ -176,7 +157,6 @@
},
{
"BriefDescription": "Reference cycles when core is not halted",
- "Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF",
"PublicDescription": "This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.",
@@ -185,7 +165,6 @@
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
- "Counter": "Fixed counter 3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.",
"SampleAfterValue": "2000003",
@@ -193,7 +172,6 @@
},
{
"BriefDescription": "Cycles the divider is busy. Does not imply a stall waiting for the divider.",
- "Counter": "0,1",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.ALL",
"PublicDescription": "Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions.",
@@ -202,7 +180,6 @@
},
{
"BriefDescription": "Fixed Counter: Counts the number of instructions retired",
- "Counter": "Fixed counter 1",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of \"retirement\" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.",
"SampleAfterValue": "2000003",
@@ -210,7 +187,6 @@
},
{
"BriefDescription": "Instructions retired",
- "Counter": "0,1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PublicDescription": "This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.",
@@ -218,7 +194,6 @@
},
{
"BriefDescription": "Counts all machine clears",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.ALL",
"PublicDescription": "Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions \"older\" than this one will be allowed to finish. This instruction and all \"younger\" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY.",
@@ -227,7 +202,6 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors.",
@@ -236,7 +210,6 @@
},
{
"BriefDescription": "Counts the number of cycles when no uops are allocated for any reason.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.ALL",
"PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle.",
@@ -245,7 +218,6 @@
},
{
"BriefDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.MISPREDICTS",
"PublicDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted.",
@@ -254,7 +226,6 @@
},
{
"BriefDescription": "Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED",
"PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidth.",
@@ -263,7 +234,6 @@
},
{
"BriefDescription": "Counts the number of cycles when no uops are allocated and a RATstall is asserted.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.RAT_STALL",
"SampleAfterValue": "200003",
@@ -271,7 +241,6 @@
},
{
"BriefDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.ROB_FULL",
"PublicDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available).",
@@ -280,7 +249,6 @@
},
{
"BriefDescription": "Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts.",
- "Counter": "0,1",
"EventCode": "0xCB",
"EventName": "RS_FULL_STALL.ALL",
"SampleAfterValue": "200003",
@@ -288,7 +256,6 @@
},
{
"BriefDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M",
- "Counter": "0,1",
"EventCode": "0xCB",
"EventName": "RS_FULL_STALL.MEC",
"PublicDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M.",
@@ -297,7 +264,6 @@
},
{
"BriefDescription": "Micro-ops retired",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PublicDescription": "This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops.",
@@ -306,7 +272,6 @@
},
{
"BriefDescription": "MSROM micro-ops retired",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MS",
"PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json
index b50cee3a5e4c..1be3fa5c4ad3 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Loads missed DTLB",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"PEBS": "1",
@@ -11,7 +10,6 @@
},
{
"BriefDescription": "Total cycles for all the page walks. (I-side and D-side)",
- "Counter": "0,1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.CYCLES",
"PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.",
@@ -20,7 +18,6 @@
},
{
"BriefDescription": "Duration of D-side page-walks in core cycles",
- "Counter": "0,1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
@@ -29,7 +26,6 @@
},
{
"BriefDescription": "D-side page-walks",
- "Counter": "0,1",
"EdgeDetect": "1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
@@ -39,7 +35,6 @@
},
{
"BriefDescription": "Duration of I-side page-walks in core cycles",
- "Counter": "0,1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
@@ -48,7 +43,6 @@
},
{
"BriefDescription": "I-side page-walks",
- "Counter": "0,1",
"EdgeDetect": "1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
@@ -58,7 +52,6 @@
},
{
"BriefDescription": "Total page walks that are completed (I-side and D-side)",
- "Counter": "0,1",
"EdgeDetect": "1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.WALKS",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 26/32] perf vendor events intel: Refresh skylake metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (15 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 25/32] perf vendor events intel: Refresh silvermont events Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 27/32] perf vendor events intel: Refresh skylakex " Ian Rogers
` (5 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the skylake metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/skylake/cache.json | 660 ------------------
.../arch/x86/skylake/floating-point.json | 14 -
.../pmu-events/arch/x86/skylake/frontend.json | 109 ---
.../pmu-events/arch/x86/skylake/memory.json | 358 ----------
.../pmu-events/arch/x86/skylake/other.json | 4 -
.../pmu-events/arch/x86/skylake/pipeline.json | 192 -----
.../arch/x86/skylake/skl-metrics.json | 155 ++--
.../arch/x86/skylake/uncore-cache.json | 18 -
.../arch/x86/skylake/uncore-other.json | 31 +-
.../arch/x86/skylake/virtual-memory.json | 56 --
10 files changed, 103 insertions(+), 1494 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json
index c3183819bf52..1538ddb5752f 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "L1D miss outstandings duration in cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.NON_SILENT",
"SampleAfterValue": "200003",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.SILENT",
"SampleAfterValue": "200003",
@@ -81,8 +65,6 @@
},
{
"BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.USELESS_HWPF",
"SampleAfterValue": "200003",
@@ -90,8 +72,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.USELESS_PREF",
"SampleAfterValue": "200003",
@@ -99,8 +79,6 @@
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts the total number of L2 code requests.",
@@ -109,8 +87,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -119,8 +95,6 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PublicDescription": "Demand requests that miss L2 cache.",
@@ -129,8 +103,6 @@
},
{
"BriefDescription": "Demand requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"PublicDescription": "Demand requests to L2 cache.",
@@ -139,8 +111,6 @@
},
{
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
@@ -149,8 +119,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -159,8 +127,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
@@ -169,8 +135,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
@@ -179,8 +143,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
@@ -189,8 +151,6 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -199,8 +159,6 @@
},
{
"BriefDescription": "All requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"PublicDescription": "All requests that miss L2 cache.",
@@ -209,8 +167,6 @@
},
{
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
@@ -219,8 +175,6 @@
},
{
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
@@ -229,8 +183,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"PublicDescription": "All L2 requests.",
@@ -239,8 +191,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
@@ -249,8 +199,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
@@ -259,8 +207,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
@@ -269,8 +215,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL057",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
@@ -280,8 +224,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL057",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
@@ -291,8 +233,6 @@
},
{
"BriefDescription": "All retired load instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
@@ -302,24 +242,18 @@
},
{
"BriefDescription": "All retired store instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x82"
},
{
"BriefDescription": "All retired memory instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ANY",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Counts all retired memory instructions - loads and stores.",
"SampleAfterValue": "2000003",
@@ -327,8 +261,6 @@
},
{
"BriefDescription": "Retired load instructions with locked access.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
@@ -338,8 +270,6 @@
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
@@ -350,12 +280,9 @@
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
@@ -363,8 +290,6 @@
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
@@ -375,12 +300,9 @@
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
@@ -388,8 +310,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
@@ -400,8 +320,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
@@ -412,8 +330,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -423,8 +339,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
@@ -435,8 +349,6 @@
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
@@ -446,8 +358,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
@@ -458,8 +368,6 @@
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
@@ -470,8 +378,6 @@
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
@@ -482,8 +388,6 @@
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
@@ -494,8 +398,6 @@
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
@@ -506,8 +408,6 @@
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
@@ -518,8 +418,6 @@
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
@@ -530,8 +428,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -540,8 +436,6 @@
},
{
"BriefDescription": "Any memory transaction that reached the SQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
@@ -550,8 +444,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
@@ -560,8 +452,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -570,8 +460,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -580,8 +468,6 @@
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
@@ -590,8 +476,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -600,8 +484,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -611,8 +493,6 @@
},
{
"BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -622,8 +502,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -633,8 +511,6 @@
},
{
"BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -644,8 +520,6 @@
},
{
"BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
@@ -654,8 +528,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
@@ -664,8 +536,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -674,8 +544,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -684,8 +552,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -694,2072 +560,1554 @@
},
{
"BriefDescription": "Counts all demand code readshave any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC01C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4001C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x401C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data readshave any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC01C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4001C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x401C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC01C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4001C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x401C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requestshave any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC01C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4001C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x401C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC0028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of cache line split locks sent to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
@@ -2768,8 +2116,6 @@
},
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA",
"SampleAfterValue": "2000003",
@@ -2777,8 +2123,6 @@
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"SampleAfterValue": "2000003",
@@ -2786,8 +2130,6 @@
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0",
"SampleAfterValue": "2000003",
@@ -2795,8 +2137,6 @@
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json
index d6cee5ae4402..eb83fa537e7d 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/perf/pmu-events/arch/x86/skylake/frontend.json
index 8633ee406813..13ccf50db43d 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
@@ -40,13 +32,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
@@ -54,13 +43,10 @@
"PEBS": "1",
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
@@ -68,39 +54,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
@@ -108,26 +85,20 @@
"PEBS": "2",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
"MSRValue": "0x408006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
@@ -135,39 +106,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x400206",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
"MSRValue": "0x410006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
@@ -175,39 +137,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x200206",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
"MSRIndex": "0x3F7",
"MSRValue": "0x300206",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
@@ -215,52 +168,40 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
"MSRValue": "0x400406",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
"MSRValue": "0x420006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x404006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
@@ -268,13 +209,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
@@ -282,13 +220,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
"PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
@@ -297,8 +232,6 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
"SampleAfterValue": "200003",
@@ -306,8 +239,6 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
"SampleAfterValue": "200003",
@@ -315,8 +246,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL",
"SampleAfterValue": "200003",
@@ -324,8 +253,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -335,8 +262,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -346,8 +271,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -357,8 +280,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -368,8 +289,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -379,8 +298,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
@@ -389,8 +306,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -400,8 +315,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -410,8 +323,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -421,8 +332,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -432,8 +341,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
@@ -442,8 +349,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -454,8 +359,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
@@ -464,8 +367,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -474,8 +375,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -485,8 +384,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -496,8 +393,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -507,8 +402,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -518,8 +411,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/memory.json b/tools/perf/pmu-events/arch/x86/skylake/memory.json
index 74ea4ccb4c9a..588ad6059a13 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_EVENTS",
"SampleAfterValue": "2000003",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_MEM",
"SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
@@ -60,8 +48,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_TIMER",
"SampleAfterValue": "2000003",
@@ -69,8 +55,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
"SampleAfterValue": "2000003",
@@ -78,8 +62,6 @@
},
{
"BriefDescription": "Number of times an HLE execution successfully committed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
@@ -88,8 +70,6 @@
},
{
"BriefDescription": "Number of times an HLE execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
@@ -98,8 +78,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL089",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
@@ -109,8 +87,6 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -119,13 +95,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -134,13 +107,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -149,13 +119,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -164,13 +131,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -179,13 +143,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -194,13 +155,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -209,13 +167,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -224,13 +179,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Demand Data Read requests who miss L3 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"PublicDescription": "Demand Data Read requests who miss L3 cache.",
@@ -239,8 +191,6 @@
},
{
"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
@@ -249,8 +199,6 @@
},
{
"BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
"SampleAfterValue": "2000003",
@@ -258,8 +206,6 @@
},
{
"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
@@ -268,1064 +214,798 @@
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x20001C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFC400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x203C400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7C400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC4000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2004000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x44000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x20001C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFC400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x203C400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7C400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC4000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2004000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x44000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x20001C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFC400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x203C400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7C400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC4000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2004000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x44000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x20001C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFC408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x203C408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7C408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC4008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2004008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x44008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -1335,8 +1015,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
"PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -1345,8 +1023,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
"PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -1355,8 +1031,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
@@ -1365,8 +1039,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_TIMER",
"SampleAfterValue": "2000003",
@@ -1374,8 +1046,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
"PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
@@ -1384,8 +1054,6 @@
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.",
@@ -1394,8 +1062,6 @@
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
@@ -1404,8 +1070,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@@ -1413,8 +1077,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -1423,8 +1085,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -1433,8 +1093,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
@@ -1443,8 +1101,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
@@ -1453,8 +1109,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY",
"SampleAfterValue": "2000003",
@@ -1462,8 +1116,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -1472,8 +1124,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -1482,8 +1132,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -1492,8 +1140,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -1502,8 +1148,6 @@
},
{
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -1512,8 +1156,6 @@
},
{
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json
index 8f4bc8892c47..9f3a9dffb807 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/other.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of hardware interrupts received by the processor.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.RECEIVED",
"PublicDescription": "Counts the number of hardware interruptions received by the processor.",
@@ -10,8 +8,6 @@
"UMask": "0x1"
},
{
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x09",
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json
index 79fda10ec4bb..cf35a535c2f6 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
@@ -45,8 +37,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
@@ -56,8 +46,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -68,8 +56,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
@@ -80,8 +66,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
@@ -92,8 +76,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
@@ -104,8 +86,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
@@ -115,8 +95,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
@@ -124,8 +102,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -135,8 +111,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -146,8 +120,6 @@
},
{
"BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -157,8 +129,6 @@
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -167,8 +137,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003",
@@ -176,8 +144,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003",
@@ -186,8 +152,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003",
@@ -195,8 +159,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003",
@@ -204,8 +166,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
@@ -213,8 +173,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003",
@@ -223,8 +181,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003",
@@ -232,8 +188,6 @@
},
{
"BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x3C",
@@ -243,8 +197,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -253,16 +205,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -271,16 +219,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -289,8 +233,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -299,8 +241,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -309,8 +249,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -319,8 +257,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -329,8 +265,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "20",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -339,8 +273,6 @@
},
{
"BriefDescription": "Total execution stalls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -349,8 +281,6 @@
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
@@ -359,8 +289,6 @@
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -369,8 +297,6 @@
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -379,8 +305,6 @@
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -389,8 +313,6 @@
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
"SampleAfterValue": "2000003",
@@ -398,8 +320,6 @@
},
{
"BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
"PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -408,8 +328,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
@@ -418,8 +336,6 @@
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
@@ -428,8 +344,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue": "2000003",
@@ -437,8 +351,6 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
@@ -447,8 +359,6 @@
},
{
"BriefDescription": "Number of all retired NOP instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.NOP",
@@ -458,8 +368,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
@@ -470,8 +378,6 @@
},
{
"BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.",
- "Counter": "0,2,3",
- "CounterHTOff": "0,2,3",
"CounterMask": "10",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
@@ -484,8 +390,6 @@
},
{
"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
"SampleAfterValue": "2000003",
@@ -493,8 +397,6 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
"PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
@@ -504,8 +406,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue": "2000003",
@@ -513,8 +413,6 @@
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -523,8 +421,6 @@
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
@@ -533,8 +429,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -543,8 +437,6 @@
},
{
"BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
@@ -553,8 +445,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -564,8 +454,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -575,8 +463,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
@@ -585,8 +471,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -596,8 +480,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -606,8 +488,6 @@
},
{
"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY",
"SampleAfterValue": "100003",
@@ -615,8 +495,6 @@
},
{
"BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
"PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
@@ -625,8 +503,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "Counts resource-related stall cycles.",
@@ -635,8 +511,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
@@ -645,8 +519,6 @@
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
@@ -655,8 +527,6 @@
},
{
"BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.PAUSE_INST",
"SampleAfterValue": "2000003",
@@ -664,8 +534,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -674,8 +542,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -687,8 +553,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
@@ -697,8 +561,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
@@ -707,8 +569,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
@@ -717,8 +577,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
@@ -727,8 +585,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
@@ -737,8 +593,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
@@ -747,8 +601,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
@@ -757,8 +609,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
@@ -767,8 +617,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Number of uops executed from any thread.",
@@ -777,8 +625,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -787,8 +633,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -797,8 +641,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -807,8 +649,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -817,8 +657,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -828,8 +666,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -839,8 +675,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -850,8 +684,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -861,8 +693,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -872,8 +702,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -884,8 +712,6 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -894,8 +720,6 @@
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87",
"PublicDescription": "Counts the number of x87 uops executed.",
@@ -904,8 +728,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
@@ -914,8 +736,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue": "2000003",
@@ -923,8 +743,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -935,8 +753,6 @@
},
{
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
@@ -945,8 +761,6 @@
},
{
"BriefDescription": "Number of macro-fused uops retired. (non precise)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
@@ -955,8 +769,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PublicDescription": "Counts the retirement slots used.",
@@ -965,8 +777,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -977,8 +787,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json
index f138b9836b51..972d3744c2c8 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json
@@ -41,7 +41,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
"MetricName": "tma_mispredicts_resteers",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -49,7 +49,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
- "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+ "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
"MetricName": "tma_clears_resteers",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -120,7 +120,7 @@
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -128,7 +128,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -144,7 +144,7 @@
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_backend_bound",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
@@ -152,7 +152,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -198,7 +198,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
+ "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -230,7 +230,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l2_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
@@ -246,7 +246,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "((18.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + (16.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+ "MetricExpr": "(18.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 16.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -254,7 +254,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "(16.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+ "MetricExpr": "16.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -262,7 +262,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "(6.5 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+ "MetricExpr": "6.5 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -270,7 +270,7 @@
},
{
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_sq_full",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -278,7 +278,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)",
+ "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -310,7 +310,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -318,7 +318,7 @@
},
{
"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "(22 * Average_Frequency) * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
+ "MetricExpr": "22 * Average_Frequency * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
"MetricName": "tma_false_sharing",
"PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
@@ -372,7 +372,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
+ "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS)",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -427,7 +427,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_alu_op_utilization",
"ScaleUnit": "100%"
@@ -483,7 +483,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricExpr": "tma_port_4",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_store_op_utilization",
"ScaleUnit": "100%"
@@ -622,7 +622,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -652,19 +652,19 @@
},
{
"BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "Memory_Bandwidth"
},
{
"BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
"MetricGroup": "Mem;MemoryLat;Offcore",
"MetricName": "Memory_Latency"
},
{
"BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) ",
+ "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
"MetricGroup": "Mem;MemoryTLB;Offcore",
"MetricName": "Memory_Data_TLBs"
},
@@ -737,32 +737,32 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "FP_Arith_Utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
- "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
+ "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
"MetricGroup": "Cor;SMT",
"MetricName": "Core_Bound_Likely"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
@@ -804,13 +804,13 @@
},
{
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP"
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricGroup": "Flops;InsType",
"MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@@ -905,7 +905,7 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts",
"MetricName": "Branch_Misprediction_Cost"
},
@@ -947,55 +947,55 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI_Load"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem;Offcore",
"MetricName": "L2MPKI_All"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2MPKI_Load"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_All"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_Load"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "FB_HPKI"
},
@@ -1008,25 +1008,25 @@
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "L3_Cache_Access_BW"
},
@@ -1056,19 +1056,19 @@
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -1081,7 +1081,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@@ -1099,74 +1099,99 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+ "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+ "MetricExpr": "MEM_Parallel_Requests",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Request_Latency"
},
{
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+ "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests"
},
+ {
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_REQUESTS.DATA_READ) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
+ },
{
"BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "arb@event\\=0x80\\,umask\\=0x2@ / arb@event\\=0x80\\,umask\\=0x2\\,cmask\\=1@",
+ "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ@thresh\\=1@",
"MetricGroup": "Mem;MemoryBW;SoC",
"MetricName": "MEM_Parallel_Reads"
},
+ {
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "UNC_CLOCK.SOCKET",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
+ },
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
+ {
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
+ },
{
"BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
index edb1014bee0f..ec9463c94ffe 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
@@ -11,7 +10,6 @@
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
@@ -21,7 +19,6 @@
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
@@ -31,7 +28,6 @@
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
@@ -41,7 +37,6 @@
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
@@ -51,7 +46,6 @@
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
@@ -61,7 +55,6 @@
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
@@ -71,7 +64,6 @@
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
@@ -81,7 +73,6 @@
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
@@ -91,7 +82,6 @@
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
@@ -101,41 +91,33 @@
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"UMask": "0x44",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
- "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"UMask": "0x41",
"Unit": "CBO"
}
diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
index bf5d4acdd6b8..e6d4cd625597 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
@@ -1,12 +1,10 @@
[
{
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
- "Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
- "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
@@ -14,8 +12,7 @@
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
@@ -24,8 +21,7 @@
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
- "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
@@ -33,43 +29,42 @@
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
"PerPkg": "1",
- "PublicDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
- "UMask": "0x02",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
"PerPkg": "1",
- "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
"PerPkg": "1",
- "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
- "Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
- "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"UMask": "0x20",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
- "Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json
index dd334b416c57..f59405877ae8 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 1G page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 4K page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@@ -102,8 +82,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@@ -113,8 +91,6 @@
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -123,8 +99,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 1G page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -133,8 +107,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -143,8 +115,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 4K page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -153,8 +123,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -163,8 +131,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4f",
"EventName": "EPT.WALK_PENDING",
"PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
@@ -173,8 +139,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -183,8 +147,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
@@ -193,8 +155,6 @@
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -202,8 +162,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
@@ -213,8 +171,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -223,8 +179,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -233,8 +187,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -243,8 +195,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -253,8 +203,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
@@ -263,8 +211,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -273,8 +219,6 @@
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 27/32] perf vendor events intel: Refresh skylakex metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (16 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 26/32] perf vendor events intel: Refresh skylake metrics and events Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 28/32] perf vendor events intel: Refresh snowridgex events Ian Rogers
` (4 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the skylakex metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. uncore-other.json
changes due to events now being sorted. The formatting changes
increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/skylakex/cache.json | 368 -
.../arch/x86/skylakex/floating-point.json | 18 -
.../arch/x86/skylakex/frontend.json | 109 -
.../pmu-events/arch/x86/skylakex/memory.json | 310 -
.../pmu-events/arch/x86/skylakex/other.json | 30 -
.../arch/x86/skylakex/pipeline.json | 194 -
.../arch/x86/skylakex/skx-metrics.json | 2134 +-
.../arch/x86/skylakex/uncore-memory.json | 2303 +-
.../arch/x86/skylakex/uncore-other.json | 29356 +++++++++-------
.../arch/x86/skylakex/uncore-power.json | 45 +-
.../arch/x86/skylakex/virtual-memory.json | 56 -
11 files changed, 18426 insertions(+), 16497 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
index e21010c0df41..92da692795e7 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "L1D miss outstandings duration in cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.NON_SILENT",
"PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped.",
@@ -73,8 +59,6 @@
},
{
"BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.SILENT",
"SampleAfterValue": "200003",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.USELESS_HWPF",
"SampleAfterValue": "200003",
@@ -91,8 +73,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Deprecated": "1",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.USELESS_PREF",
@@ -101,8 +81,6 @@
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts the total number of L2 code requests.",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -121,8 +97,6 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PublicDescription": "Demand requests that miss L2 cache.",
@@ -131,8 +105,6 @@
},
{
"BriefDescription": "Demand requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"PublicDescription": "Demand requests to L2 cache.",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
@@ -151,8 +121,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -161,8 +129,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
@@ -171,8 +137,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
@@ -181,8 +145,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
@@ -191,8 +153,6 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -201,8 +161,6 @@
},
{
"BriefDescription": "All requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"PublicDescription": "All requests that miss L2 cache.",
@@ -211,8 +169,6 @@
},
{
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
@@ -221,8 +177,6 @@
},
{
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
@@ -231,8 +185,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"PublicDescription": "All L2 requests.",
@@ -241,8 +193,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
@@ -251,8 +201,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
@@ -261,8 +209,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
@@ -271,8 +217,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL057",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
@@ -282,8 +226,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL057",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
@@ -293,8 +235,6 @@
},
{
"BriefDescription": "All retired load instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
@@ -304,24 +244,18 @@
},
{
"BriefDescription": "All retired store instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x82"
},
{
"BriefDescription": "All retired memory instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ANY",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Counts all retired memory instructions - loads and stores.",
"SampleAfterValue": "2000003",
@@ -329,8 +263,6 @@
},
{
"BriefDescription": "Retired load instructions with locked access.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
@@ -340,8 +272,6 @@
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
@@ -352,12 +282,9 @@
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
@@ -365,8 +292,6 @@
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
@@ -377,12 +302,9 @@
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
@@ -390,8 +312,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
@@ -402,8 +322,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
@@ -414,8 +332,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -425,8 +341,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
@@ -437,8 +351,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
@@ -449,8 +361,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
@@ -460,8 +370,6 @@
},
{
"BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
@@ -472,8 +380,6 @@
},
{
"BriefDescription": "Retired load instructions whose data sources was remote HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
@@ -484,8 +390,6 @@
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
@@ -495,8 +399,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
@@ -507,8 +409,6 @@
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
@@ -519,8 +419,6 @@
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
@@ -531,8 +429,6 @@
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
@@ -543,8 +439,6 @@
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
@@ -555,8 +449,6 @@
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
@@ -567,8 +459,6 @@
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
@@ -579,8 +469,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -589,8 +477,6 @@
},
{
"BriefDescription": "Any memory transaction that reached the SQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
@@ -599,8 +485,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
@@ -609,8 +493,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -619,8 +501,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -629,8 +509,6 @@
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
@@ -639,8 +517,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -649,8 +525,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -660,8 +534,6 @@
},
{
"BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -671,8 +543,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -682,8 +552,6 @@
},
{
"BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -693,8 +561,6 @@
},
{
"BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
@@ -703,8 +569,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
@@ -713,8 +577,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -723,8 +585,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -733,8 +593,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -743,872 +601,654 @@
},
{
"BriefDescription": "Counts all demand & prefetch data reads that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of cache line split locks sent to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
@@ -1617,8 +1257,6 @@
},
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA",
"SampleAfterValue": "2000003",
@@ -1626,8 +1264,6 @@
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"SampleAfterValue": "2000003",
@@ -1635,8 +1271,6 @@
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0",
"SampleAfterValue": "2000003",
@@ -1644,8 +1278,6 @@
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
index 09810e3d688c..64dd36387209 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -81,8 +65,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json
index 8633ee406813..13ccf50db43d 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
@@ -40,13 +32,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
@@ -54,13 +43,10 @@
"PEBS": "1",
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
@@ -68,39 +54,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
@@ -108,26 +85,20 @@
"PEBS": "2",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
"MSRValue": "0x408006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
@@ -135,39 +106,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x400206",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
"MSRValue": "0x410006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
@@ -175,39 +137,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x200206",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
"MSRIndex": "0x3F7",
"MSRValue": "0x300206",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
@@ -215,52 +168,40 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
"MSRValue": "0x400406",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
"MSRValue": "0x420006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x404006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
@@ -268,13 +209,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
@@ -282,13 +220,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
"PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
@@ -297,8 +232,6 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
"SampleAfterValue": "200003",
@@ -306,8 +239,6 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
"SampleAfterValue": "200003",
@@ -315,8 +246,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL",
"SampleAfterValue": "200003",
@@ -324,8 +253,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -335,8 +262,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -346,8 +271,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -357,8 +280,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -368,8 +289,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -379,8 +298,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
@@ -389,8 +306,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -400,8 +315,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -410,8 +323,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -421,8 +332,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -432,8 +341,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
@@ -442,8 +349,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -454,8 +359,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
@@ -464,8 +367,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -474,8 +375,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -485,8 +384,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -496,8 +393,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -507,8 +402,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -518,8 +411,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/memory.json b/tools/perf/pmu-events/arch/x86/skylakex/memory.json
index a570fe3e7a2d..2b797dbc75fe 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_EVENTS",
"SampleAfterValue": "2000003",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_MEM",
"SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
@@ -60,8 +48,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_TIMER",
"SampleAfterValue": "2000003",
@@ -69,8 +55,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
"SampleAfterValue": "2000003",
@@ -78,8 +62,6 @@
},
{
"BriefDescription": "Number of times an HLE execution successfully committed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
@@ -88,8 +70,6 @@
},
{
"BriefDescription": "Number of times an HLE execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
@@ -98,8 +78,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL089",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
@@ -109,8 +87,6 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -119,13 +95,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -134,13 +107,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -149,13 +119,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -164,13 +131,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -179,13 +143,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -194,13 +155,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -209,13 +167,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -224,13 +179,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Demand Data Read requests who miss L3 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"PublicDescription": "Demand Data Read requests who miss L3 cache.",
@@ -239,8 +191,6 @@
},
{
"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
@@ -249,8 +199,6 @@
},
{
"BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
"SampleAfterValue": "2000003",
@@ -258,8 +206,6 @@
},
{
"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
@@ -268,872 +214,654 @@
},
{
"BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63FC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -1143,8 +871,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
"PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -1153,8 +879,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
"PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -1163,8 +887,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
@@ -1173,8 +895,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_TIMER",
"SampleAfterValue": "2000003",
@@ -1182,8 +902,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
"PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
@@ -1192,8 +910,6 @@
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.",
@@ -1202,8 +918,6 @@
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
@@ -1212,8 +926,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@@ -1221,8 +933,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -1231,8 +941,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -1241,8 +949,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
@@ -1251,8 +957,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
@@ -1261,8 +965,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY",
"SampleAfterValue": "2000003",
@@ -1270,8 +972,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -1280,8 +980,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -1290,8 +988,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -1300,8 +996,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -1310,8 +1004,6 @@
},
{
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -1320,8 +1012,6 @@
},
{
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/perf/pmu-events/arch/x86/skylakex/other.json
index 403805e7e581..cda8a7a45f0c 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.THROTTLE",
"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
"SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
"SampleAfterValue": "2000003",
@@ -59,8 +47,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
"SampleAfterValue": "2000003",
@@ -68,8 +54,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
"SampleAfterValue": "2000003",
@@ -77,8 +61,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
"SampleAfterValue": "2000003",
@@ -86,8 +68,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
"SampleAfterValue": "2000003",
@@ -95,8 +75,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
"SampleAfterValue": "2000003",
@@ -104,8 +82,6 @@
},
{
"BriefDescription": "Number of hardware interrupts received by the processor.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.RECEIVED",
"PublicDescription": "Counts the number of hardware interruptions received by the processor.",
@@ -114,8 +90,6 @@
},
{
"BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xFE",
"EventName": "IDI_MISC.WB_DOWNGRADE",
"PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
@@ -124,8 +98,6 @@
},
{
"BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xFE",
"EventName": "IDI_MISC.WB_UPGRADE",
"PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
@@ -134,8 +106,6 @@
},
{
"BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x09",
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json
index f085b9145952..64e1fe351333 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
@@ -45,8 +37,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
@@ -56,8 +46,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -68,8 +56,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
@@ -80,8 +66,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
@@ -92,8 +76,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
@@ -104,8 +86,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
@@ -115,8 +95,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
@@ -124,8 +102,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -135,8 +111,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -146,8 +120,6 @@
},
{
"BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -157,8 +129,6 @@
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -167,8 +137,6 @@
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
@@ -178,8 +146,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003",
@@ -187,8 +153,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003",
@@ -197,8 +161,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003",
@@ -206,8 +168,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003",
@@ -215,8 +175,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
@@ -224,8 +182,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003",
@@ -234,8 +190,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003",
@@ -243,8 +197,6 @@
},
{
"BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x3C",
@@ -254,8 +206,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -264,16 +214,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -282,16 +228,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -300,8 +242,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -310,8 +250,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -320,8 +258,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -330,8 +266,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -340,8 +274,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "20",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -350,8 +282,6 @@
},
{
"BriefDescription": "Total execution stalls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -360,8 +290,6 @@
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
@@ -370,8 +298,6 @@
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -380,8 +306,6 @@
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -390,8 +314,6 @@
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -400,8 +322,6 @@
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
"SampleAfterValue": "2000003",
@@ -409,8 +329,6 @@
},
{
"BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
"PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -419,8 +337,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
@@ -429,8 +345,6 @@
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
@@ -439,8 +353,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue": "2000003",
@@ -448,8 +360,6 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
@@ -458,8 +368,6 @@
},
{
"BriefDescription": "Number of all retired NOP instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.NOP",
@@ -469,8 +377,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
@@ -481,8 +387,6 @@
},
{
"BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.",
- "Counter": "0,2,3",
- "CounterHTOff": "0,2,3",
"CounterMask": "10",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
@@ -495,8 +399,6 @@
},
{
"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
"SampleAfterValue": "2000003",
@@ -504,8 +406,6 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
"PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
@@ -515,8 +415,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue": "2000003",
@@ -524,8 +422,6 @@
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -534,8 +430,6 @@
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
@@ -544,8 +438,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -554,8 +446,6 @@
},
{
"BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
@@ -564,8 +454,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -575,8 +463,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -586,8 +472,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
@@ -596,8 +480,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -607,8 +489,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -617,8 +497,6 @@
},
{
"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY",
"SampleAfterValue": "100003",
@@ -626,8 +504,6 @@
},
{
"BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
"PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
@@ -636,8 +512,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "Counts resource-related stall cycles.",
@@ -646,8 +520,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
@@ -656,8 +528,6 @@
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
@@ -666,8 +536,6 @@
},
{
"BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.PAUSE_INST",
"SampleAfterValue": "2000003",
@@ -675,8 +543,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -685,8 +551,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -698,8 +562,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
@@ -708,8 +570,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
@@ -718,8 +578,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
@@ -728,8 +586,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
@@ -738,8 +594,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
@@ -748,8 +602,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
@@ -758,8 +610,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
@@ -768,8 +618,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
@@ -778,8 +626,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Number of uops executed from any thread.",
@@ -788,8 +634,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -798,8 +642,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -808,8 +650,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -818,8 +658,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -828,8 +666,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -839,8 +675,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -850,8 +684,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -861,8 +693,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -872,8 +702,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -883,8 +711,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -895,8 +721,6 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -905,8 +729,6 @@
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87",
"PublicDescription": "Counts the number of x87 uops executed.",
@@ -915,8 +737,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
@@ -925,8 +745,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue": "2000003",
@@ -934,8 +752,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -946,8 +762,6 @@
},
{
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
@@ -956,8 +770,6 @@
},
{
"BriefDescription": "Number of macro-fused uops retired. (non precise)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
@@ -966,8 +778,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PublicDescription": "Counts the retirement slots used.",
@@ -976,8 +786,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -988,8 +796,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
index bc8e42554096..1f8d60cce3ce 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
@@ -1,1513 +1,1497 @@
[
{
- "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
- "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
- "MetricGroup": "PGO;TopdownL1;tma_L1_group",
- "MetricName": "tma_frontend_bound",
- "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+ "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "Mispredictions"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
- "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
- "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_latency",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "Memory_Bandwidth"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
- "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / CLKS",
- "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_icache_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
+ "MetricGroup": "Mem;MemoryLat;Offcore",
+ "MetricName": "Memory_Latency"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
- "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS",
- "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_itlb_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
+ "MetricGroup": "Mem;MemoryTLB;Offcore",
+ "MetricName": "Memory_Data_TLBs"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
- "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_branch_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
+ "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
+ "MetricGroup": "Ret",
+ "MetricName": "Branching_Overhead"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_mispredicts_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+ "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+ "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
+ "MetricName": "Big_Code"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
- "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_clears_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+ "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
+ "MetricGroup": "Fed;FetchBW;Frontend",
+ "MetricName": "Instruction_Fetch_BW"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
- "MetricExpr": "9 * BACLEARS.ANY / CLKS",
- "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_unknown_branches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+ "MetricExpr": "INST_RETIRED.ANY / CLKS",
+ "MetricGroup": "Ret;Summary",
+ "MetricName": "IPC"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
- "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_dsb_switches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uops Per Instruction",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "UPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
- "MetricExpr": "ILD_STALL.LCP / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_lcp",
- "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW",
+ "MetricName": "UpTB"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
- "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS",
- "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_ms_switches",
- "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+ "MetricExpr": "1 / IPC",
+ "MetricGroup": "Mem;Pipeline",
+ "MetricName": "CPI"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
- "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
- "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_bandwidth",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "Pipeline",
+ "MetricName": "CLKS"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
- "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_mite",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+ "MetricExpr": "4 * CORE_CLKS",
+ "MetricGroup": "tma_L1_group",
+ "MetricName": "SLOTS"
},
{
- "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
- "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
- "MetricName": "tma_decoder0_alone",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of Executed- by Issued-Uops",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+ "MetricGroup": "Cor;Pipeline",
+ "MetricName": "Execute_per_Issue",
+ "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
- "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_dsb",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+ "MetricGroup": "Ret;SMT;tma_L1_group",
+ "MetricName": "CoreIPC"
},
{
- "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_bad_speculation",
- "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Floating Point Operations Per Cycle",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricGroup": "Flops;Ret",
+ "MetricName": "FLOPc"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_branch_mispredicts",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "FP_Arith_Utilization",
+ "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
- "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
- "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_machine_clears",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+ "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+ "MetricName": "ILP"
},
{
- "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_backend_bound",
- "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+ "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "Core_Bound_Likely"
},
{
- "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
- "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_memory_bound",
- "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
+ "MetricGroup": "SMT",
+ "MetricName": "CORE_CLKS"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
- "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l1_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+ "MetricGroup": "InsType",
+ "MetricName": "IpLoad"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
- "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_dtlb_load",
- "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+ "MetricGroup": "InsType",
+ "MetricName": "IpStore"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Fed;InsType",
+ "MetricName": "IpBranch"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "IpCall"
},
{
- "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
- "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_store_fwd_blk",
- "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+ "MetricName": "IpTB"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
- "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_lock_latency",
- "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch instructions per taken branch. ",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "BpTkBranch"
},
{
- "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
- "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_split_loads",
- "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpFLOP"
},
{
- "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
- "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_4k_aliasing",
- "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpArith",
+ "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
},
{
- "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
- "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS",
- "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_fb_full",
- "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_SP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l2_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_DP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l3_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX128",
+ "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "((44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (44 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_contested_accesses",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX256",
+ "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "(44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_data_sharing",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX512",
+ "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "(17 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_l3_hit_latency",
- "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+ "MetricGroup": "Prefetches",
+ "MetricName": "IpSWPF"
},
{
- "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_sq_full",
- "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+ "MetricExpr": "INST_RETIRED.ANY",
+ "MetricGroup": "Summary;tma_L1_group",
+ "MetricName": "Instructions"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_dram_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "Retire"
+ },
+ {
+ "BriefDescription": "",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+ "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+ "MetricName": "Execute"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_bandwidth",
- "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+ "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "Fetch_UpC"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_latency",
- "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+ "MetricGroup": "DSB;Fed;FetchBW",
+ "MetricName": "DSB_Coverage"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
- "MetricExpr": "(59.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_local_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT",
+ "MetricGroup": "DSBmiss",
+ "MetricName": "DSB_Switch_Cost"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
- "MetricExpr": "(127 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
+ "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "DSB_Misses"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
- "MetricExpr": "((89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_cache",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "IpDSB_Miss_Ret"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
- "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_store_bound",
- "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "IpMispredict"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 11 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_store_latency",
- "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "Branch_Misprediction_Cost"
},
{
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "((110 * Average_Frequency) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + (47.5 * Average_Frequency) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are non-taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_NT"
},
{
- "BriefDescription": "This metric represents rate of split store accesses",
- "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
- "MetricGroup": "TopdownL4;tma_store_bound_group",
- "MetricName": "tma_split_stores",
- "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are taken conditionals",
+ "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_TK"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
- "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_dtlb_store",
- "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are CALL or RET",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "CallRet"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "Jump"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
+ "MetricGroup": "Mem;MemoryBound;MemoryLat",
+ "MetricName": "Load_Miss_Real_Latency"
},
{
- "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
- "MetricExpr": "tma_backend_bound - tma_memory_bound",
- "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_core_bound",
- "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+ "MetricGroup": "Mem;MemoryBW;MemoryBound",
+ "MetricName": "MLP"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
- "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS",
- "MetricGroup": "TopdownL3;tma_core_bound_group",
- "MetricName": "tma_divider",
- "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
- "MetricName": "tma_ports_utilization",
- "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_0",
- "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Backend;CacheMisses;Mem",
+ "MetricName": "L2MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
- "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_serializing_operation",
- "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem;Offcore",
+ "MetricName": "L2MPKI_All"
},
{
- "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
- "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_mixing_vectors",
- "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2MPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_1",
- "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_All"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_2",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
- "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_3m",
- "ScaleUnit": "100%"
+ "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L3MPKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_alu_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "FB_HPKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
- "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_0",
- "ScaleUnit": "100%"
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+ "MetricConstraint": "NO_NMI_WATCHDOG",
+ "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "Page_Walks_Utilization"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_1",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_5",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_6",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_load_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_2",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+ "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_Silent_PKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_3",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+ "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_NonSilent_PKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_store_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "L1D_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_4",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "L2_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_7",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_retiring",
- "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Access_BW",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW_1T"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
- "MetricExpr": "tma_retiring - tma_heavy_operations",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_light_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average CPU Utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricGroup": "HPC;Summary",
+ "MetricName": "CPU_Utilization"
},
{
- "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
- "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
- "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_fp_arith",
- "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+ "MetricGroup": "Power;Summary",
+ "MetricName": "Average_Frequency"
},
{
- "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
- "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
- "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_x87_use",
- "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Giga Floating Point Operations Per Second",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "GFLOPs",
+ "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_scalar",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+ "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricGroup": "Power",
+ "MetricName": "Turbo_Utilization"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_vector",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
+ "MetricExpr": "(CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS)",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License0_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_128b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
+ "MetricExpr": "(CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS)",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License1_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_256b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
+ "MetricExpr": "(CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS)",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License2_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions."
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_512b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
+ "MetricGroup": "SMT",
+ "MetricName": "SMT_2T_Utilization"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
- "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_memory_operations",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_Utilization"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
- "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_fused_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_CPI"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
- "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_non_fused_branches",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "DRAM_BW_Use"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
- "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_nop_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
},
{
- "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
- "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_other_light_ops",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_heavy_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+ "MetricExpr": "1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@",
+ "MetricGroup": "Mem;MemoryLat;Server;SoC",
+ "MetricName": "MEM_DRAM_Read_Latency"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
- "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
- "MetricGroup": "TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_few_uops_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;Mem;Server;SoC",
+ "MetricName": "IO_Write_BW"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
- "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_microcode_sequencer",
- "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
+ "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;Mem;Server;SoC",
+ "MetricName": "IO_Read_BW"
},
{
- "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
- "MetricExpr": "100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_assists",
- "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "cha_0@event\\=0x0@",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
- "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_cisc",
- "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+ "MetricGroup": "Branches;OS",
+ "MetricName": "IpFarBranch"
},
{
- "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
- "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "Mispredictions"
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
},
{
- "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "Memory_Bandwidth"
+ "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricName": "cpu_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
- "MetricGroup": "Mem;MemoryLat;Offcore",
- "MetricName": "Memory_Latency"
+ "BriefDescription": "CPU operating frequency (in GHz)",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+ "MetricName": "cpu_operating_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) ",
- "MetricGroup": "Mem;MemoryTLB;Offcore",
- "MetricName": "Memory_Data_TLBs"
+ "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+ "MetricName": "cpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
- "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
- "MetricGroup": "Ret",
- "MetricName": "Branching_Overhead"
+ "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+ "MetricName": "loads_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
- "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
- "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
- "MetricName": "Big_Code"
+ "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+ "MetricName": "stores_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
- "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
- "MetricGroup": "Fed;FetchBW;Frontend",
- "MetricName": "Instruction_Fetch_BW"
+ "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+ "MetricName": "l1d_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
- "MetricExpr": "INST_RETIRED.ANY / CLKS",
- "MetricGroup": "Ret;Summary",
- "MetricName": "IPC"
+ "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+ "MetricName": "l1d_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Uops Per Instruction",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;Ret;Retire",
- "MetricName": "UPI"
+ "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+ "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW",
- "MetricName": "UpTB"
+ "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
- "MetricExpr": "1 / IPC",
- "MetricGroup": "Mem;Pipeline",
- "MetricName": "CPI"
+ "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+ "MetricName": "l2_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "Pipeline",
- "MetricName": "CLKS"
+ "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
- "MetricExpr": "4 * CORE_CLKS",
- "MetricGroup": "tma_L1_group",
- "MetricName": "SLOTS"
+ "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_code_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "The ratio of Executed- by Issued-Uops",
- "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
- "MetricGroup": "Cor;Pipeline",
- "MetricName": "Execute_per_Issue",
- "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+ "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY",
+ "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
- "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
- "MetricGroup": "Ret;SMT;tma_L1_group",
- "MetricName": "CoreIPC"
+ "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY",
+ "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
- "MetricGroup": "Flops;Ret",
- "MetricName": "FLOPc"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
+ "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "FP_Arith_Utilization",
- "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
+ "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
- "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
- "MetricName": "ILP"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
+ "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
- "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
- "MetricGroup": "Cor;SMT",
- "MetricName": "Core_Bound_Likely"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "itlb_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
- "MetricGroup": "SMT",
- "MetricName": "CORE_CLKS"
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "itlb_large_page_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
- "MetricGroup": "InsType",
- "MetricName": "IpLoad"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
- "MetricGroup": "InsType",
- "MetricName": "IpStore"
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2mb_large_page_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Branches;Fed;InsType",
- "MetricName": "IpBranch"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_store_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "IpCall"
+ "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)",
+ "MetricName": "numa_reads_addressed_to_local_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
- "MetricName": "IpTB"
+ "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)",
+ "MetricName": "numa_reads_addressed_to_remote_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Branch instructions per taken branch. ",
- "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "BpTkBranch"
+ "BriefDescription": "Uncore operating frequency in GHz",
+ "MetricExpr": "UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time",
+ "MetricName": "uncore_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpFLOP"
+ "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+ "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+ "MetricName": "upi_data_transmit_bw",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpArith",
- "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+ "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_SP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_DP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "DDR memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX128",
- "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_writes",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX256",
- "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "(UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_reads",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX512",
- "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_decoded_icache",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
- "MetricGroup": "Prefetches",
- "MetricName": "IpSWPF"
+ "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
- "MetricExpr": "INST_RETIRED.ANY",
- "MetricGroup": "Summary;tma_L1_group",
- "MetricName": "Instructions"
+ "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
- "MetricGroup": "Pipeline;Ret",
- "MetricName": "Retire"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "",
- "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
- "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
- "MetricName": "Execute"
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Average number of Uops issued by front-end when it issued something",
- "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
- "MetricGroup": "Fed;FetchBW",
- "MetricName": "Fetch_UpC"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
- "MetricGroup": "DSB;Fed;FetchBW",
- "MetricName": "DSB_Coverage"
+ "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+ "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
+ "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_frontend_bound",
+ "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT",
- "MetricGroup": "DSBmiss",
- "MetricName": "DSB_Switch_Cost"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+ "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
+ "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_latency",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
- "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "DSB_Misses"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+ "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_icache_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "IpDSB_Miss_Ret"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+ "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_itlb_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "IpMispredict"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+ "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_branch_resteers",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BrMispredicts",
- "MetricName": "Branch_Misprediction_Cost"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_mispredicts_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are non-taken conditionals",
- "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_NT"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+ "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_clears_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are taken conditionals",
- "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_TK"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+ "MetricExpr": "9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_unknown_branches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are CALL or RET",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "CallRet"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_dsb_switches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "Jump"
+ "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+ "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_lcp",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
- "MetricGroup": "Mem;MemoryBound;MemoryLat",
- "MetricName": "Load_Miss_Real_Latency"
+ "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+ "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_ms_switches",
+ "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
- "MetricGroup": "Mem;MemoryBW;MemoryBound",
- "MetricName": "MLP"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+ "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
+ "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_bandwidth",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+ "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_mite",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI_Load"
+ "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+ "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CORE_CLKS",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+ "MetricName": "tma_decoder0_alone",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "Backend;CacheMisses;Mem",
- "MetricName": "L2MPKI"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+ "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_dsb",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem;Offcore",
- "MetricName": "L2MPKI_All"
+ "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_bad_speculation",
+ "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2MPKI_Load"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_branch_mispredicts",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_All"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+ "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_machine_clears",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+ "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_backend_bound",
+ "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_Load"
+ "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
+ "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_memory_bound",
+ "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L3MPKI"
+ "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+ "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l1_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "FB_HPKI"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+ "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_dtlb_load",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
- "MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "Page_Walks_Utilization"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW"
+ "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW"
+ "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+ "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_store_fwd_blk",
+ "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+ "MetricExpr": "min((12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_lock_latency",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW"
+ "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+ "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_split_loads",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
- "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_Silent_PKI"
+ "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+ "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_4k_aliasing",
+ "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
- "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_NonSilent_PKI"
+ "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+ "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_fb_full",
+ "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "L1D_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l2_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "L2_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l3_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+ "MetricExpr": "min(((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_contested_accesses",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Access_BW",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW_1T"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+ "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_data_sharing",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
- "MetricGroup": "HPC;Summary",
- "MetricName": "CPU_Utilization"
+ "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+ "MetricExpr": "min((20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_l3_hit_latency",
+ "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
- "MetricGroup": "Power;Summary",
- "MetricName": "Average_Frequency"
+ "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_sq_full",
+ "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "GFLOPs",
- "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+ "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+ "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound, 1)",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_dram_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average Frequency Utilization relative nominal frequency",
- "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
- "MetricGroup": "Power",
- "MetricName": "Turbo_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_bandwidth",
+ "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
- "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License0_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
+ "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_latency",
+ "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
- "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License1_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+ "MetricExpr": "min((80 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_local_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
- "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License2_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions."
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+ "MetricExpr": "min((147.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
- "MetricGroup": "SMT",
- "MetricName": "SMT_2T_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+ "MetricExpr": "min(((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_cache",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "OS",
- "MetricName": "Kernel_Utilization"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+ "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_store_bound",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
- "MetricGroup": "OS",
- "MetricName": "Kernel_CPI"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_store_latency",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC",
- "MetricName": "DRAM_BW_Use"
+ "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+ "MetricExpr": "min((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_false_sharing",
+ "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "1000000000 * (cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x35\\,umask\\=0x21\\,config\\=0x40433@) / (Socket_CLKS / duration_time)",
- "MetricGroup": "Mem;MemoryLat;SoC",
- "MetricName": "MEM_Read_Latency"
+ "BriefDescription": "This metric represents rate of split store accesses",
+ "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_split_stores",
+ "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433\\,thresh\\=1@",
- "MetricGroup": "Mem;MemoryBW;SoC",
- "MetricName": "MEM_Parallel_Reads"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+ "MetricExpr": "min((9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS, 1)",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_dtlb_store",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
- "MetricExpr": "1000000000 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@",
- "MetricGroup": "Mem;MemoryLat;Server;SoC",
- "MetricName": "MEM_DRAM_Read_Latency"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_store - DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
- "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1000000000 / duration_time",
- "MetricGroup": "IoBW;Mem;Server;SoC",
- "MetricName": "IO_Write_BW"
+ "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
- "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1000000000 / duration_time",
- "MetricGroup": "IoBW;Mem;Server;SoC",
- "MetricName": "IO_Read_BW"
+ "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+ "MetricExpr": "tma_backend_bound - tma_memory_bound",
+ "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_core_bound",
+ "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Socket actual clocks when any core is active on that socket",
- "MetricExpr": "cha_0@event\\=0x0@",
- "MetricGroup": "SoC",
- "MetricName": "Socket_CLKS"
+ "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+ "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_divider",
+ "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
- "MetricGroup": "Branches;OS",
- "MetricName": "IpFarBranch"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+ "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD)",
+ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_ports_utilization",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_0",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+ "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_serializing_operation",
+ "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_mixing_vectors",
+ "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_1",
+ "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_2",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+ "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_3m",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_alu_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
+ "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_0",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "CPU operating frequency (in GHz)",
- "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "cpu_operating_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_1",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "loads_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_5",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "stores_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_6",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_load_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_2",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_3",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_store_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
+ "MetricExpr": "tma_store_op_utilization",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_4",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_7",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_code_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_retiring",
+ "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+ "MetricExpr": "tma_retiring - (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_light_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+ "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector",
+ "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fp_arith",
+ "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
- "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@ ) / ( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+ "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
+ "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_x87_use",
+ "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ ) / ( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_scalar",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ ) / ( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_vector",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_128b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_large_page_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_256b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_512b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2mb_large_page_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+ "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_memory_operations",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_store_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
+ "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fused_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_local_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
+ "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_non_fused_branches",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_remote_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+ "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_nop_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore operating frequency in GHz",
- "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "uncore_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+ "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_other_light_ops",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
- "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "upi_data_transmit_bw",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+ "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_heavy_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+ "MetricExpr": "tma_heavy_operations - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_few_uops_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_microcode_sequencer",
+ "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+ "MetricExpr": "min(100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_assists",
+ "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
- "MetricExpr": "(( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_writes",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+ "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_cisc",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
- "MetricExpr": "(( UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3 ) * 4 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_reads",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C3 residency percent per core",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_decoded_icache",
- "ScaleUnit": "1%"
+ "BriefDescription": "C6 residency percent per core",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
- "ScaleUnit": "1%"
+ "BriefDescription": "C7 residency percent per core",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_microcode_sequencer",
- "ScaleUnit": "1%"
+ "BriefDescription": "C2 residency percent per package",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C3 residency percent per package",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C6 residency percent per package",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_remote_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C7 residency percent per package",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
index 62941146e396..8784118123b4 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
@@ -1,540 +1,514 @@
[
- {
- "BriefDescription": "DRAM Page Activate commands sent due to a write request",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.WR",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_REG",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "DRAM Underfill Read CAS Commands issued",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "All DRAM Read CAS Commands issued (including underfills)",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "iMC"
- },
{
"BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "LLC_MISSES.MEM_READ",
"PerPkg": "1",
+ "PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read. This event includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
"ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "iMC"
},
- {
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_WMM",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "All DRAM Write CAS commands issued",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR",
- "PerPkg": "1",
- "UMask": "0xC",
- "Unit": "iMC"
- },
{
"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "LLC_MISSES.MEM_WRITE",
"PerPkg": "1",
+ "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
"ScaleUnit": "64Bytes",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM CAS Commands issued",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.ALL",
+ "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Memory controller clock ticks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_M_CLOCKTICKS",
+ "BriefDescription": "DRAM Activate Count; Activate due to Read",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.RD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x85",
- "EventName": "UNC_M_POWER_CHANNEL_PPD",
- "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
- "MetricName": "power_channel_ppd %",
+ "BriefDescription": "DRAM Page Activate commands sent due to a write request",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles Memory is in self refresh power mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x43",
- "EventName": "UNC_M_POWER_SELF_REFRESH",
- "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
- "MetricName": "power_self_refresh %",
+ "BriefDescription": "ACT command issued by 2 cycle bypass",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M_BYP_CMDS.ACT",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Pre-charges due to page misses",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "BriefDescription": "CAS command issued by 2 cycle bypass",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M_BYP_CMDS.CAS",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Pre-charge for reads",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.RD",
+ "BriefDescription": "PRE command issued by 2 cycle bypass",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M_BYP_CMDS.PRE",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS",
+ "BriefDescription": "All DRAM CAS Commands issued",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M_RPQ_OCCUPANCY",
+ "BriefDescription": "All DRAM Read CAS Commands issued (including underfills)",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
+ "PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read. This event includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.RD_ISOCH",
"PerPkg": "1",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x81",
- "EventName": "UNC_M_WPQ_OCCUPANCY",
+ "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
+ "PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count; Activate due to Read",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.RD",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.RD_RMM",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.BYP",
+ "BriefDescription": "DRAM Underfill Read CAS Commands issued",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request).",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "ACT command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M_BYP_CMDS.ACT",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.RD_WMM",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "CAS command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M_BYP_CMDS.CAS",
+ "BriefDescription": "All DRAM Write CAS commands issued",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "PRE command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M_BYP_CMDS.PRE",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.WR_ISOCH",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
"UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_WMM",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+ "EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_ISOCH",
+ "BriefDescription": "Memory controller clock ticks",
+ "EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts clockticks of the fixed frequency clock of the memory controller using one of the programmable counters.",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_ISOCH",
+ "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
+ "EventCode": "0xff",
+ "EventName": "UNC_M_CLOCKTICKS_F",
"PerPkg": "1",
- "UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that the precharge all command was sent.",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
- "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+ "EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of refreshes issued.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
- "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+ "EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of refreshes issued.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "ECC Correctable Errors",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.READ",
+ "EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.WRITE",
+ "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+ "EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+ "EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Channel DLLOFF Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
+ "EventCode": "0x85",
+ "EventName": "UNC_M_POWER_CHANNEL_PPD",
+ "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100",
+ "MetricName": "power_channel_ppd",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of.",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Critical Throttle Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M_POWER_PCU_THROTTLING",
"PerPkg": "1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Cycles Memory is in self refresh power mode",
+ "EventCode": "0x43",
+ "EventName": "UNC_M_POWER_SELF_REFRESH",
+ "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100",
+ "MetricName": "power_self_refresh",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
"UMask": "0x2",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
+ "EventCode": "0x2",
+ "EventName": "UNC_M_PRE_COUNT.BYP",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring. This does not include implicit precharge commands sent in auto-precharge mode.",
"UMask": "0x2",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Pre-charges due to page misses",
+ "EventCode": "0x2",
+ "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of explicit DRAM Precharge commands sent on this channel as a result of a DRAM page miss. This does not include the implicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include Precharge commands sent as a result of a page close counter expiration.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Pre-charge for reads",
+ "EventCode": "0x2",
+ "EventName": "UNC_M_PRE_COUNT.RD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of explicit DRAM Precharge commands issued on a per channel basis due to a read, so as to close the previous DRAM page, before opening the requested page.",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Pre-charge for writes",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.BYP",
+ "BriefDescription": "Read CAS issued with HIGH priority",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with LOW priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.LOW",
"PerPkg": "1",
@@ -543,7 +517,6 @@
},
{
"BriefDescription": "Read CAS issued with MEDIUM priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.MED",
"PerPkg": "1",
@@ -551,26 +524,23 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Read CAS issued with HIGH priority",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
"EventCode": "0xA0",
- "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
+ "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
+ "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK0",
"PerPkg": "1",
@@ -578,7 +548,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK1",
"PerPkg": "1",
@@ -586,143 +555,119 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0x3",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0x5",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
"PerPkg": "1",
- "UMask": "0x6",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
- "PerPkg": "1",
- "UMask": "0x7",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
"PerPkg": "1",
- "UMask": "0x9",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
"PerPkg": "1",
@@ -731,7 +676,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
"PerPkg": "1",
@@ -740,7 +684,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
"PerPkg": "1",
@@ -749,16 +692,22 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK0",
"PerPkg": "1",
@@ -766,16 +715,62 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
+ "PerPkg": "1",
+ "UMask": "0xa",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
+ "PerPkg": "1",
+ "UMask": "0xb",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
+ "PerPkg": "1",
+ "UMask": "0xc",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
+ "PerPkg": "1",
+ "UMask": "0xd",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
+ "PerPkg": "1",
+ "UMask": "0xe",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
+ "PerPkg": "1",
+ "UMask": "0xf",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK2",
"PerPkg": "1",
@@ -784,7 +779,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK3",
"PerPkg": "1",
@@ -793,7 +787,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK4",
"PerPkg": "1",
@@ -802,7 +795,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK5",
"PerPkg": "1",
@@ -811,7 +803,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK6",
"PerPkg": "1",
@@ -820,7 +811,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK7",
"PerPkg": "1",
@@ -829,7 +819,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK8",
"PerPkg": "1",
@@ -838,7 +827,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK9",
"PerPkg": "1",
@@ -846,124 +834,110 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0x11",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0x12",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x13",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
+ "BriefDescription": "RD_CAS Access to Rank 2; All Banks",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
"PerPkg": "1",
- "UMask": "0xF",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 1",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 10",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK10",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 11",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK11",
"PerPkg": "1",
- "UMask": "0x12",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 12",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK12",
"PerPkg": "1",
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{
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- "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
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+ "EventName": "UNC_M_RD_CAS_RANK2.BANK13",
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+ "UMask": "0xd",
"Unit": "iMC"
},
{
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- "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
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+ "UMask": "0xe",
"Unit": "iMC"
},
{
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- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 15",
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+ "EventName": "UNC_M_RD_CAS_RANK2.BANK15",
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+ "UMask": "0xf",
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},
{
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"EventName": "UNC_M_RD_CAS_RANK2.BANK2",
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@@ -972,7 +946,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK2.BANK3",
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@@ -981,7 +954,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK2.BANK4",
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@@ -990,7 +962,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK2.BANK5",
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@@ -999,7 +970,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK2.BANK6",
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@@ -1008,7 +978,6 @@
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{
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"EventName": "UNC_M_RD_CAS_RANK2.BANK7",
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@@ -1017,7 +986,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK2.BANK8",
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@@ -1026,7 +994,6 @@
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"EventName": "UNC_M_RD_CAS_RANK2.BANK9",
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@@ -1034,124 +1001,110 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 10",
- "Counter": "0,1,2,3",
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- "EventName": "UNC_M_RD_CAS_RANK2.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANKG0",
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+ "UMask": "0x11",
"Unit": "iMC"
},
{
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- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)",
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- "EventName": "UNC_M_RD_CAS_RANK2.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANKG1",
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+ "UMask": "0x12",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 12",
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+ "EventName": "UNC_M_RD_CAS_RANK2.BANKG2",
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+ "UMask": "0x13",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 13",
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+ "EventName": "UNC_M_RD_CAS_RANK2.BANKG3",
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},
{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK14",
+ "BriefDescription": "RD_CAS Access to Rank 3; All Banks",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS",
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},
{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK15",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 0",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK0",
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"Unit": "iMC"
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{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 1",
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+ "EventName": "UNC_M_RD_CAS_RANK3.BANK1",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANKG0",
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+ "EventName": "UNC_M_RD_CAS_RANK3.BANK10",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANKG1",
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+ "EventName": "UNC_M_RD_CAS_RANK3.BANK11",
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{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANKG2",
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+ "EventName": "UNC_M_RD_CAS_RANK3.BANK12",
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{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANKG3",
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+ "EventCode": "0xB3",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK13",
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- "UMask": "0x14",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
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- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 14",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK14",
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+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 15",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK15",
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- "UMask": "0x1",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 2",
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"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK2",
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@@ -1160,7 +1113,6 @@
},
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"EventName": "UNC_M_RD_CAS_RANK3.BANK3",
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@@ -1169,7 +1121,6 @@
},
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"EventName": "UNC_M_RD_CAS_RANK3.BANK4",
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@@ -1178,7 +1129,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK3.BANK5",
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@@ -1187,7 +1137,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK3.BANK6",
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@@ -1196,7 +1145,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK3.BANK7",
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@@ -1205,7 +1153,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK3.BANK8",
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@@ -1214,7 +1161,6 @@
},
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"EventName": "UNC_M_RD_CAS_RANK3.BANK9",
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@@ -1222,124 +1168,110 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 10",
- "Counter": "0,1,2,3",
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- "EventName": "UNC_M_RD_CAS_RANK3.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANKG0",
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- "UMask": "0xA",
+ "UMask": "0x11",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)",
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- "EventName": "UNC_M_RD_CAS_RANK3.BANK11",
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- "UMask": "0xB",
+ "UMask": "0x12",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)",
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- "EventName": "UNC_M_RD_CAS_RANK3.BANK12",
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+ "UMask": "0x13",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 13",
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- "EventName": "UNC_M_RD_CAS_RANK3.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANKG3",
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"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK14",
+ "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
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},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 15",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK15",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
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},
{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS",
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},
{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANKG0",
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+ "EventCode": "0xB4",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
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{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANKG1",
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+ "EventCode": "0xB4",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
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- "UMask": "0x12",
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},
{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANKG2",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
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{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANKG3",
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+ "EventCode": "0xB4",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
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+ "UMask": "0xd",
"Unit": "iMC"
},
{
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- "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
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+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
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- "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
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- "UMask": "0x1",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
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"EventName": "UNC_M_RD_CAS_RANK4.BANK2",
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@@ -1348,7 +1280,6 @@
},
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"EventName": "UNC_M_RD_CAS_RANK4.BANK3",
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@@ -1357,7 +1288,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK4.BANK4",
"PerPkg": "1",
@@ -1366,7 +1296,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK4.BANK5",
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@@ -1375,7 +1304,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK4.BANK6",
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@@ -1384,7 +1312,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK4.BANK7",
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@@ -1393,7 +1320,6 @@
},
{
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- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK8",
"PerPkg": "1",
@@ -1402,7 +1328,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK4.BANK9",
"PerPkg": "1",
@@ -1410,124 +1335,110 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
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- "UMask": "0xA",
+ "UMask": "0x11",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
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- "UMask": "0xB",
+ "UMask": "0x12",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
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- "UMask": "0xC",
+ "UMask": "0x13",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
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- "UMask": "0xD",
+ "UMask": "0x14",
"Unit": "iMC"
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{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
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- "Counter": "0,1,2,3",
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- "EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
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- "EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
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"Unit": "iMC"
},
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"Unit": "iMC"
},
{
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@@ -1554,7 +1463,6 @@
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@@ -1572,7 +1479,6 @@
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@@ -1590,7 +1495,6 @@
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"EventName": "UNC_M_RD_CAS_RANK5.BANK9",
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"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
- "Counter": "0,1,2,3",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
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+ "UMask": "0x11",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
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+ "UMask": "0x12",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
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+ "UMask": "0x13",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
- "Counter": "0,1,2,3",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
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+ "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
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{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
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+ "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
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{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
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+ "EventCode": "0xB6",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
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+ "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
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+ "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
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+ "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
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+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
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+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
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- "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
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+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
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- "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
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+ "UMask": "0xf",
"Unit": "iMC"
},
{
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"EventName": "UNC_M_RD_CAS_RANK6.BANK2",
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"EventName": "UNC_M_RD_CAS_RANK6.BANK7",
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"EventName": "UNC_M_RD_CAS_RANK6.BANK8",
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"EventName": "UNC_M_RD_CAS_RANK6.BANK9",
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"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
- "Counter": "0,1,2,3",
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"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
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+ "UMask": "0x11",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
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- "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
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- "UMask": "0xB",
+ "UMask": "0x12",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
- "Counter": "0,1,2,3",
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- "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
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+ "UMask": "0x13",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
- "Counter": "0,1,2,3",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
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+ "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
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{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
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- "UMask": "0x12",
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{
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- "Counter": "0,1,2,3",
- "EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
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+ "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
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- "UMask": "0x13",
+ "UMask": "0xc",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
+ },
+ {
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
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- "UMask": "0x14",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
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- "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
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+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
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+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
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- "UMask": "0x1",
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"Unit": "iMC"
},
{
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@@ -1912,7 +1781,6 @@
},
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},
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"EventName": "UNC_M_RD_CAS_RANK7.BANK4",
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@@ -1930,7 +1797,6 @@
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@@ -1939,7 +1805,6 @@
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"EventName": "UNC_M_RD_CAS_RANK7.BANK6",
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@@ -1948,7 +1813,6 @@
},
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@@ -1957,7 +1821,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK8",
"PerPkg": "1",
@@ -1966,79 +1829,14 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
- {
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
- "PerPkg": "1",
- "UMask": "0xA",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
- "PerPkg": "1",
- "UMask": "0xB",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
- "PerPkg": "1",
- "UMask": "0xC",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
- "PerPkg": "1",
- "UMask": "0xD",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
- "PerPkg": "1",
- "UMask": "0xE",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "iMC"
- },
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
"PerPkg": "1",
@@ -2047,7 +1845,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
"PerPkg": "1",
@@ -2056,7 +1853,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
"PerPkg": "1",
@@ -2065,7 +1861,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
"PerPkg": "1",
@@ -2074,23 +1869,38 @@
},
{
"BriefDescription": "Read Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M_RPQ_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x80",
+ "EventName": "UNC_M_RPQ_OCCUPANCY",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"PerPkg": "1",
@@ -2099,7 +1909,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.STARVE",
"PerPkg": "1",
@@ -2108,7 +1917,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"PerPkg": "1",
@@ -2117,199 +1925,196 @@
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x81",
+ "EventName": "UNC_M_WPQ_OCCUPANCY",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Not getting the requested Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_M_WRONG_MM",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
"PerPkg": "1",
- "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0x3",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
"PerPkg": "1",
- "UMask": "0x5",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0x6",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
"PerPkg": "1",
- "UMask": "0x7",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
"PerPkg": "1",
- "UMask": "0x9",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
"PerPkg": "1",
@@ -2318,7 +2123,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
"PerPkg": "1",
@@ -2327,7 +2131,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
"PerPkg": "1",
@@ -2336,7 +2139,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
"PerPkg": "1",
@@ -2344,160 +2146,142 @@
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
"PerPkg": "1",
- "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
"PerPkg": "1",
- "UMask": "0x3",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
"PerPkg": "1",
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{
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{
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"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0x12",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x13",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+ "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
"PerPkg": "1",
- "UMask": "0xF",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0x12",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
"PerPkg": "1",
- "UMask": "0x13",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0x14",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
"PerPkg": "1",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK2",
"PerPkg": "1",
@@ -3499,7 +3228,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK3",
"PerPkg": "1",
@@ -3508,7 +3236,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK4",
"PerPkg": "1",
@@ -3517,7 +3244,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK5",
"PerPkg": "1",
@@ -3526,7 +3252,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK6",
"PerPkg": "1",
@@ -3535,7 +3260,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK7",
"PerPkg": "1",
@@ -3544,7 +3268,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK8",
"PerPkg": "1",
@@ -3553,79 +3276,14 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
- "PerPkg": "1",
- "UMask": "0xA",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
- "PerPkg": "1",
- "UMask": "0xB",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
- "PerPkg": "1",
- "UMask": "0xC",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
- "PerPkg": "1",
- "UMask": "0xD",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
- "PerPkg": "1",
- "UMask": "0xE",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "iMC"
- },
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
"PerPkg": "1",
@@ -3634,7 +3292,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
"PerPkg": "1",
@@ -3643,7 +3300,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
"PerPkg": "1",
@@ -3652,19 +3308,10 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
- },
- {
- "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
- "Counter": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_M_CLOCKTICKS_F",
- "PerPkg": "1",
- "Unit": "iMC"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
index 0d106fe7aae3..3cf8b7c458ba 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
@@ -1,8248 +1,12229 @@
[
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventName": "UNC_C_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
- "PerPkg": "1",
- "UMask": "0x42",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+ "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
+ "EventCode": "0x83",
+ "EventName": "LLC_MISSES.PCIE_READ",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "MetricName": "LLC_MISSES.PCIE_READ",
"PerPkg": "1",
- "UMask": "0x82",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+ "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
+ "EventCode": "0x83",
+ "EventName": "LLC_MISSES.PCIE_WRITE",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "MetricName": "LLC_MISSES.PCIE_WRITE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.HA",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.TOR",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
- "Counter": "0,1,2,3",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Number of times that an RFO hit in S state",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RFO_HIT_S",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "read requests from home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "write requests from home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x0C",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "read requests from local home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "write requests from local home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "RspIFwd Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RspSFwd Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IRQ",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x31",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IRQ",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x31",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.REM_ALL",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x30",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0xA5",
- "EventName": "UNC_C_FAST_ASSERTED",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; IRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy; IRQ",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x14",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x24",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Hits from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x14",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Misses from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x24",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; All from Local iA",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x31",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Hits from Local iA",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; All from Local iA",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x31",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Hits from Local iA",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Misses from Local iA",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "FaST wire asserted; Horizontal",
- "Counter": "0,1,2,3",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_FAST_ASSERTED.HORZ",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the uncore caching & home agent (CHA)",
- "Counter": "0,1,2,3",
- "EventName": "UNC_CHA_CLOCKTICKS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
- "Counter": "0,1,2,3",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Read requests from a remote socket",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
+ "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RspI Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
+ "BriefDescription": "CHA to iMC Bypass; Not Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Rsp*WB Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB",
+ "BriefDescription": "CHA to iMC Bypass; Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RspCnflct* Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
+ "BriefDescription": "Clockticks of the uncore caching & home agent (CHA)",
+ "EventName": "UNC_CHA_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts clockticks of the clock controlling the uncore caching and home agent (CHA).",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for M-state entries",
- "Counter": "0,1,2,3",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xC0",
+ "EventName": "UNC_CHA_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for E-state entries",
- "Counter": "0,1,2,3",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
+ "BriefDescription": "Core PMA Events; C1 State",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.C1_STATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for S-state entries",
- "Counter": "0,1,2,3",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
+ "BriefDescription": "Core PMA Events; C1 Transition",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
+ "BriefDescription": "Core PMA Events; C6 State",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.C6_STATE",
"PerPkg": "1",
- "UMask": "0x30",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized; Lines in M state",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
+ "BriefDescription": "Core PMA Events; C6 Transition",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized; Lines in E state",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
+ "BriefDescription": "Core PMA Events; GV",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.GV",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized; Lines in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
+ "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xe2",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized; Lines in F State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F",
+ "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xe1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
- "Filter": "config1=0x40433",
+ "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xe4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
- "Filter": "config1=0x40233",
+ "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x42",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "Core Cross Snoops Issued; Single Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x41",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
- "Filter": "config1=0x4b433",
+ "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
- "Filter": "config1=0x4b233",
+ "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x82",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO",
- "Filter": "config1=0x4b033",
+ "BriefDescription": "Core Cross Snoops Issued; Single Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x81",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
- "Filter": "config1=0x40433",
+ "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x84",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
- "Filter": "config1=0x40233",
+ "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x22",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "Core Cross Snoops Issued; Single External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
- "Filter": "config1=0x4b433",
+ "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
- "Filter": "config1=0x4b233",
+ "BriefDescription": "Counter 0 Occupancy",
+ "EventCode": "0x1F",
+ "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO",
- "Filter": "config1=0x4b033",
+ "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
- "Filter": "config1=0x40433",
+ "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
- "Filter": "config1=0x40233",
+ "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.HA",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.TOR",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
- "Filter": "config1=0x4b433",
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+ "EventCode": "0xAE",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
- "Filter": "config1=0x4b233",
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+ "EventCode": "0xAE",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
- "Filter": "config1=0x4b033",
+ "BriefDescription": "FaST wire asserted; Horizontal",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_FAST_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
- "Filter": "config1=0x40433",
+ "BriefDescription": "FaST wire asserted; Vertical",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_FAST_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
- "Filter": "config1=0x40233",
+ "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
- "Filter": "config1=0x4b433",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
- "Filter": "config1=0x4b233",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
- "Filter": "config1=0x4b033",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
+ "EventCode": "0x5E",
+ "EventName": "UNC_CHA_HITME_LOOKUP.READ",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the IIO Traffic Controller",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_IIO_CLOCKTICKS",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "EventCode": "0x5E",
+ "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
"PerPkg": "1",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0",
- "FCMask": "0x7",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x1",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1",
- "FCMask": "0x7",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x1",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2",
- "FCMask": "0x7",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x1",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3",
- "FCMask": "0x7",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x1",
- "Unit": "IIO"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0",
- "FCMask": "0x7",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x4",
- "Unit": "IIO"
+ "PublicDescription": "Received RspFwdI* for a local request, but converted HitME$ to SF entry",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1",
- "FCMask": "0x7",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x4",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2",
- "FCMask": "0x7",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x4",
- "Unit": "IIO"
+ "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E received for a remote request",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3",
- "FCMask": "0x7",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
"PerPkg": "1",
- "PortMask": "0x8",
"UMask": "0x4",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal IV Ring in Use; Left",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Horizontal IV Ring in Use; Right",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "HA to iMC Reads Issued; ISOCH",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
- },
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "LLC_MISSES.PCIE_WRITE",
- "FCMask": "0x07",
- "Filter": "ch_mask=0x1f",
- "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "MetricName": "LLC_MISSES.PCIE_WRITE",
+ "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
"PerPkg": "1",
- "PortMask": "0x01",
- "ScaleUnit": "4Bytes",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations",
+ "EventCode": "0x62",
+ "EventName": "UNC_CHA_IODC_ALLOC.INVITOM",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full",
+ "EventCode": "0x62",
+ "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate",
+ "EventCode": "0x62",
+ "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.ALL",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "LLC_MISSES.PCIE_READ",
- "FCMask": "0x07",
- "Filter": "ch_mask=0x1f",
- "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "MetricName": "LLC_MISSES.PCIE_READ",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
"PerPkg": "1",
- "PortMask": "0x01",
- "ScaleUnit": "4Bytes",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Moved to Cbo section",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ANY",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions",
+ "UMask": "0x3",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Local",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
+ "UMask": "0x31",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Remote",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
+ "UMask": "0x91",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+ "UMask": "0x9",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITE",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.",
+ "UMask": "0x5",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - All Lines",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2f",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - Lines in E State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x22",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - Lines in F State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x28",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - Lines in M State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - All Lines",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8f",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - Lines in E State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x82",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - Lines in F State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x88",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - Lines in M State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x81",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x84",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Lines in E state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Lines in F State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Lines in M state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Cbo Misc; CV0 Prefetch Miss",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Cbo Misc; CV0 Prefetch Victim",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Number of times that an RFO hit in S state.",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RFO_HIT_S",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.WC_ALIASING",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
- "FCMask": "0x4",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
- "FCMask": "0x4",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
- "FCMask": "0x4",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
- "FCMask": "0x4",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
- "FCMask": "0x04",
+ "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
- "FCMask": "0x04",
+ "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
- "FCMask": "0x04",
+ "BriefDescription": "Read requests",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .",
+ "UMask": "0x3",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
- "FCMask": "0x04",
+ "BriefDescription": "Read requests from a unit on this socket",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
- "FCMask": "0x4",
+ "BriefDescription": "Read requests from a remote socket",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
"PerPkg": "1",
- "PortMask": "0x0f",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
- "FCMask": "0x04",
+ "BriefDescription": "Write requests",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES",
"PerPkg": "1",
- "UMask": "0x0f",
- "Unit": "IIO"
+ "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0xc",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Total IRP occupancy of inbound read and write requests",
- "Counter": "0,1",
- "EventCode": "0xF",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+ "BriefDescription": "Write Requests from a unit on this socket",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
"UMask": "0x4",
- "Unit": "IRP"
+ "Unit": "CHA"
},
{
- "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.RFO",
+ "BriefDescription": "Read and Write Requests; Writes Remote",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).",
"UMask": "0x8",
- "Unit": "IRP"
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
- "Counter": "0,1",
- "EventCode": "0x18",
- "EventName": "UNC_I_FAF_INSERTS",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Occupancy of the IRP FAF queue",
- "Counter": "0,1",
- "EventCode": "0x19",
- "EventName": "UNC_I_FAF_OCCUPANCY",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound write (fast path) requests received by the IRP",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x8",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_UPI_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Response packets that go direct to core",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_UPI_L1_POWER_CYCLES",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x25",
- "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UPI LL"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.NULL",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FLITs that bypassed the TxL Buffer",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_UPI_TxL_BYPASSED",
+ "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent; Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.DATA",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.NULL",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Protocol header and credit FLITs received from any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x97",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Protocol header and credit FLITs transmitted across any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x97",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Idle FLITs transmitted",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.IDLE",
+ "BriefDescription": "Ingress (from CMS) Allocations; IPQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x47",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Null FLITs transmitted from any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
+ "BriefDescription": "Ingress (from CMS) Allocations; IRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x27",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Null FLITs received from any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
+ "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x27",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid data FLITs received from any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
+ "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid data FLITs transmitted via any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+ "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UPI_DATA_BANDWIDTH_TX",
+ "BriefDescription": "Ingress (from CMS) Allocations; RRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
"PerPkg": "1",
- "ScaleUnit": "7.11E-06Bytes",
- "UMask": "0xf",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Response packets that go direct to Intel UPI",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U",
+ "BriefDescription": "Ingress (from CMS) Allocations; WBQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0",
"EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
"UMask": "0x2",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
+ "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to core transaction were overridden",
- "Counter": "0,1,2,3",
- "EventCode": "0x25",
- "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+ "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+ "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+ "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+ "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+ "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+ "BriefDescription": "Ingress Probe Queue Rejects; ANY0",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
"PerPkg": "1",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from I to S",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
+ "BriefDescription": "Ingress Probe Queue Rejects; HA",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
"PerPkg": "1",
"UMask": "0x2",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from I to A",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
+ "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from S to I",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
+ "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from S to A",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
+ "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from A to I",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
+ "BriefDescription": "Ingress Probe Queue Rejects; SF Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from A to S",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
+ "BriefDescription": "Ingress Probe Queue Rejects; Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.NORMAL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Reads to iMC issued",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ALL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Partial Non-Isochronous writes to the iMC",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Writes to iMC issued",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.ALL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.NI",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Prefetch requests that got turn into a demand request",
- "Counter": "0,1,2,3",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inserts into the Memory Controller Prefetch Queue",
- "Counter": "0,1,2,3",
- "EventCode": "0x57",
- "EventName": "UNC_M2M_PREFCAM_INSERTS",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M2M_RxC_AD_INSERTS",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_M2M_RxC_BL_INSERTS",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_M2M_TxC_AD_INSERTS",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0xA",
- "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Occupancy; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles when direct to Intel UPI was disabled",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "ISMQ Rejects; AD REQ on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages sent direct to the Intel UPI",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
+ "BriefDescription": "ISMQ Rejects; AD RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+ "BriefDescription": "ISMQ Rejects; Non UPI AK Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit",
- "Counter": "0,1,2",
- "EventCode": "0x29",
- "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+ "BriefDescription": "ISMQ Rejects; BL NCB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+ "BriefDescription": "ISMQ Rejects; BL NCS on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+ "BriefDescription": "ISMQ Rejects; BL RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+ "BriefDescription": "ISMQ Rejects; BL WB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Single External Snoops",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+ "BriefDescription": "ISMQ Rejects; Non UPI IV Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Single Core Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+ "BriefDescription": "ISMQ Retries; AD REQ on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Single Eviction",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+ "BriefDescription": "ISMQ Retries; AD RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x81",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+ "BriefDescription": "ISMQ Retries; Non UPI AK Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0xE1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+ "BriefDescription": "ISMQ Retries; BL NCB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x22",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+ "BriefDescription": "ISMQ Retries; BL NCS on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0xE2",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE",
+ "BriefDescription": "ISMQ Retries; BL RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x24",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE",
- "PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE",
+ "BriefDescription": "ISMQ Retries; BL WB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x84",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE",
+ "BriefDescription": "ISMQ Retries; Non UPI IV Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0xE4",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x1F",
- "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+ "BriefDescription": "ISMQ Rejects; ANY0",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*",
- "Counter": "0,1,2,3",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+ "BriefDescription": "ISMQ Rejects; HA",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
+ "BriefDescription": "ISMQ Retries; ANY0",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
- "Counter": "0,1,2,3",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+ "BriefDescription": "ISMQ Retries; HA",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
- "Counter": "0,1,2,3",
- "EventCode": "0x5E",
- "EventName": "UNC_CHA_HITME_LOOKUP.READ",
+ "BriefDescription": "Ingress (from CMS) Occupancy; IPQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
- "Counter": "0,1,2,3",
- "EventCode": "0x5E",
- "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
+ "BriefDescription": "Ingress (from CMS) Occupancy; IRQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+ "BriefDescription": "Ingress (from CMS) Occupancy; RRQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+ "BriefDescription": "Ingress (from CMS) Occupancy; WBQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
+ "BriefDescription": "Other Retries; AD REQ on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+ "BriefDescription": "Other Retries; AD RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+ "BriefDescription": "Other Retries; Non UPI AK Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
+ "BriefDescription": "Other Retries; BL NCB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
+ "BriefDescription": "Other Retries; BL NCS on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
+ "BriefDescription": "Other Retries; BL RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "HA to iMC Reads Issued; ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+ "BriefDescription": "Other Retries; BL WB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+ "BriefDescription": "Other Retries; Non UPI IV Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+ "BriefDescription": "Other Retries; Allow Snoop",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+ "BriefDescription": "Other Retries; ANY0",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
+ "BriefDescription": "Other Retries; HA",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+ "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x62",
- "EventName": "UNC_CHA_IODC_ALLOC.INVITOM",
+ "BriefDescription": "Other Retries; LLC Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full",
- "Counter": "0,1,2,3",
- "EventCode": "0x62",
- "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL",
+ "BriefDescription": "Other Retries; PhyAddr Match",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate",
- "Counter": "0,1,2,3",
- "EventCode": "0x62",
- "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED",
+ "BriefDescription": "Other Retries; SF Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE",
+ "BriefDescription": "Other Retries; Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.ALL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x5",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.ANY",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.LOCAL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x31",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.REMOTE",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x91",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.LOCAL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x2f",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.REMOTE",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc; Write Combining Aliasing",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.WC_ALIASING",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc; CV0 Prefetch Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc; CV0 Prefetch Miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast",
- "Counter": "0,1,2,3",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
+ "BriefDescription": "Request Queue Retries; AD REQ on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
+ "BriefDescription": "Request Queue Retries; AD RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
+ "BriefDescription": "Request Queue Retries; Non UPI AK Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
+ "BriefDescription": "Request Queue Retries; BL NCB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
+ "BriefDescription": "Request Queue Retries; BL NCS on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "write requests from remote home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
+ "BriefDescription": "Request Queue Retries; BL RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.",
+ "BriefDescription": "Request Queue Retries; BL WB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
+ "BriefDescription": "Request Queue Retries; Non UPI IV Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
+ "BriefDescription": "Request Queue Retries; Allow Snoop",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC",
+ "BriefDescription": "Request Queue Retries; ANY0",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.BCST_REM",
+ "BriefDescription": "Request Queue Retries; HA",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC",
+ "BriefDescription": "Request Queue Retries; LLC Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM",
+ "BriefDescription": "Request Queue Retries; PhyAddr Match",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspS",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
+ "BriefDescription": "Request Queue Retries; SF Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+ "BriefDescription": "Request Queue Retries; Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received; RspFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
+ "BriefDescription": "RRQ Rejects; AD REQ on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI",
+ "BriefDescription": "RRQ Rejects; AD RSP on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS",
+ "BriefDescription": "RRQ Rejects; Non UPI AK Request",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD",
+ "BriefDescription": "RRQ Rejects; BL NCB on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD",
+ "BriefDescription": "RRQ Rejects; BL NCS on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB",
+ "BriefDescription": "RRQ Rejects; BL RSP on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB",
+ "BriefDescription": "RRQ Rejects; BL WB on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT",
+ "BriefDescription": "RRQ Rejects; Non UPI IV Request",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD",
+ "BriefDescription": "RRQ Rejects; Allow Snoop",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.EVICT",
+ "BriefDescription": "RRQ Rejects; ANY0",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.PRQ",
+ "BriefDescription": "RRQ Rejects; HA",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IPQ",
+ "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.HIT",
+ "BriefDescription": "RRQ Rejects; LLC Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS",
+ "BriefDescription": "RRQ Rejects; PhyAddr Match",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.EVICT",
+ "BriefDescription": "RRQ Rejects; SF Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.PRQ",
+ "BriefDescription": "RRQ Rejects; Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IPQ",
+ "BriefDescription": "WBQ Rejects; AD REQ on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.HIT",
+ "BriefDescription": "WBQ Rejects; AD RSP on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS",
+ "BriefDescription": "WBQ Rejects; Non UPI AK Request",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI; Pushed to LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+ "BriefDescription": "WBQ Rejects; BL NCB on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI; Pushed to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+ "BriefDescription": "WBQ Rejects; BL NCS on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
+ "BriefDescription": "WBQ Rejects; BL RSP on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
+ "BriefDescription": "WBQ Rejects; BL WB on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
+ "BriefDescription": "WBQ Rejects; Non UPI IV Request",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
+ "BriefDescription": "WBQ Rejects; Allow Snoop",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
+ "BriefDescription": "WBQ Rejects; ANY0",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
+ "BriefDescription": "WBQ Rejects; HA",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOC_IO",
+ "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x34",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOC_IA",
+ "BriefDescription": "WBQ Rejects; LLC Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x31",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
+ "BriefDescription": "WBQ Rejects; PhyAddr Match",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x37",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO",
+ "BriefDescription": "WBQ Rejects; SF Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x34",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA",
+ "BriefDescription": "WBQ Rejects; Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x31",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x37",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; C1 State",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.C1_STATE",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; C1 Transition",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; C6 State",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.C6_STATE",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; C6 Transition",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; GV",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.GV",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Snoops Sent; All",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of snoops issued by the HA.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Snoops Sent; Directed snoops for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "RspCnflct* Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Snoop Responses Received; RspFwd",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "RspI Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
"PerPkg": "1",
+ "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
"UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "RspIFwd Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Snoop Responses Received : RspS",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "RspSFwd Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
+ "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
"UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Rsp*WB Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
+ "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
+ "BriefDescription": "Snoop Responses Received Local; RspFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
+ "BriefDescription": "Snoop Responses Received Local; RspI",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
+ "BriefDescription": "Snoop Responses Received Local; RspIFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
+ "BriefDescription": "Snoop Responses Received Local; RspS",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
+ "BriefDescription": "Snoop Responses Received Local; RspSFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_H_CLOCK",
+ "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0xAE",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
- "Counter": "0,1,2,3",
- "EventCode": "0xAE",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Left",
- "Counter": "0,1,2,3",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Right",
- "Counter": "0,1,2,3",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "TOR Inserts; Hits from Local",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x15",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "TOR Inserts; All from Local iA and IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests",
+ "UMask": "0x35",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "TOR Inserts; Misses from Local",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x25",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "TOR Inserts; SF/LLC Evictions",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "TOR Inserts; Hit (Not a Miss)",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.HIT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "TOR Inserts; All from Local iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores",
+ "UMask": "0x31",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "TOR Inserts; Hits from Local iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+ "Filter": "config1=0x40233",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0xA4",
- "EventName": "UNC_C_RING_SRC_THRTL",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
+ "Filter": "config1=0x40433",
"PerPkg": "1",
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+ "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
+ "Filter": "config1=0x4b233",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; IPQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
+ "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
+ "Filter": "config1=0x4b433",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO",
+ "Filter": "config1=0x4b033",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; RRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; WBQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+ "Filter": "config1=0x40233",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
+ "Filter": "config1=0x40433",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
+ "Filter": "config1=0x4b233",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
+ "Filter": "config1=0x4b433",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO",
+ "Filter": "config1=0x4b033",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "TOR Inserts; All from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic",
+ "UMask": "0x34",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x23",
- "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0",
+ "BriefDescription": "TOR Inserts; Hits from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x14",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
+ "BriefDescription": "TOR Inserts; Misses from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "TOR Inserts; ItoM misses from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+ "Filter": "config1=0x49033",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership.",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; SF Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "TOR Inserts; RdCur misses from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR",
+ "Filter": "config1=0x43C33",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state.",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+ "BriefDescription": "TOR Inserts; RFO misses from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify.",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "TOR Inserts; IPQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x18",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x28",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "TOR Inserts; IRQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x37",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "TOR Inserts; Miss",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MISS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "TOR Inserts; PRQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x30",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x19",
- "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x50",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x60",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x90",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0xa0",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+ "BriefDescription": "TOR Occupancy; All from Local",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests",
+ "UMask": "0x37",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "TOR Occupancy; Hits from Local",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x17",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "TOR Occupancy; Misses from Local",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x27",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "TOR Occupancy; SF/LLC Evictions",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "TOR Occupancy; Hit (Not a Miss)",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "TOR Occupancy; All from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally initiated requests from iA Cores",
+ "UMask": "0x31",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "TOR Occupancy; Hits from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "Filter": "config1=0x40233",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+ "Filter": "config1=0x40433",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; AD REQ on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
+ "Filter": "config1=0x4b233",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; AD RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
+ "Filter": "config1=0x4b433",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; BL RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
+ "Filter": "config1=0x4b033",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; BL WB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; BL NCB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "TOR Occupancy; Misses from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+ "Filter": "config1=0x40233",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x25",
- "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+ "Filter": "config1=0x40433",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
+ "Filter": "config1=0x4b233",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x2D",
- "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
+ "Filter": "config1=0x4b433",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
+ "Filter": "config1=0x4b033",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy; IPQ",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy; RRQ",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
+ "BriefDescription": "TOR Occupancy; All from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally generated IO traffic",
+ "UMask": "0x34",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy; WBQ",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
+ "BriefDescription": "TOR Occupancy; Hits from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x14",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; AD REQ on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "TOR Occupancy; Misses from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; AD RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+ "Filter": "config1=0x49033",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership.",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; BL RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR",
+ "Filter": "config1=0x43C33",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; BL WB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "BriefDescription": "TOR Occupancy; RFO misses from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify.",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; BL NCB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "TOR Occupancy; IPQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x18",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x2F",
- "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x28",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+ "BriefDescription": "TOR Occupancy; IRQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; LLC Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x37",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; SF Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+ "BriefDescription": "TOR Occupancy; Miss",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+ "BriefDescription": "TOR Occupancy; PRQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; Allow Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+ "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x21",
- "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+ "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; AD REQ on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; AD RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; BL RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; BL WB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; BL NCB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x2B",
- "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; LLC Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; SF Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; Allow Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x27",
- "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; LLC Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; SF Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x29",
- "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; LLC Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; SF Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "CMS Vertical ADS Used; IV",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC",
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC",
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC",
+ "BriefDescription": "CMS Vert Egress Allocations; IV",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC",
+ "BriefDescription": "CMS Vertical Egress NACKs; IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "CMS Vert Egress Occupancy; IV",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "Vertical IV Ring in Use; Down",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
+ "BriefDescription": "Vertical IV Ring in Use; Up",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
+ "BriefDescription": "WbPushMtoI; Pushed to LLC",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
+ "BriefDescription": "WbPushMtoI; Pushed to Memory",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E",
+ "UMask": "0xe4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "Core Cross Snoop Responses",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M",
+ "UMask": "0xf0",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E",
+ "UMask": "0xe2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M",
+ "UMask": "0xe8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E",
+ "UMask": "0xe1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M",
+ "UMask": "0x50",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E",
+ "UMask": "0x42",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M",
+ "UMask": "0x48",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E",
+ "UMask": "0x41",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E",
+ "UMask": "0x84",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M",
+ "UMask": "0x90",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E",
+ "UMask": "0x82",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M",
+ "UMask": "0x88",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E",
+ "UMask": "0x81",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M",
+ "UMask": "0x30",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E",
+ "UMask": "0x22",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
+ "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M",
+ "UMask": "0x28",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS",
+ "Deprecated": "1",
+ "EventName": "UNC_C_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ",
+ "Deprecated": "1",
+ "EventCode": "0xA5",
+ "EventName": "UNC_C_FAST_ASSERTED",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.ANY",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x3",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.LOCAL",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x31",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x91",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x9",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x5",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
"Deprecated": "1",
- "EventCode": "0x9E",
- "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.LOCAL",
+ "PerPkg": "1",
+ "UMask": "0x2f",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL",
+ "Deprecated": "1",
+ "EventCode": "0xA4",
+ "EventName": "UNC_C_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT",
"Deprecated": "1",
- "EventCode": "0x92",
- "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.EVICT",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.HIT",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x18",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x28",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x31",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS",
"Deprecated": "1",
- "EventCode": "0x93",
- "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x37",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.LOC_IA",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x31",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.LOC_IO",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x34",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.MISS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.PRQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x14",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS",
"Deprecated": "1",
- "EventCode": "0x91",
- "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.REM_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x30",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x50",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x60",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x90",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0xa0",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.EVICT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.IV",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.HIT",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x18",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x28",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x31",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x90",
- "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x37",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x31",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x34",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.PRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x14",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.IV",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Down",
- "Counter": "0,1,2,3",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x41",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x81",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0xE1",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x22",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x42",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x82",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0xE2",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x24",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x84",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0xE4",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x28",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x48",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x88",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0xE8",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x30",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x50",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x90",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0xF0",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x18",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x28",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x50",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x60",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x90",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0xA0",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x14",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x24",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x18",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x28",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; All from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+ "Deprecated": "1",
+ "EventCode": "0x57",
+ "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE",
"PerPkg": "1",
- "UMask": "0x34",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; All from Local iA and IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+ "Deprecated": "1",
+ "EventCode": "0x57",
+ "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x35",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Hits from Local",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+ "Deprecated": "1",
+ "EventCode": "0x57",
+ "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN",
"PerPkg": "1",
- "UMask": "0x15",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Misses from Local",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS",
+ "Deprecated": "1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_H_CLOCK",
"PerPkg": "1",
- "UMask": "0x25",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; All from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE",
+ "Deprecated": "1",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.C1_STATE",
"PerPkg": "1",
- "UMask": "0x34",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Hits from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION",
+ "Deprecated": "1",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.C1_TRANSITION",
"PerPkg": "1",
- "UMask": "0x14",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Misses from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE",
+ "Deprecated": "1",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.C6_STATE",
"PerPkg": "1",
- "UMask": "0x24",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Hits from Local",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION",
+ "Deprecated": "1",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.C6_TRANSITION",
"PerPkg": "1",
- "UMask": "0x17",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Misses from Local",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV",
+ "Deprecated": "1",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.GV",
"PerPkg": "1",
- "UMask": "0x27",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.ANY_GTONE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0xe2",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.ANY_ONE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0xe1",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.ANY_REMOTE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0xe4",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.CORE_GTONE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x42",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.CORE_ONE",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x41",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.CORE_REMOTE",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EVICT_GTONE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x82",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EVICT_ONE",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x81",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x84",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EXT_GTONE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x22",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EXT_ONE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EXT_REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY",
+ "Deprecated": "1",
+ "EventCode": "0x1F",
+ "EventName": "UNC_H_COUNTER0_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB",
- "PerPkg": "1",
- "UMask": "0x20",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_DIR_LOOKUP.NO_SNP",
+ "PerPkg": "1",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
+ "Deprecated": "1",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_DIR_LOOKUP.SNP",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
+ "Deprecated": "1",
+ "EventCode": "0x54",
+ "EventName": "UNC_H_DIR_UPDATE.HA",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
+ "Deprecated": "1",
+ "EventCode": "0x54",
+ "EventName": "UNC_H_DIR_UPDATE.TOR",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Deprecated": "1",
+ "EventCode": "0xAE",
+ "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Deprecated": "1",
+ "EventCode": "0xAE",
+ "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
+ "Deprecated": "1",
+ "EventCode": "0x5F",
+ "EventName": "UNC_H_HITME_HIT.EX_RDS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+ "Deprecated": "1",
+ "EventCode": "0x5F",
+ "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE",
+ "Deprecated": "1",
+ "EventCode": "0x5F",
+ "EventName": "UNC_H_HITME_HIT.WBMTOE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+ "Deprecated": "1",
+ "EventCode": "0x5F",
+ "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ",
+ "Deprecated": "1",
+ "EventCode": "0x5E",
+ "EventName": "UNC_H_HITME_LOOKUP.READ",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE",
+ "Deprecated": "1",
+ "EventCode": "0x5E",
+ "EventName": "UNC_H_HITME_LOOKUP.WRITE",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+ "Deprecated": "1",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV",
+ "Deprecated": "1",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_HITME_MISS.READ_OR_INV",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+ "Deprecated": "1",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.RDINVOWN",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.SHARED",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA7",
+ "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA7",
+ "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA7",
+ "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA7",
+ "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent; Directed snoops for Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA9",
+ "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA9",
+ "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspI",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA9",
+ "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspS",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA9",
+ "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspIFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xAB",
+ "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspSFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xAB",
+ "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xAB",
+ "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xAB",
+ "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspCnflct",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+ "Deprecated": "1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+ "Deprecated": "1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL",
+ "Deprecated": "1",
+ "EventCode": "0x59",
+ "EventName": "UNC_H_IMC_READS_COUNT.NORMAL",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY",
+ "Deprecated": "1",
+ "EventCode": "0x59",
+ "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY",
"PerPkg": "1",
- "UMask": "0x03",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.FULL",
"PerPkg": "1",
- "UMask": "0x05",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG",
"PerPkg": "1",
- "UMask": "0x09",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ANY",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Local",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL",
"PerPkg": "1",
- "UMask": "0x31",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Remote",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG",
"PerPkg": "1",
- "UMask": "0x91",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
"Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM",
"Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+ "EventCode": "0x62",
+ "EventName": "UNC_H_IODC_ALLOC.INVITOM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL",
"Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+ "EventCode": "0x62",
+ "EventName": "UNC_H_IODC_ALLOC.IODCFULL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED",
"Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE",
+ "EventCode": "0x62",
+ "EventName": "UNC_H_IODC_ALLOC.OSBGATED",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized; Local - All Lines",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL",
+ "Deprecated": "1",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.ALL",
"PerPkg": "1",
- "UMask": "0x2F",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT",
"Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.SNPOUT",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; IRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE",
+ "Deprecated": "1",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.WBMTOE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; SF/LLC Evictions",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI",
+ "Deprecated": "1",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.WBMTOI",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; PRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
+ "Deprecated": "1",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; IPQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS",
+ "Deprecated": "1",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.CV0_PREF_MISS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Hit (Not a Miss)",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC",
+ "Deprecated": "1",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.CV0_PREF_VIC",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
+ "Deprecated": "1",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.RFO_HIT_S",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "UMask": "0x37",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.WC_ALIASING",
"PerPkg": "1",
- "UMask": "0x18",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_OSB",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS",
+ "EventCode": "0x55",
+ "EventName": "UNC_H_OSB",
"PerPkg": "1",
- "UMask": "0x28",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2",
"PerPkg": "1",
- "UMask": "0x50",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3",
"PerPkg": "1",
- "UMask": "0x60",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4",
"PerPkg": "1",
- "UMask": "0x90",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5",
"PerPkg": "1",
- "UMask": "0xA0",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; IRQ",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
+ "Deprecated": "1",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; SF/LLC Evictions",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
+ "Deprecated": "1",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; PRQ",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; IPQ",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Hit (Not a Miss)",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+ "BriefDescription": "read requests from home agent",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x3",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Miss",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+ "BriefDescription": "read requests from local home agent",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.READS_LOCAL",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
+ "BriefDescription": "read requests from remote home agent",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.READS_REMOTE",
"PerPkg": "1",
- "UMask": "0x37",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
+ "BriefDescription": "write requests from home agent",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.WRITES",
"PerPkg": "1",
- "UMask": "0x18",
+ "UMask": "0xc",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
+ "BriefDescription": "write requests from local home agent",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
- "UMask": "0x28",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_RING_SRC_THRTL",
+ "BriefDescription": "write requests from remote home agent",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD",
+ "Deprecated": "1",
+ "EventCode": "0xA1",
+ "EventName": "UNC_H_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK",
+ "Deprecated": "1",
+ "EventCode": "0xA1",
+ "EventName": "UNC_H_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL",
+ "Deprecated": "1",
+ "EventCode": "0xA1",
+ "EventName": "UNC_H_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV",
+ "Deprecated": "1",
+ "EventCode": "0xA1",
+ "EventName": "UNC_H_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD",
+ "Deprecated": "1",
+ "EventCode": "0xA0",
+ "EventName": "UNC_H_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK",
+ "Deprecated": "1",
+ "EventCode": "0xA0",
+ "EventName": "UNC_H_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL",
+ "Deprecated": "1",
+ "EventCode": "0xA0",
+ "EventName": "UNC_H_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV",
+ "Deprecated": "1",
+ "EventCode": "0xA0",
+ "EventName": "UNC_H_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV",
- "PerPkg": "1",
- "UMask": "0x08",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+ "Deprecated": "1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD",
+ "PerPkg": "1",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+ "Deprecated": "1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+ "Deprecated": "1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+ "Deprecated": "1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD",
+ "Deprecated": "1",
+ "EventCode": "0xA2",
+ "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK",
+ "Deprecated": "1",
+ "EventCode": "0xA2",
+ "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL",
+ "Deprecated": "1",
+ "EventCode": "0xA2",
+ "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV",
+ "Deprecated": "1",
+ "EventCode": "0xA2",
+ "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ",
+ "Deprecated": "1",
+ "EventCode": "0x13",
+ "EventName": "UNC_H_RxC_INSERTS.IPQ",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
+ "Deprecated": "1",
+ "EventCode": "0x13",
+ "EventName": "UNC_H_RxC_INSERTS.IRQ",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ",
+ "Deprecated": "1",
+ "EventCode": "0x13",
+ "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ",
+ "Deprecated": "1",
+ "EventCode": "0x13",
+ "EventName": "UNC_H_RxC_INSERTS.PRQ",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ",
+ "Deprecated": "1",
+ "EventCode": "0x13",
+ "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ",
+ "Deprecated": "1",
+ "EventCode": "0x13",
+ "EventName": "UNC_H_RxC_INSERTS.RRQ",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ",
+ "Deprecated": "1",
+ "EventCode": "0x13",
+ "EventName": "UNC_H_RxC_INSERTS.WBQ",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x23",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+ "Deprecated": "1",
+ "EventCode": "0x23",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA",
+ "Deprecated": "1",
+ "EventCode": "0x23",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.HA",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
+ "EventCode": "0x23",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x23",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
+ "EventCode": "0x23",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x23",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x23",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x19",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+ "Deprecated": "1",
+ "EventCode": "0x19",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA",
+ "Deprecated": "1",
+ "EventCode": "0x19",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.HA",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
+ "EventCode": "0x19",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x19",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
+ "EventCode": "0x19",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x19",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x19",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x24",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x24",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x24",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x24",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x24",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x24",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2C",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2C",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2C",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2C",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2C",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2C",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+ "Deprecated": "1",
+ "EventCode": "0x25",
+ "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA",
+ "Deprecated": "1",
+ "EventCode": "0x25",
+ "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+ "Deprecated": "1",
+ "EventCode": "0x2D",
+ "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA",
+ "Deprecated": "1",
+ "EventCode": "0x2D",
+ "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ",
+ "Deprecated": "1",
+ "EventCode": "0x11",
+ "EventName": "UNC_H_RxC_OCCUPANCY.IPQ",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "Deprecated": "1",
+ "EventCode": "0x11",
+ "EventName": "UNC_H_RxC_OCCUPANCY.IRQ",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ",
+ "Deprecated": "1",
+ "EventCode": "0x11",
+ "EventName": "UNC_H_RxC_OCCUPANCY.RRQ",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ",
+ "Deprecated": "1",
+ "EventCode": "0x11",
+ "EventName": "UNC_H_RxC_OCCUPANCY.WBQ",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2E",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2E",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2E",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2E",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2E",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2E",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+ "Deprecated": "1",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA",
+ "Deprecated": "1",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.HA",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "Deprecated": "1",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+ "Deprecated": "1",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x20",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x20",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x20",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x20",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x20",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x20",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+ "Deprecated": "1",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA",
+ "Deprecated": "1",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.HA",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x2B",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+ "Deprecated": "1",
+ "EventCode": "0x2B",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "Deprecated": "1",
+ "EventCode": "0x2B",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "Deprecated": "1",
+ "EventCode": "0x2B",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x2B",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "Deprecated": "1",
+ "EventCode": "0x2B",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x2B",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x2B",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x26",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x26",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x26",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x26",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x26",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x26",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+ "Deprecated": "1",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA",
+ "Deprecated": "1",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.HA",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x28",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x28",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x28",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x28",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x28",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x28",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+ "Deprecated": "1",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA",
+ "Deprecated": "1",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.HA",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+ "Deprecated": "1",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB4",
+ "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB4",
+ "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB4",
+ "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB4",
+ "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB2",
+ "EventName": "UNC_H_RxR_BYPASS.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB2",
+ "EventName": "UNC_H_RxR_BYPASS.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB2",
+ "EventName": "UNC_H_RxR_BYPASS.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB2",
+ "EventName": "UNC_H_RxR_BYPASS.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB2",
+ "EventName": "UNC_H_RxR_BYPASS.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB2",
+ "EventName": "UNC_H_RxR_BYPASS.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB3",
+ "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB3",
+ "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB3",
+ "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB3",
+ "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB3",
+ "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV",
+ "Deprecated": "1",
+ "EventCode": "0xB3",
+ "EventName": "UNC_H_RxR_CRD_STARVED.IFV",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB3",
+ "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB1",
+ "EventName": "UNC_H_RxR_INSERTS.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB1",
+ "EventName": "UNC_H_RxR_INSERTS.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB1",
+ "EventName": "UNC_H_RxR_INSERTS.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB1",
+ "EventName": "UNC_H_RxR_INSERTS.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB1",
+ "EventName": "UNC_H_RxR_INSERTS.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB1",
+ "EventName": "UNC_H_RxR_INSERTS.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB0",
+ "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB0",
+ "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB0",
+ "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB0",
+ "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0xB0",
+ "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0xB0",
+ "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE",
+ "Deprecated": "1",
+ "EventCode": "0x3D",
+ "EventName": "UNC_H_SF_EVICTION.E_STATE",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE",
+ "Deprecated": "1",
+ "EventCode": "0x3D",
+ "EventName": "UNC_H_SF_EVICTION.M_STATE",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE",
+ "Deprecated": "1",
+ "EventCode": "0x3D",
+ "EventName": "UNC_H_SF_EVICTION.S_STATE",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.BCST_REM",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.LOCAL",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.REMOTE",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPFWD",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPI",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPS",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.IV",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.IV",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA6",
+ "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA6",
+ "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA6",
+ "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA6",
+ "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA8",
+ "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA8",
+ "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA8",
+ "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA8",
+ "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xAA",
+ "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xAA",
+ "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xAA",
+ "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xAA",
+ "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN",
+ "Deprecated": "1",
+ "EventCode": "0xAC",
+ "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP",
+ "Deprecated": "1",
+ "EventCode": "0xAC",
+ "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC",
+ "Deprecated": "1",
+ "EventCode": "0x56",
+ "EventName": "UNC_H_WB_PUSH_MTOI.LLC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM",
+ "Deprecated": "1",
+ "EventCode": "0x56",
+ "EventName": "UNC_H_WB_PUSH_MTOI.MEM",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
+ "Deprecated": "1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
+ "Deprecated": "1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
+ "Deprecated": "1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
+ "Deprecated": "1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
+ "Deprecated": "1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
+ "Deprecated": "1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE",
+ "PerPkg": "1",
+ "UMask": "0xe4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM",
+ "PerPkg": "1",
+ "UMask": "0xf0",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE",
+ "PerPkg": "1",
+ "UMask": "0xe2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM",
+ "PerPkg": "1",
+ "UMask": "0xe8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE",
+ "PerPkg": "1",
+ "UMask": "0xe1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE",
+ "PerPkg": "1",
+ "UMask": "0x44",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM",
+ "PerPkg": "1",
+ "UMask": "0x50",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE",
+ "PerPkg": "1",
+ "UMask": "0x42",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM",
+ "PerPkg": "1",
+ "UMask": "0x48",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE",
+ "PerPkg": "1",
+ "UMask": "0x41",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE",
+ "PerPkg": "1",
+ "UMask": "0x84",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM",
+ "PerPkg": "1",
+ "UMask": "0x90",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE",
+ "PerPkg": "1",
+ "UMask": "0x82",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM",
+ "PerPkg": "1",
+ "UMask": "0x88",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE",
+ "PerPkg": "1",
+ "UMask": "0x81",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE",
+ "PerPkg": "1",
+ "UMask": "0x24",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM",
+ "PerPkg": "1",
+ "UMask": "0x30",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE",
+ "PerPkg": "1",
+ "UMask": "0x22",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM",
+ "PerPkg": "1",
+ "UMask": "0x28",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE",
+ "PerPkg": "1",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Clockticks of the IIO Traffic Controller",
+ "EventCode": "0x1",
+ "EventName": "UNC_IIO_CLOCKTICKS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+ "FCMask": "0x4",
+ "PerPkg": "1",
+ "PortMask": "0x0f",
+ "UMask": "0x3",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+ "FCMask": "0x4",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "UMask": "0x3",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+ "FCMask": "0x4",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "UMask": "0x3",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+ "FCMask": "0x4",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "UMask": "0x3",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+ "FCMask": "0x4",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "UMask": "0x3",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts; Port 3",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+ "FCMask": "0x04",
+ "PerPkg": "1",
+ "UMask": "0xf",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+ "FCMask": "0x04",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+ "FCMask": "0x04",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+ "FCMask": "0x04",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+ "FCMask": "0x04",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV",
+ "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV",
+ "BriefDescription": "Num Link Correctable Errors",
+ "EventCode": "0xF",
+ "EventName": "UNC_IIO_LINK_NUM_CORR_ERR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV",
+ "BriefDescription": "Num Link Retries",
+ "EventCode": "0xE",
+ "EventName": "UNC_IIO_LINK_NUM_RETRIES",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "FaST wire asserted; Vertical",
- "Counter": "0,1,2,3",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_FAST_ASSERTED.VERT",
+ "BriefDescription": "Number packets that passed the Mask/Match Filter",
+ "EventCode": "0x21",
+ "EventName": "UNC_IIO_MASK_MATCH",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL",
+ "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus",
+ "EventCode": "0x2",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if all bits specified by mask match",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Local - Lines in M State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+ "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus",
+ "EventCode": "0x2",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x21",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if all bits specified by mask match",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Local - Lines in E State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+ "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
+ "EventCode": "0x2",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x22",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if all bits specified by mask match",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Local - Lines in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
+ "BriefDescription": "AND Mask/match for debug bus; PCIE bus",
+ "EventCode": "0x2",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if all bits specified by mask match",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Local - Lines in F State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
+ "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
+ "EventCode": "0x2",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x28",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if all bits specified by mask match",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Remote - Lines in M State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
+ "BriefDescription": "AND Mask/match for debug bus",
+ "EventCode": "0x2",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x81",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if all bits specified by mask match",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Remote - Lines in E State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
+ "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus",
+ "EventCode": "0x3",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
"PerPkg": "1",
- "UMask": "0x82",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if any bits specified by mask match",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Remote - Lines in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
+ "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus",
+ "EventCode": "0x3",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x84",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if any bits specified by mask match",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Remote - Lines in F State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F",
+ "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
+ "EventCode": "0x3",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x88",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if any bits specified by mask match",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Remote - All Lines",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+ "BriefDescription": "OR Mask/match for debug bus; PCIE bus",
+ "EventCode": "0x3",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
"PerPkg": "1",
- "UMask": "0x8F",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if any bits specified by mask match",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; All from Local",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
+ "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
+ "EventCode": "0x3",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x37",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if any bits specified by mask match",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RdCur misses from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR",
- "Filter": "config1=0x43C33",
+ "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)",
+ "EventCode": "0x3",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PublicDescription": "Asserted if any bits specified by mask match",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RFO misses from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "UNC_IIO_NOTHING",
+ "EventName": "UNC_IIO_NOTHING",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; ItoM misses from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
- "Filter": "config1=0x49033",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
- "Filter": "config1=0x49033",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x2",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR",
- "Filter": "config1=0x43C33",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x4",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO misses from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x8",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
+ "PortMask": "0x10",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
+ "PortMask": "0x20",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
+ "PortMask": "0x1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts; Port 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
+ "PortMask": "0x2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Num Link Correctable Errors",
- "Counter": "0,1,2,3",
- "EventCode": "0xF",
- "EventName": "UNC_IIO_LINK_NUM_CORR_ERR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2",
+ "FCMask": "0x7",
"PerPkg": "1",
+ "PortMask": "0x4",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Num Link Retries",
- "Counter": "0,1,2,3",
- "EventCode": "0xE",
- "EventName": "UNC_IIO_LINK_NUM_RETRIES",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3",
+ "FCMask": "0x7",
"PerPkg": "1",
+ "PortMask": "0x8",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number packets that passed the Mask/Match Filter",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_IIO_MASK_MATCH",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0",
+ "FCMask": "0x7",
"PerPkg": "1",
+ "PortMask": "0x1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x1",
+ "PortMask": "0x2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus; PCIE bus",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x2",
+ "PortMask": "0x4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3",
+ "FCMask": "0x7",
"PerPkg": "1",
+ "PortMask": "0x8",
"UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x8",
+ "PortMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x10",
+ "PortMask": "0x20",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x20",
+ "PortMask": "0x1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1",
+ "FCMask": "0x7",
"PerPkg": "1",
+ "PortMask": "0x2",
"UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus; PCIE bus",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x2",
+ "PortMask": "0x4",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x4",
+ "PortMask": "0x8",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x8",
+ "PortMask": "0x10",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x10",
+ "PortMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x20",
+ "PortMask": "0x1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "UNC_IIO_NOTHING",
- "Counter": "0,1,2,3",
- "EventName": "UNC_IIO_NOTHING",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1",
+ "FCMask": "0x7",
"PerPkg": "1",
+ "PortMask": "0x2",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x2",
+ "PortMask": "0x4",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x2",
+ "PortMask": "0x8",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x2",
+ "PortMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x2",
+ "PortMask": "0x20",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
- "Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x83",
"EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0",
@@ -8254,7 +12235,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
- "Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x83",
"EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1",
@@ -8266,7 +12246,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
- "Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x83",
"EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2",
@@ -8278,7 +12257,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
- "Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x83",
"EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3",
@@ -8289,784 +12267,697 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0",
- "FCMask": "0x7",
- "PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1",
- "FCMask": "0x7",
- "PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x10",
+ "PortMask": "0x10",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x10",
+ "PortMask": "0x20",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
+ "PortMask": "0x1",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
+ "PortMask": "0x2",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x1",
+ "PortMask": "0x4",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x1",
+ "PortMask": "0x8",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x1",
+ "PortMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x1",
+ "PortMask": "0x20",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x4",
+ "PortMask": "0x10",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x4",
+ "PortMask": "0x20",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x4",
+ "PortMask": "0x1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x4",
+ "PortMask": "0x2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x8",
+ "PortMask": "0x4",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x8",
+ "PortMask": "0x8",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x8",
+ "PortMask": "0x10",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x8",
+ "PortMask": "0x20",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
+ "PortMask": "0x10",
"UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
+ "PortMask": "0x20",
"UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x20",
+ "PortMask": "0x1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x20",
+ "PortMask": "0x2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x40",
+ "PortMask": "0x4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x40",
+ "PortMask": "0x8",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Symbol Times on Link",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_IIO_SYMBOL_TIMES",
- "PerPkg": "1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
+ "PortMask": "0x10",
"UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
+ "PortMask": "0x20",
"UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x1",
+ "PortMask": "0x1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x1",
+ "PortMask": "0x2",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x2",
+ "PortMask": "0x4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x2",
+ "PortMask": "0x8",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x2",
+ "PortMask": "0x10",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x2",
+ "PortMask": "0x20",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x8",
+ "PortMask": "0x10",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x8",
+ "PortMask": "0x20",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Symbol Times on Link",
+ "EventCode": "0x82",
+ "EventName": "UNC_IIO_SYMBOL_TIMES",
+ "PerPkg": "1",
+ "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x8",
+ "PortMask": "0x1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x8",
+ "PortMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
+ "PortMask": "0x4",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
+ "PortMask": "0x8",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
+ "PortMask": "0x10",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
+ "PortMask": "0x20",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0",
@@ -9077,8 +12968,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1",
@@ -9089,8 +12979,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2",
@@ -9101,8 +12990,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3",
@@ -9113,59 +13001,76 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.PART0",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.PART1",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.PART2",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.PART3",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
@@ -9173,11 +13078,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
@@ -9185,11 +13089,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
@@ -9197,11 +13100,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
@@ -9209,107 +13111,98 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x2",
+ "PortMask": "0x10",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x2",
+ "PortMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x2",
+ "PortMask": "0x1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x2",
+ "PortMask": "0x2",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x4",
+ "PortMask": "0x4",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x4",
+ "PortMask": "0x8",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x4",
+ "PortMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x4",
+ "PortMask": "0x20",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
@@ -9317,11 +13210,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
@@ -9329,11 +13221,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
@@ -9341,11 +13232,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
@@ -9353,104 +13243,95 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x10",
+ "PortMask": "0x10",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x10",
+ "PortMask": "0x20",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x10",
+ "PortMask": "0x1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x10",
+ "PortMask": "0x2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x20",
+ "PortMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x20",
+ "PortMask": "0x8",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x20",
+ "PortMask": "0x10",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x20",
+ "PortMask": "0x20",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0",
@@ -9462,7 +13343,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1",
@@ -9474,7 +13354,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2",
@@ -9486,7 +13365,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xC1",
"EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3",
@@ -9497,379 +13375,263 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0",
- "FCMask": "0x7",
- "PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x80",
+ "PortMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x80",
+ "PortMask": "0x20",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "VTd Access; Vtd hit",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "VTd Access; context cache miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "VTd Access; L1 miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "VTd Access; L2 miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "VTd Access; L3 miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS",
- "PerPkg": "1",
+ "PortMask": "0x1",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Access; TLB miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "VTd Access; TLB is full",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "VTd Access; TLB miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "VTd Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_VTD_OCCUPANCY",
- "PerPkg": "1",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
+ "PortMask": "0x2",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PortMask": "0x4",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x4",
+ "PortMask": "0x8",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x4",
+ "PortMask": "0x10",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x1",
+ "PortMask": "0x1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x1",
+ "PortMask": "0x2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
+ "PortMask": "0x4",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
+ "PortMask": "0x8",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x8",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x8",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x2",
+ "PortMask": "0x1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x2",
+ "PortMask": "0x2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
+ "PortMask": "0x4",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
+ "PortMask": "0x8",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
+ "PortMask": "0x1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
+ "PortMask": "0x2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
+ "PortMask": "0x4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
+ "PortMask": "0x8",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
@@ -9877,11 +13639,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
@@ -9889,203 +13650,186 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
+ "PortMask": "0x1",
"UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PortMask": "0x2",
"UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x8",
+ "PortMask": "0x4",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x8",
+ "PortMask": "0x8",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
+ "Deprecated": "1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
+ "PortMask": "0x1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
+ "PortMask": "0x2",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x4",
+ "PortMask": "0x4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x4",
+ "PortMask": "0x8",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
+ "PortMask": "0x1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
+ "PortMask": "0x2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x8",
+ "PortMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x8",
+ "PortMask": "0x8",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
@@ -10093,11 +13837,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
@@ -10105,12643 +13848,12288 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
+ "PortMask": "0x01",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PortMask": "0x02",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
+ "PortMask": "0x04",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x80",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x80",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
+ "PortMask": "0x01",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
+ "PortMask": "0x02",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x4",
+ "PortMask": "0x04",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x4",
+ "PortMask": "0x08",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x1",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x1",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x8",
+ "PortMask": "0x01",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x8",
+ "PortMask": "0x02",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x2",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x2",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
"UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
"UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x20",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x20",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x80",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x80",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x80",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x80",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x40",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x40",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
+ "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
+ "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
+ "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x80",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
+ "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x80",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
+ "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x04",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
+ "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x04",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
+ "PortMask": "0x01",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
+ "PortMask": "0x02",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
+ "PortMask": "0x04",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
+ "PortMask": "0x08",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x02",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x02",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+ "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+ "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+ "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+ "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x20",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x20",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x20",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x20",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+ "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+ "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x04",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x04",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
+ "PortMask": "0x01",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
+ "PortMask": "0x02",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
+ "PortMask": "0x04",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PortMask": "0x08",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x08",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x08",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
+ "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
+ "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+ "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+ "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+ "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+ "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x20",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x20",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x20",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x20",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+ "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+ "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "VTd Access; context cache miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "VTd Access; L1 miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "VTd Access; L2 miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "VTd Access; L3 miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "VTd Access; Vtd hit",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "VTd Access; TLB miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS",
"PerPkg": "1",
- "PortMask": "0x08",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "VTd Access; TLB is full",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL",
"PerPkg": "1",
- "PortMask": "0x10",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "VTd Access; TLB miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "VTd Occupancy",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_VTD_OCCUPANCY",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Total Write Cache Occupancy; Any Source",
+ "EventCode": "0xF",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Total Write Cache Occupancy; Snoops",
+ "EventCode": "0xF",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Total IRP occupancy of inbound read and write requests.",
+ "EventCode": "0xF",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.",
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "IRP Clocks",
+ "EventCode": "0x1",
+ "EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
- "Unit": "IIO"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Coherent Ops; CLFlush",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x80",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; CRd",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.CRD",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Coherent Ops; DRd",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.DRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Coherent Ops; PCIDCAHin5t",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Coherent Ops; PCIRdCur",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Coherent Ops; WbMtoI",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "FAF RF full",
+ "EventCode": "0x17",
+ "EventName": "UNC_I_FAF_FULL",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+ "EventCode": "0x18",
+ "EventName": "UNC_I_FAF_INSERTS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Occupancy of the IRP FAF queue.",
+ "EventCode": "0x19",
+ "EventName": "UNC_I_FAF_OCCUPANCY",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "FAF allocation -- sent to ADQ",
+ "EventCode": "0x16",
+ "EventName": "UNC_I_FAF_TRANSACTIONS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "All Inserts Inbound (p2p + faf + cset)",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.FAST_REQ",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 0",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.UNKNOWN",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 1; Lost Forward",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
- "PortMask": "0x10",
+ "PublicDescription": "Snoop pulled away ownership before a write was committed",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 1; Received Invalid",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 1; Received Valid",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "P2P Requests",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_P2P_INSERTS",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "P2P requests from the ITC",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "P2P Occupancy",
+ "EventCode": "0x15",
+ "EventName": "UNC_I_P2P_OCCUPANCY",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "P2P B & S Queue Occupancy",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "P2P Transactions; P2P completions",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "P2P Transactions; match if local only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
"PerPkg": "1",
- "PortMask": "0x10",
"UMask": "0x40",
- "Unit": "IIO"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "P2P Transactions; match if local and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Total Write Cache Occupancy; Any Source",
- "Counter": "0,1",
- "EventCode": "0xF",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+ "BriefDescription": "P2P Transactions; P2P Message",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Total Write Cache Occupancy; Snoops",
- "Counter": "0,1",
- "EventCode": "0xF",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+ "BriefDescription": "P2P Transactions; P2P reads",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "IRP Clocks",
- "Counter": "0,1",
- "EventCode": "0x1",
- "EventName": "UNC_I_CLOCKTICKS",
+ "BriefDescription": "P2P Transactions; Match if remote only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
"PerPkg": "1",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; PCIRdCur",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+ "BriefDescription": "P2P Transactions; match if remote and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x20",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; CRd",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.CRD",
+ "BriefDescription": "P2P Transactions; P2P Writes",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; DRd",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.DRD",
+ "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
+ "UMask": "0x7e",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; PCIDCAHin5t",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+ "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
+ "UMask": "0x74",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; WbMtoI",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+ "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
+ "UMask": "0x72",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; CLFlush",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+ "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
+ "UMask": "0x78",
"Unit": "IRP"
},
{
- "BriefDescription": "FAF RF full",
- "Counter": "0,1",
- "EventCode": "0x17",
- "EventName": "UNC_I_FAF_FULL",
+ "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
"PerPkg": "1",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
+ "UMask": "0x71",
"Unit": "IRP"
},
{
- "BriefDescription": "FAF allocation -- sent to ADQ",
- "Counter": "0,1",
- "EventCode": "0x16",
- "EventName": "UNC_I_FAF_TRANSACTIONS",
+ "BriefDescription": "Snoop Responses; Hit E or S",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "All Inserts Inbound (p2p + faf + cset)",
- "Counter": "0,1",
- "EventCode": "0x1E",
- "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+ "BriefDescription": "Snoop Responses; Hit I",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)",
- "Counter": "0,1",
- "EventCode": "0x1E",
- "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+ "BriefDescription": "Snoop Responses; Hit M",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.FAST_REQ",
+ "BriefDescription": "Snoop Responses; Miss",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.FAST_REJ",
+ "BriefDescription": "Snoop Responses; SnpCode",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+ "BriefDescription": "Snoop Responses; SnpData",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x20",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+ "BriefDescription": "Snoop Responses; SnpInv",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "BriefDescription": "Inbound Transaction Count; Atomic",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
"UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.FAST_XFER",
+ "BriefDescription": "Inbound Transaction Count; Other",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
"UMask": "0x20",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+ "BriefDescription": "Inbound Transaction Count; Read Prefetches",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.UNKNOWN",
+ "BriefDescription": "Inbound Transaction Count; Reads",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SLOW_I",
+ "BriefDescription": "Inbound Transaction Count; Writes",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+ "UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SLOW_S",
+ "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SLOW_E",
+ "BriefDescription": "AK Egress Allocations",
+ "EventCode": "0xB",
+ "EventName": "UNC_I_TxC_AK_INSERTS",
"PerPkg": "1",
- "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SLOW_M",
+ "BriefDescription": "BL DRS Egress Cycles Full",
+ "EventCode": "0x5",
+ "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Lost Forward",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.LOST_FWD",
+ "BriefDescription": "BL DRS Egress Inserts",
+ "EventCode": "0x2",
+ "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Invalid",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "BriefDescription": "BL DRS Egress Occupancy",
+ "EventCode": "0x8",
+ "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Valid",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "BriefDescription": "BL NCB Egress Cycles Full",
+ "EventCode": "0x6",
+ "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Requests",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_I_P2P_INSERTS",
+ "BriefDescription": "BL NCB Egress Inserts",
+ "EventCode": "0x3",
+ "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Occupancy",
- "Counter": "0,1",
- "EventCode": "0x15",
- "EventName": "UNC_I_P2P_OCCUPANCY",
+ "BriefDescription": "BL NCB Egress Occupancy",
+ "EventCode": "0x9",
+ "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Transactions; P2P reads",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+ "BriefDescription": "BL NCS Egress Cycles Full",
+ "EventCode": "0x7",
+ "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Transactions; P2P Writes",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+ "BriefDescription": "BL NCS Egress Inserts",
+ "EventCode": "0x4",
+ "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
"PerPkg": "1",
- "UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Transactions; P2P Message",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+ "BriefDescription": "BL NCS Egress Occupancy",
+ "EventCode": "0xA",
+ "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Transactions; P2P completions",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+ "BriefDescription": "No AD Egress Credit Stalls",
+ "EventCode": "0x1A",
+ "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Transactions; Match if remote only",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+ "BriefDescription": "No BL Egress Credit Stalls",
+ "EventCode": "0x1B",
+ "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Transactions; match if remote and target matches",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0xD",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Transactions; match if local only",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0xE",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
- "BriefDescription": "P2P Transactions; match if local and target matches",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+ "BriefDescription": "Outbound Request Queue Occupancy",
+ "EventCode": "0xC",
+ "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Miss",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.MISS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; Hit I",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; Hit E or S",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; Hit M",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; SnpCode",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; SnpData",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Snoop Responses; SnpInv",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPINV",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Inbound Transaction Count; Reads",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.READS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Inbound Transaction Count; Writes",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Inbound Transaction Count; Read Prefetches",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Inbound Transaction Count; Atomic",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Inbound Transaction Count; Other",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "No AD Egress Credit Stalls",
- "Counter": "0,1",
- "EventCode": "0x1A",
- "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "AK Egress Allocations",
- "Counter": "0,1",
- "EventCode": "0xB",
- "EventName": "UNC_I_TxC_AK_INSERTS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL DRS Egress Cycles Full",
- "Counter": "0,1",
- "EventCode": "0x5",
- "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL DRS Egress Inserts",
- "Counter": "0,1",
- "EventCode": "0x2",
- "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL DRS Egress Occupancy",
- "Counter": "0,1",
- "EventCode": "0x8",
- "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCB Egress Cycles Full",
- "Counter": "0,1",
- "EventCode": "0x6",
- "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCB Egress Inserts",
- "Counter": "0,1",
- "EventCode": "0x3",
- "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCB Egress Occupancy",
- "Counter": "0,1",
- "EventCode": "0x9",
- "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCS Egress Cycles Full",
- "Counter": "0,1",
- "EventCode": "0x7",
- "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCS Egress Inserts",
- "Counter": "0,1",
- "EventCode": "0x4",
- "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCS Egress Occupancy",
- "Counter": "0,1",
- "EventCode": "0xA",
- "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
- "EventCode": "0x1B",
- "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "EventCode": "0xD",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "EventCode": "0xE",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
- "EventCode": "0xC",
- "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x72",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x74",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x78",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x7e",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x71",
- "Unit": "IRP"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
- "Unit": "UPI LL"
- },
- {
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
- },
- {
- "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_UPI_PHY_INIT_CYCLES",
- "PerPkg": "1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "L1 Req Nack",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_UPI_POWER_L1_NACK",
+ "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
+ "EventCode": "0x22",
+ "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "L1 Req (same as L1 Ack)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "M2M to iMC Bypass; Taken",
"EventCode": "0x22",
- "EventName": "UNC_UPI_POWER_L1_REQ",
+ "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "BriefDescription": "M2M to iMC Bypass; Not Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "BriefDescription": "M2M to iMC Bypass; Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "BriefDescription": "Cycles - at UCLK",
+ "EventName": "UNC_M2M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xC0",
+ "EventName": "UNC_M2M_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles in L0. Receive side",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
"EventCode": "0x24",
- "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
+ "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CRC Errors Detected",
- "Counter": "0,1,2,3",
- "EventCode": "0xB",
- "EventName": "UNC_UPI_RxL_CRC_ERRORS",
+ "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)",
+ "Unit": "M2M"
},
{
- "BriefDescription": "LLR Requests Sent",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
+ "BriefDescription": "Number of reads in which direct to core transaction were overridden",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden",
+ "Unit": "M2M"
},
{
- "BriefDescription": "VN0 Credit Consumed",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
+ "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+ "EventCode": "0x28",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden",
+ "Unit": "M2M"
},
{
- "BriefDescription": "VN1 Credit Consumed",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
+ "BriefDescription": "Cycles when direct to Intel UPI was disabled",
+ "EventCode": "0x27",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled",
+ "Unit": "M2M"
},
{
- "BriefDescription": "VNA Credit Consumed",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
+ "BriefDescription": "Messages sent direct to the Intel UPI",
+ "EventCode": "0x26",
+ "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Received; Slot 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+ "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+ "EventCode": "0x29",
+ "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Received; Slot 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+ "BriefDescription": "Directory Hit; On NonDirty Line in A State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Received; Slot 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+ "BriefDescription": "Directory Hit; On NonDirty Line in I State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UPI LL"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Received; Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.DATA",
+ "BriefDescription": "Directory Hit; On NonDirty Line in L State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Received; LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+ "BriefDescription": "Directory Hit; On NonDirty Line in S State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Received; LLCTRL",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+ "BriefDescription": "Directory Hit; On Dirty Line in A State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR",
+ "BriefDescription": "Directory Hit; On Dirty Line in I State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ",
+ "BriefDescription": "Directory Hit; On Dirty Line in L State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP",
+ "BriefDescription": "Directory Hit; On Dirty Line in S State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
"PerPkg": "1",
- "UMask": "0x9",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP",
+ "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
"PerPkg": "1",
- "UMask": "0xA",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.WB",
+ {
+ "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
"PerPkg": "1",
- "UMask": "0xB",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB",
+ "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
"PerPkg": "1",
- "UMask": "0xC",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS",
+ "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
"PerPkg": "1",
- "UMask": "0xD",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets; Slot 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+ "BriefDescription": "Directory Miss; On NonDirty Line in A State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets; Slot 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+ "BriefDescription": "Directory Miss; On NonDirty Line in I State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets; Slot 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+ "BriefDescription": "Directory Miss; On NonDirty Line in L State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UPI LL"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "BriefDescription": "Directory Miss; On NonDirty Line in S State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "BriefDescription": "Directory Miss; On Dirty Line in A State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "BriefDescription": "Directory Miss; On Dirty Line in I State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "BriefDescription": "Directory Miss; On Dirty Line in L State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "BriefDescription": "Directory Miss; On Dirty Line in S State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "BriefDescription": "Multi-socket cacheline Directory update from A to I",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
"PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid)",
"UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "BriefDescription": "Multi-socket cacheline Directory update from A to S",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared)",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "BriefDescription": "Multi-socket cacheline Directory update from I to A",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
"PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll)",
"UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "BriefDescription": "Multi-socket cacheline Directory update from I to S",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared)",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "BriefDescription": "Multi-socket cacheline Directory update from S to A",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
"PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll)",
"UMask": "0x10",
- "Unit": "UPI LL"
- },
- {
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "BriefDescription": "Multi-socket cacheline Directory update from S to I",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid)",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+ "EventCode": "0xAE",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+ "EventCode": "0xAE",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "BriefDescription": "FaST wire asserted; Horizontal",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_FAST_ASSERTED.HORZ",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles in L0. Transmit side",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
+ "BriefDescription": "FaST wire asserted; Vertical",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_FAST_ASSERTED.VERT",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Sent; Slot 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Sent; Slot 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Sent; Slot 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Sent; LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Sent; LLCTRL",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x9",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.WB",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xE",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0xF",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_UPI_TxL_INSERTS",
+ "BriefDescription": "Horizontal IV Ring in Use; Left",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x42",
- "EventName": "UNC_UPI_TxL_OCCUPANCY",
+ "BriefDescription": "Horizontal IV Ring in Use; Right",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
- "Counter": "0,1,2,3",
- "EventCode": "0x45",
- "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "BriefDescription": "Reads to iMC issued",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ALL",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "VNA Credits Pending Return - Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x44",
- "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
+ "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority.",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "BriefDescription": "M2M Reads Issued to iMC; Critical Priority",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ISOCH",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Received; Protocol Header",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+ "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.NORMAL",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Sent; Protocol Header",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+ "BriefDescription": "Writes to iMC issued",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.ALL",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC",
+ "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.REM",
+ "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.NI",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "UPI LL"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
+ "BriefDescription": "Partial Non-Isochronous writes to the iMC",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR",
+ "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
- "UMaskExt": "0x10",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
+ "BriefDescription": "Number Packet Header Matches; MC Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MC",
"PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR",
+ "BriefDescription": "Number Packet Header Matches; Mesh Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MESH",
"PerPkg": "1",
- "UMaskExt": "0x40",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": "Prefetch CAM Cycles Full",
+ "EventCode": "0x53",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0xA",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty",
+ "EventCode": "0x54",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0xC",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Valid Flits Received; Idle",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.IDLE",
+ "BriefDescription": "Prefetch requests that got turn into a demand request",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS",
"PerPkg": "1",
- "UMask": "0x47",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory)",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+ "BriefDescription": "Inserts into the Memory Controller Prefetch Queue",
+ "EventCode": "0x57",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
+ "BriefDescription": "Prefetch CAM Occupancy",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x0108",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x09",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x0109",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x0A",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x010A",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x0C",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x010C",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x0D",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x010D",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x0E",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x010E",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x010F",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
+ "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x108",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x09",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x109",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x0A",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x10A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+ "Deprecated": "1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
- "UMask": "0x0C",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+ "Deprecated": "1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
- "UMask": "0x10C",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
+ "Deprecated": "1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
- "UMask": "0x0D",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0",
"PerPkg": "1",
- "UMask": "0x10D",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1",
"PerPkg": "1",
- "UMask": "0x0E",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2",
"PerPkg": "1",
- "UMask": "0x10E",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
"PerPkg": "1",
- "UMask": "0x10F",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
"PerPkg": "1",
- "UMask": "0x01AA",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
+ "BriefDescription": "AD Ingress (from CMS) Full",
+ "EventCode": "0x4",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x012A",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+ "BriefDescription": "AD Ingress (from CMS) Not Empty",
+ "EventCode": "0x3",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+ "BriefDescription": "AD Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x1",
+ "EventName": "UNC_M2M_RxC_AD_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and",
+ "Unit": "M2M"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+ "BriefDescription": "AD Ingress (from CMS) Occupancy",
+ "EventCode": "0x2",
+ "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
+ "BriefDescription": "BL Ingress (from CMS) Full",
+ "EventCode": "0x8",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x1AA",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
+ "BriefDescription": "BL Ingress (from CMS) Not Empty",
+ "EventCode": "0x7",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x12A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2M to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN",
+ "BriefDescription": "BL Ingress (from CMS) Allocations",
+ "EventCode": "0x5",
+ "EventName": "UNC_M2M_RxC_BL_INSERTS",
"PerPkg": "1",
- "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles - at UCLK",
- "Counter": "0,1,2,3",
- "EventName": "UNC_M2M_CLOCKTICKS",
+ "BriefDescription": "BL Ingress (from CMS) Occupancy",
+ "EventCode": "0x6",
+ "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
"PerPkg": "1",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Hit; On Dirty Line in I State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Hit; On Dirty Line in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Hit; On Dirty Line in L State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Hit; On Dirty Line in A State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Hit; On NonDirty Line in I State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Hit; On NonDirty Line in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Hit; On NonDirty Line in L State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+ "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Hit; On NonDirty Line in A State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Miss; On Dirty Line in I State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Miss; On Dirty Line in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+ "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Miss; On Dirty Line in L State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Miss; On Dirty Line in A State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Miss; On NonDirty Line in I State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+ "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Miss; On NonDirty Line in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Miss; On NonDirty Line in L State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Directory Miss; On NonDirty Line in A State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+ "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Reads Issued to iMC; Critical Priority",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ISOCH",
+ "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS",
+ "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL",
+ "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS",
+ "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Number Packet Header Matches; Mesh Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MESH",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Number Packet Header Matches; MC Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MC",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Cycles Full",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Cycles Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY",
+ "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Number AD Ingress Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_M2M_TGR_AD_CREDITS",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Number BL Ingress Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x42",
- "EventName": "UNC_M2M_TGR_BL_CREDITS",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Cycles Full; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Cycles Full; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Cycles Full; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Cycles Not Empty; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Cycles Not Empty; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Cycles Not Empty; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Inserts; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Inserts; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Inserts; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Occupancy; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Tracker Occupancy; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Tracker Occupancy; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Pending Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x48",
- "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Full; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Write Tracker Cycles Full; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Full; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1",
+ "BriefDescription": "Number AD Ingress Credits",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2M_TGR_AD_CREDITS",
"PerPkg": "1",
- "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2",
+ "BriefDescription": "Number BL Ingress Credits",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2M_TGR_BL_CREDITS",
"PerPkg": "1",
- "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Inserts; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0",
+ "BriefDescription": "Tracker Cycles Full; Channel 0",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Inserts; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1",
+ "BriefDescription": "Tracker Cycles Full; Channel 1",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Inserts; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2",
+ "BriefDescription": "Tracker Cycles Full; Channel 2",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Occupancy; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "Tracker Cycles Not Empty; Channel 0",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Occupancy; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "Tracker Cycles Not Empty; Channel 1",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Occupancy; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2",
+ "BriefDescription": "Tracker Cycles Not Empty; Channel 2",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Tracker Inserts; Channel 0",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Tracker Inserts; Channel 1",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "Tracker Inserts; Channel 2",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Tracker Occupancy; Channel 0",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Tracker Occupancy; Channel 1",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Tracker Occupancy; Channel 2",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Data Pending Occupancy",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "AD Egress (to CMS) Credit Acquired",
+ "EventCode": "0xD",
+ "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+ "EventCode": "0xE",
+ "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "AD Egress (to CMS) Full",
+ "EventCode": "0xC",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "AD Egress (to CMS) Not Empty",
+ "EventCode": "0xB",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "AD Egress (to CMS) Allocations",
+ "EventCode": "0x9",
+ "EventName": "UNC_M2M_TxC_AD_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+ "EventCode": "0xF",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "AD Egress (to CMS) Occupancy",
+ "EventCode": "0xA",
+ "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.NDR",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "AK Egress (to CMS) Full; All",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x88",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0xa0",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x90",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "AK Egress (to CMS) Not Empty; All",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "AK Egress (to CMS) Allocations; All",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0",
+ "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1",
+ "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2",
+ "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3",
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4",
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5",
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
- "Counter": "0,1,2,3",
- "EventCode": "0xAE",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0xAE",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "AK Egress (to CMS) Occupancy; All",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "AK Egress (to CMS) Sideband",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Sideband",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Left",
- "Counter": "0,1,2,3",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
+ "EventCode": "0x1A",
+ "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Right",
- "Counter": "0,1,2,3",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
+ "EventCode": "0x1A",
+ "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "BL Egress (to CMS) Full; All",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "BL Egress (to CMS) Not Empty; All",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "BL Egress (to CMS) Allocations; All",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "BL Egress (to CMS) Occupancy; All",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_RING_SRC_THRTL",
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+ "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC",
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC",
+ "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC",
+ "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "CMS Vertical ADS Used; IV",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0xE",
- "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Egress (to CMS) Credit Acquired",
- "Counter": "0,1,2,3",
- "EventCode": "0xD",
- "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "EventCode": "0xC",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0xB",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0xF",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x10",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.NDR",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1E",
- "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1E",
- "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+ "BriefDescription": "CMS Vert Egress Allocations; IV",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1A",
- "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1A",
- "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+ "BriefDescription": "CMS Vertical Egress NACKs; IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "CMS Vert Egress Occupancy; IV",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "Vertical IV Ring in Use; Down",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC",
+ "BriefDescription": "Vertical IV Ring in Use; Up",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
+ "Deprecated": "1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
+ "Deprecated": "1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
+ "Deprecated": "1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC",
+ "BriefDescription": "Write Tracker Cycles Full; Channel 0",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "Write Tracker Cycles Full; Channel 1",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC",
+ "BriefDescription": "Write Tracker Cycles Full; Channel 2",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC",
+ "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC",
+ "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC",
+ "BriefDescription": "Write Tracker Inserts; Channel 0",
+ "EventCode": "0x61",
+ "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "Write Tracker Inserts; Channel 1",
+ "EventCode": "0x61",
+ "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC",
+ "BriefDescription": "Write Tracker Inserts; Channel 2",
+ "EventCode": "0x61",
+ "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC",
+ "BriefDescription": "Write Tracker Occupancy; Channel 0",
+ "EventCode": "0x60",
+ "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Write Tracker Occupancy; Channel 1",
+ "EventCode": "0x60",
+ "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC",
+ "BriefDescription": "Write Tracker Occupancy; Channel 2",
+ "EventCode": "0x60",
+ "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1",
+ "BriefDescription": "CBox AD Credits Empty; Requests",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0",
+ "BriefDescription": "CBox AD Credits Empty; Snoops",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1",
+ "BriefDescription": "CBox AD Credits Empty; VNA Messages",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV",
+ "BriefDescription": "CBox AD Credits Empty; Writebacks",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0",
+ "BriefDescription": "Number of uclks in domain",
+ "EventCode": "0x1",
+ "EventName": "UNC_M3UPI_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xC0",
+ "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0",
+ "BriefDescription": "D2C Sent",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M3UPI_D2C_SENT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Count cases BL sends direct to core",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1",
+ "BriefDescription": "D2U Sent",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M3UPI_D2U_SENT",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Cases where SMI3 sends D2U command",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0",
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+ "EventCode": "0xAE",
+ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1",
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+ "EventCode": "0xAE",
+ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "FaST wire asserted; Horizontal",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "FaST wire asserted; Vertical",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Down",
- "Counter": "0,1,2,3",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x40",
- "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI",
+ "BriefDescription": "Horizontal IV Ring in Use; Left",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+ "BriefDescription": "Horizontal IV Ring in Use; Right",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+ "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
+ "BriefDescription": "M2 BL Credits Empty; IIO2",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
+ "BriefDescription": "M2 BL Credits Empty; IIO3",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.IV",
+ "BriefDescription": "M2 BL Credits Empty; IIO4",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.IV",
+ "BriefDescription": "M2 BL Credits Empty; IIO5",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
+ "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
+ "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
+ "BriefDescription": "Multi Slot Flit Received; AD - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+ "BriefDescription": "Multi Slot Flit Received; AD - Slot 1",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+ "BriefDescription": "Multi Slot Flit Received; AD - Slot 2",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+ "BriefDescription": "Multi Slot Flit Received; AK - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0",
+ "BriefDescription": "Multi Slot Flit Received; AK - Slot 2",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1",
+ "BriefDescription": "Multi Slot Flit Received; BL - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "FaST wire asserted; Vertical",
- "Counter": "0,1,2,3",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_FAST_ASSERTED.VERT",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "FaST wire asserted; Horizontal",
- "Counter": "0,1,2,3",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_FAST_ASSERTED.HORZ",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x88",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x90",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+ "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0xA0",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+ "BriefDescription": "Lost Arb for VN0; REQ on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+ "BriefDescription": "Lost Arb for VN0; RSP on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+ "BriefDescription": "Lost Arb for VN0; SNP on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+ "BriefDescription": "Lost Arb for VN0; NCB on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+ "BriefDescription": "Lost Arb for VN0; NCS on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+ "BriefDescription": "Lost Arb for VN0; RSP on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+ "BriefDescription": "Lost Arb for VN0; WB on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+ "BriefDescription": "Lost Arb for VN1; REQ on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+ "BriefDescription": "Lost Arb for VN1; RSP on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+ "BriefDescription": "Lost Arb for VN1; SNP on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+ "BriefDescription": "Lost Arb for VN1; NCB on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+ "BriefDescription": "Lost Arb for VN1; NCS on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+ "BriefDescription": "Lost Arb for VN1; RSP on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+ "BriefDescription": "Lost Arb for VN1; WB on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+ "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+ "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Sideband",
- "Counter": "0,1,2,3",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD",
+ "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Sideband",
- "Counter": "0,1,2,3",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR",
+ "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VNA",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+ "PerPkg": "1",
+ "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0",
"PerPkg": "1",
+ "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
+ "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1",
"PerPkg": "1",
+ "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
+ "BriefDescription": "Can't Arb for VN0; REQ on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
+ "BriefDescription": "Can't Arb for VN0; RSP on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
+ "BriefDescription": "Can't Arb for VN0; SNP on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
+ "BriefDescription": "Can't Arb for VN0; NCB on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
+ "BriefDescription": "Can't Arb for VN0; NCS on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
+ "BriefDescription": "Can't Arb for VN0; RSP on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
+ "BriefDescription": "Can't Arb for VN0; WB on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+ "BriefDescription": "Can't Arb for VN1; REQ on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0",
+ "BriefDescription": "Can't Arb for VN1; RSP on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1",
+ "BriefDescription": "Can't Arb for VN1; SNP on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP",
"PerPkg": "1",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0",
+ "BriefDescription": "Can't Arb for VN1; NCB on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1",
+ "BriefDescription": "Can't Arb for VN1; NCS on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CBox AD Credits Empty; VNA Messages",
- "Counter": "0,1,2",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Can't Arb for VN1; RSP on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CBox AD Credits Empty; Writebacks",
- "Counter": "0,1,2",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+ "BriefDescription": "Can't Arb for VN1; WB on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CBox AD Credits Empty; Requests",
- "Counter": "0,1,2",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
+ "BriefDescription": "No Credits to Arb for VN0; REQ on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CBox AD Credits Empty; Snoops",
- "Counter": "0,1,2",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
+ "BriefDescription": "No Credits to Arb for VN0; RSP on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2",
- "EventCode": "0x1",
- "EventName": "UNC_M3UPI_CLOCKTICKS",
+ "BriefDescription": "No Credits to Arb for VN0; SNP on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP",
"PerPkg": "1",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "D2U Sent",
- "Counter": "0,1,2",
- "EventCode": "0x2A",
- "EventName": "UNC_M3UPI_D2U_SENT",
+ "BriefDescription": "No Credits to Arb for VN0; NCB on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB",
+ "BriefDescription": "No Credits to Arb for VN0; NCS on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO2",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+ "BriefDescription": "No Credits to Arb for VN0; RSP on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO3",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+ "BriefDescription": "No Credits to Arb for VN0; WB on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO4",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+ "BriefDescription": "No Credits to Arb for VN1; REQ on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO5",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+ "BriefDescription": "No Credits to Arb for VN1; RSP on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+ "BriefDescription": "No Credits to Arb for VN1; SNP on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+ "BriefDescription": "No Credits to Arb for VN1; NCB on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AD - Slot 0",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+ "BriefDescription": "No Credits to Arb for VN1; NCS on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AD - Slot 1",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+ "BriefDescription": "No Credits to Arb for VN1; RSP on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AD - Slot 2",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+ "BriefDescription": "No Credits to Arb for VN1; WB on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; BL - Slot 0",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+ "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AK - Slot 0",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+ "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AK - Slot 2",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+ "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
+ "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
+ "BriefDescription": "VN0 message lost contest for flit; REQ on AD",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
+ "BriefDescription": "VN0 message lost contest for flit; RSP on AD",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
+ "BriefDescription": "VN0 message lost contest for flit; SNP on AD",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
+ "BriefDescription": "VN0 message lost contest for flit; NCB on BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+ "BriefDescription": "VN0 message lost contest for flit; NCS on BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
+ "BriefDescription": "VN0 message lost contest for flit; RSP on BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
+ "BriefDescription": "VN0 message lost contest for flit; WB on BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
+ "BriefDescription": "VN1 message lost contest for flit; REQ on AD",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
+ "BriefDescription": "VN1 message lost contest for flit; RSP on AD",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
+ "BriefDescription": "VN1 message lost contest for flit; SNP on AD",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
+ "BriefDescription": "VN1 message lost contest for flit; NCB on BL",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
+ "BriefDescription": "VN1 message lost contest for flit; NCS on BL",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
+ "BriefDescription": "VN1 message lost contest for flit; RSP on BL",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
+ "BriefDescription": "VN1 message lost contest for flit; WB on BL",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
+ "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
+ "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
+ "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
+ "BriefDescription": "Credit Occupancy; D2K Credits",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
+ "BriefDescription": "Credit Occupancy; Packets in BGF FIFO",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
+ "BriefDescription": "Credit Occupancy; Packets in BGF Path",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
+ "BriefDescription": "Credit Occupancy",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
+ "BriefDescription": "Credit Occupancy",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
+ "BriefDescription": "Credit Occupancy; Transmit Credits",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
+ "BriefDescription": "Credit Occupancy; VNA In Use",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB",
+ "BriefDescription": "Data Flit Not Sent; All",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Data flit is ready for transmission but could not be sent",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ",
+ "BriefDescription": "Data Flit Not Sent; No BGF Credits",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Data flit is ready for transmission but could not be sent",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP",
+ "BriefDescription": "Data Flit Not Sent; No TxQ Credits",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Data flit is ready for transmission but could not be sent",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB",
+ "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "generating bl data flit sequence; waiting for data pump 0",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
"PerPkg": "1",
+ "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "pump-1-pending logic is tracking at least one message",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "pump-1-pending completion fifo is full",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
+ "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "generating bl data flit sequence; waiting for data pump 1",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ",
+ "BriefDescription": "Sent Header Flit; One Message",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "One message in flit; VNA or non-VNA flit",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP",
+ "BriefDescription": "Sent Header Flit; One Message in non-VNA",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "One message in flit; non-VNA flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+ "BriefDescription": "Sent Header Flit; Two Messages",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Two messages in flit; VNA flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
+ "BriefDescription": "Sent Header Flit; Three Messages",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Three messages in flit; VNA flit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AK Flow Q Inserts",
- "Counter": "0,1,2",
- "EventCode": "0x2F",
- "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
+ "BriefDescription": "Sent Header Flit",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1",
"PerPkg": "1",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AK Flow Q Occupancy",
- "EventCode": "0x1E",
- "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
+ "BriefDescription": "Sent Header Flit",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2",
"PerPkg": "1",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
+ "BriefDescription": "Sent Header Flit",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
+ "BriefDescription": "Slotting BL Message Into Header Flit; All",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN0 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL message requires data flit sequence",
+ "UMask": "0x2",
"Unit": "M3UPI"
- },
- {
- "BriefDescription": "Failed ARB for BL; VN0 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
+ },
+ {
+ "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Waiting for header pump 0",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
"PerPkg": "1",
+ "PublicDescription": "Header pump 1 is not required for flit",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
"PerPkg": "1",
+ "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN1 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
"PerPkg": "1",
+ "PublicDescription": "Header pump 1 is not required for flit and not available",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN1 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Waiting for header pump 1",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
+ "BriefDescription": "Flit Gen - Header 1; Acumullate",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
+ "BriefDescription": "Flit Gen - Header 1; Accumulate Ready",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
+ "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
+ "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
+ "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG",
"PerPkg": "1",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
+ "BriefDescription": "Flit Gen - Header 1; Parallel Ok",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR",
"PerPkg": "1",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
+ "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
+ "BriefDescription": "Flit Gen - Header 1; Parallel Message",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
+ "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
+ "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
+ "BriefDescription": "Header Not Sent; All",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "header flit is ready for transmission but could not be sent",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
+ "BriefDescription": "Header Not Sent; No BGF Credits",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
+ "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
+ "BriefDescription": "Header Not Sent; No TxQ Credits",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
+ "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
"PerPkg": "1",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
+ "BriefDescription": "Header Not Sent; Sent - One Slot Taken",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN",
"PerPkg": "1",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
+ "BriefDescription": "Header Not Sent; Sent - Three Slots Taken",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
+ "BriefDescription": "Header Not Sent; Sent - Two Slots Taken",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
+ "BriefDescription": "Message Held; Can't Slot AD",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
+ "BriefDescription": "Message Held; Can't Slot BL",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
+ "BriefDescription": "Message Held; Parallel AD Lost",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST",
"PerPkg": "1",
+ "PublicDescription": "some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
+ "BriefDescription": "Message Held; Parallel Attempt",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+ "PerPkg": "1",
+ "PublicDescription": "ad and bl messages attempted to slot into the same flit in parallel",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Message Held; Parallel BL Lost",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST",
"PerPkg": "1",
+ "PublicDescription": "some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
+ "BriefDescription": "Message Held; Parallel Success",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
+ "BriefDescription": "Message Held; VN0",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB",
+ "BriefDescription": "Message Held; VN1",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.VN1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
+ "BriefDescription": "VN0 message can't slot into flit; REQ on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+ "BriefDescription": "VN0 message can't slot into flit; RSP on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
+ "BriefDescription": "VN0 message can't slot into flit; SNP on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
+ "BriefDescription": "VN0 message can't slot into flit; NCB on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
+ "BriefDescription": "VN0 message can't slot into flit; NCS on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
+ "BriefDescription": "VN0 message can't slot into flit; RSP on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
+ "BriefDescription": "VN0 message can't slot into flit; WB on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
+ "BriefDescription": "VN1 message can't slot into flit; REQ on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
+ "BriefDescription": "VN1 message can't slot into flit; RSP on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; CHA on VN0",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA",
+ "BriefDescription": "VN1 message can't slot into flit; SNP on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; CHA on VN1",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA",
+ "BriefDescription": "VN1 message can't slot into flit; NCB on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE",
+ "BriefDescription": "VN1 message can't slot into flit; NCS on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE",
+ "BriefDescription": "VN1 message can't slot into flit; RSP on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+ "PerPkg": "1",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "VN1 message can't slot into flit; WB on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Snoop Arbitration; FlowQ Won",
- "Counter": "0,1,2",
- "EventCode": "0x3D",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP",
+ "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Snoop Arbitration; FlowQ Won",
- "Counter": "0,1,2",
- "EventCode": "0x3D",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP",
+ "BriefDescription": "SMI3 Prefetch Messages; Arrived",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
- "Counter": "0,1,2",
- "EventCode": "0x3D",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP",
+ "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
- "Counter": "0,1,2",
- "EventCode": "0x3D",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP",
+ "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "SMI3 Prefetch Messages; Slotted",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "Remote VNA Credits; Any In Use",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "At least one remote vna credit is in use",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Remote VNA Credits; Corrected",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of remote vna credits corrected (local return) per cycle",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Remote VNA Credits; Level < 1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "Remote VNA Credits; Level < 4",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Remote VNA Credits; Level < 5",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Remote VNA Credits; Used",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of remote vna credits consumed per cycle",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2",
- "EventCode": "0xC0",
- "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
- "Counter": "0,1,2",
- "EventCode": "0xAE",
- "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
- "Counter": "0,1,2",
- "EventCode": "0xAE",
- "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA9",
- "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA9",
- "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA9",
- "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA9",
- "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
- "Counter": "0,1,2",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Failed ARB for AD; VN0 REQ Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
- "Counter": "0,1,2",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Failed ARB for AD; VN0 RSP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Failed ARB for AD; VN0 SNP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Left",
- "Counter": "0,1,2",
- "EventCode": "0xAD",
- "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Failed ARB for AD; VN0 WB Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Right",
- "Counter": "0,1,2",
- "EventCode": "0xAD",
- "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Failed ARB for AD; VN1 REQ Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
- "Counter": "0,1,2",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Failed ARB for AD; VN1 RSP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
- "Counter": "0,1,2",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Failed ARB for AD; VN1 SNP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+ "PerPkg": "1",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Failed ARB for AD; VN1 WB Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
- "Counter": "0,1,2",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
- "Counter": "0,1,2",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
- "Counter": "0,1,2",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
- "Counter": "0,1,2",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
- "Counter": "0,1,2",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
- "Counter": "0,1,2",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; AD",
- "Counter": "0,1,2",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
- "Counter": "0,1,2",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
- "Counter": "0,1,2",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
- "Counter": "0,1,2",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_RING_SRC_THRTL",
+ "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
+ "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
+ "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
+ "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
+ "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
+ "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
+ "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
+ "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
+ "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
+ "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
+ "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
+ "BriefDescription": "Number of Snoop Targets; CHA on VN0",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
+ "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
+ "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
+ "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0",
+ "BriefDescription": "Number of Snoop Targets; CHA on VN1",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1",
+ "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
+ "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
+ "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
+ "BriefDescription": "Snoop Arbitration; FlowQ Won",
+ "EventCode": "0x3D",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+ "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
+ "EventCode": "0x3D",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN",
+ "BriefDescription": "Snoop Arbitration; FlowQ Won",
+ "EventCode": "0x3D",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ",
+ "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
+ "EventCode": "0x3D",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ",
"PerPkg": "1",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ",
+ "BriefDescription": "AK Flow Q Inserts",
+ "EventCode": "0x2F",
+ "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP",
+ "BriefDescription": "AK Flow Q Occupancy",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP",
+ "BriefDescription": "Failed ARB for BL; VN0 NCB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP",
+ "BriefDescription": "Failed ARB for BL; VN0 NCS Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB",
+ "BriefDescription": "Failed ARB for BL; VN0 RSP Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB",
+ "BriefDescription": "Failed ARB for BL; VN0 WB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS",
+ "BriefDescription": "Failed ARB for BL; VN1 NCS Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
"PerPkg": "1",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle",
- "Counter": "0,1,2",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
+ "BriefDescription": "Failed ARB for BL; VN1 NCB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb",
- "Counter": "0,1,2",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
+ "BriefDescription": "Failed ARB for BL; VN1 RSP Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1",
- "Counter": "0,1,2",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
+ "BriefDescription": "Failed ARB for BL; VN1 WB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2",
- "Counter": "0,1,2",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
+ "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ",
+ "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP",
+ "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP",
+ "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP",
+ "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB",
+ "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB",
+ "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS",
+ "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ",
+ "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP",
+ "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP",
+ "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP",
+ "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB",
+ "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB",
+ "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS",
+ "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO",
- "Counter": "0,1,2",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
+ "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path",
- "Counter": "0,1,2",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
+ "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb",
- "Counter": "0,1,2",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB",
+ "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; VNA In Use",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
+ "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; Packets in BGF FIFO",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
+ "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; Packets in BGF Path",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+ "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; Transmit Credits",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
+ "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; D2K Credits",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
+ "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
+ "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB",
"PerPkg": "1",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
"PerPkg": "1",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
"PerPkg": "1",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Data Flit Not Sent; All",
- "Counter": "0,1,2",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL",
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Data Flit Not Sent; No BGF Credits",
- "Counter": "0,1,2",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF",
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Data Flit Not Sent; No TxQ Credits",
- "Counter": "0,1,2",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ",
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
+ "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
+ "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC",
- "Counter": "0,1,2",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sent Header Flit; One Message",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sent Header Flit; Two Messages",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sent Header Flit; Three Messages",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sent Header Flit; One Message in non-VNA",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; All",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Acumullate",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Accumulate Ready",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG",
+ "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Parallel Ok",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Parallel Message",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall",
- "Counter": "0,1,2",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message",
- "Counter": "0,1,2",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; All",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL",
+ "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; No BGF Credits",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; No TxQ Credits",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
- {
- "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG",
+ {
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; Sent - One Slot Taken",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; Sent - Two Slots Taken",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; Sent - Three Slots Taken",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; VN0",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.VN0",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; VN1",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.VN1",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Parallel Attempt",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Parallel Success",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Parallel AD Lost",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Parallel BL Lost",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Can't Slot AD",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Can't Slot BL",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
+ "BriefDescription": "CMS Vertical ADS Used; IV",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
+ "BriefDescription": "CMS Vert Egress Allocations; IV",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
+ "BriefDescription": "CMS Vertical Egress NACKs; IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Arrived",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED",
+ "BriefDescription": "CMS Vert Egress Occupancy; IV",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Slotted",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Used",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Corrected",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Level < 1",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Level < 4",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
+ "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Level < 5",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
+ "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Any In Use",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
+ "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC",
+ "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC",
+ "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "UPI0 AD Credits Empty; VNA",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC",
+ "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC",
+ "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC",
+ "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC",
+ "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
- },
- {
- "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC",
+ "BriefDescription": "UPI0 BL Credits Empty; VNA",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC",
+ "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.",
+ "EventCode": "0x29",
+ "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC",
+ "BriefDescription": "Vertical IV Ring in Use; Down",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC",
+ "BriefDescription": "Vertical IV Ring in Use; Up",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "VN0 Credit Used; WB on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "VN0 Credit Used; NCB on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "VN0 Credit Used; REQ on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "VN0 Credit Used; RSP on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "VN0 Credit Used; SNP on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "VN0 Credit Used; RSP on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "VN0 No Credits; WB on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "VN0 No Credits; NCB on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "VN0 No Credits; REQ on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "VN0 No Credits; RSP on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "VN0 No Credits; SNP on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "VN0 No Credits; RSP on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "VN1 Credit Used; WB on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "VN1 Credit Used; NCB on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "VN1 Credit Used; REQ on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "VN1 Credit Used; RSP on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "VN1 Credit Used; SNP on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "VN1 Credit Used; RSP on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "VN1 No Credits; WB on BL",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "VN1 No Credits; NCB on BL",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "VN1 No Credits; REQ on AD",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "VN1 No Credits; RSP on AD",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "VN1 No Credits; SNP on AD",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "VN1 No Credits; RSP on BL",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI",
+ "Deprecated": "1",
+ "EventCode": "0x40",
+ "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)",
+ "EventCode": "0x1",
+ "EventName": "UNC_UPI_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC",
+ "BriefDescription": "Data Response packets that go direct to core",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U",
+ "Deprecated": "1",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC",
+ "BriefDescription": "Data Response packets that go direct to Intel UPI",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA .",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)",
+ "EventCode": "0x21",
+ "EventName": "UNC_UPI_L1_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC",
+ "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "EventCode": "0x16",
+ "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC",
+ "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
+ "EventCode": "0x20",
+ "EventName": "UNC_UPI_PHY_INIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC",
+ "BriefDescription": "L1 Req Nack",
+ "EventCode": "0x23",
+ "EventName": "UNC_UPI_POWER_L1_NACK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "L1 Req (same as L1 Ack).",
+ "EventCode": "0x22",
+ "EventName": "UNC_UPI_POWER_L1_REQ",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC",
+ "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode",
+ "EventCode": "0x25",
+ "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "Cycles in L0. Receive side.",
+ "EventCode": "0x24",
+ "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCB",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCB",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCS",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCS",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Request",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "REQ Message Class",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]",
+ "UMask": "0x108",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x1aa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x12a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0x10c",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - RSP",
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - RSP",
+ "UMask": "0x10a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Snoop",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "SNP Message Class",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]",
+ "UMask": "0x109",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0x10d",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "CRC Errors Detected",
+ "EventCode": "0xB",
+ "EventName": "UNC_UPI_RxL_CRC_ERRORS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; IV",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV",
+ "BriefDescription": "LLR Requests Sent",
+ "EventCode": "0x8",
+ "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "VN0 Credit Consumed",
+ "EventCode": "0x39",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "VN1 Credit Consumed",
+ "EventCode": "0x3A",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "VNA Credit Consumed",
+ "EventCode": "0x38",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0",
+ "BriefDescription": "Valid data FLITs received from any slot",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0",
+ "BriefDescription": "Null FLITs received from any slot",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0",
+ "BriefDescription": "Valid Flits Received; Data",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV",
+ "BriefDescription": "Valid Flits Received; Idle",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1",
+ "BriefDescription": "Valid Flits Received; LLCRD Not Empty",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
"PerPkg": "1",
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1",
+ "BriefDescription": "Valid Flits Received; LLCTRL",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1",
+ "BriefDescription": "Protocol header and credit FLITs received from any slot",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL",
+ "Deprecated": "1",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0",
+ "BriefDescription": "Valid Flits Received; Protocol Header",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR",
+ "Deprecated": "1",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV",
+ "BriefDescription": "Valid Flits Received; Slot 0",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1",
+ "BriefDescription": "Valid Flits Received; Slot 1",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1",
+ "BriefDescription": "Valid Flits Received; Slot 2",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; IV",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP",
+ "PerPkg": "1",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0xb",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1",
+ "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1",
+ "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1",
+ "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0",
+ "BriefDescription": "RxQ Occupancy - All Packets; Slot 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0",
+ "BriefDescription": "RxQ Occupancy - All Packets; Slot 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0",
+ "BriefDescription": "RxQ Occupancy - All Packets; Slot 2",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; IV",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
"PerPkg": "1",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1",
+ "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode",
+ "EventCode": "0x27",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "EventCode": "0x28",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "EventCode": "0x29",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "Cycles in L0. Transmit side.",
+ "EventCode": "0x26",
+ "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCB",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCB",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA8",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCS",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA8",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCS",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA8",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Request",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "REQ Message Class",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA8",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]",
+ "UMask": "0x108",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Even",
- "Counter": "0,1,2",
- "EventCode": "0xAA",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x1aa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xAA",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x12a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Even",
- "Counter": "0,1,2",
- "EventCode": "0xAA",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xAA",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0x10c",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Up",
- "Counter": "0,1,2",
- "EventCode": "0xAC",
- "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - RSP",
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Down",
- "Counter": "0,1,2",
- "EventCode": "0xAC",
- "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - RSP",
+ "UMask": "0x10a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "D2C Sent",
- "Counter": "0,1,2",
- "EventCode": "0x2B",
- "EventName": "UNC_M3UPI_D2C_SENT",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
- "Unit": "M3UPI"
+ "PublicDescription": "SNP Message Class",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "FaST wire asserted; Vertical",
- "Counter": "0,1,2",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]",
+ "UMask": "0x109",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "FaST wire asserted; Horizontal",
- "Counter": "0,1,2",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Sent Header Flit",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0x10d",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Sent Header Flit",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2",
+ "BriefDescription": "FLITs that bypassed the TxL Buffer",
+ "EventCode": "0x41",
+ "EventName": "UNC_UPI_TxL_BYPASSED",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Sent Header Flit",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3",
+ "BriefDescription": "Valid data FLITs transmitted via any slot",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; IV",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV",
+ "BriefDescription": "Null FLITs transmitted from any slot",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit.",
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV",
+ "BriefDescription": "Valid Flits Sent; Data",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VNA",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Idle FLITs transmitted",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
+ "BriefDescription": "Valid Flits Sent; LLCRD Not Empty",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
+ "BriefDescription": "Valid Flits Sent; LLCTRL",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
+ "BriefDescription": "Protocol header and credit FLITs transmitted across any slot",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received; VLW",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL",
+ "Deprecated": "1",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UBOX"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received; MSI",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+ "BriefDescription": "Valid Flits Sent; Protocol Header",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UBOX"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received; IPI",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR",
+ "Deprecated": "1",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UBOX"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+ "BriefDescription": "Valid Flits Sent; Slot 0",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UBOX"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+ "BriefDescription": "Valid Flits Sent; Slot 1",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UBOX"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "IDI Lock/SplitLock Cycles",
- "Counter": "0,1",
- "EventCode": "0x44",
- "EventName": "UNC_U_LOCK_CYCLES",
+ "BriefDescription": "Valid Flits Sent; Slot 2",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
"PerPkg": "1",
- "Unit": "UBOX"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
- "Counter": "0,1",
- "EventCode": "0x45",
- "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UBOX"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
- "Counter": "0,1",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDRAND",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UBOX"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
- "Counter": "0,1",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDSEED",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UBOX"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
- "Counter": "0,1",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UBOX"
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "RACU Request",
- "Counter": "0,1",
- "EventCode": "0x46",
- "EventName": "UNC_U_RACU_REQUESTS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS",
"PerPkg": "1",
- "Unit": "UBOX"
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
- "Counter": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_U_CLOCKTICKS",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR",
"PerPkg": "1",
- "Unit": "UBOX"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x33",
- "EventName": "UNC_H_CORE_SNP.CORE_GTONE",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.REM",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
- "UMask": "0x42",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
"Deprecated": "1",
- "EventCode": "0x33",
- "EventName": "UNC_H_CORE_SNP.EVICT_GTONE",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
- "UMask": "0x82",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
"Deprecated": "1",
- "EventCode": "0x53",
- "EventName": "UNC_H_DIR_LOOKUP.NO_SNP",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
- "UMask": "0x2",
- "Unit": "CHA"
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
"Deprecated": "1",
- "EventCode": "0x53",
- "EventName": "UNC_H_DIR_LOOKUP.SNP",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
- "UMask": "0x1",
- "Unit": "CHA"
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x54",
- "EventName": "UNC_H_DIR_UPDATE.HA",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
- "UMask": "0x1",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
"Deprecated": "1",
- "EventCode": "0x54",
- "EventName": "UNC_H_DIR_UPDATE.TOR",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
- "UMask": "0x2",
- "Unit": "CHA"
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
"Deprecated": "1",
- "EventCode": "0x5F",
- "EventName": "UNC_H_HITME_HIT.EX_RDS",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.WB",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
- "UMask": "0x1",
- "Unit": "CHA"
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x39",
- "EventName": "UNC_H_MISC.RFO_HIT_S",
+ "BriefDescription": "Tx Flit Buffer Allocations",
+ "EventCode": "0x40",
+ "EventName": "UNC_UPI_TxL_INSERTS",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
- "UMask": "0x8",
- "Unit": "CHA"
+ "PublicDescription": "Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
+ "BriefDescription": "Tx Flit Buffer Occupancy",
+ "EventCode": "0x42",
+ "EventName": "UNC_UPI_TxL_OCCUPANCY",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+ "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "EventCode": "0x45",
+ "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
- "UMask": "0x20",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.READS",
+ "BriefDescription": "VNA Credits Pending Return - Occupancy",
+ "EventCode": "0x44",
+ "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS",
- "UMask": "0x3",
- "Unit": "CHA"
+ "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.READS_LOCAL",
+ "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+ "EventCode": "0xff",
+ "EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL",
- "UMask": "0x1",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.WRITES",
+ "BriefDescription": "Message Received",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES",
- "UMask": "0xC",
- "Unit": "CHA"
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
+ "UMask": "0x8",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
+ "BriefDescription": "Message Received",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+ "PerPkg": "1",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
+ "UMask": "0x10",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "Message Received; IPI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts",
"UMask": "0x4",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x13",
- "EventName": "UNC_H_RxC_INSERTS.IRQ",
+ "BriefDescription": "Message Received; MSI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+ "PerPkg": "1",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
+ "UMask": "0x2",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "Message Received; VLW",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
"UMask": "0x1",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x19",
- "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "IDI Lock/SplitLock Cycles",
+ "EventCode": "0x44",
+ "EventName": "UNC_U_LOCK_CYCLES",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
- "Deprecated": "1",
- "EventCode": "0x11",
- "EventName": "UNC_H_RxC_OCCUPANCY.IRQ",
+ "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+ "EventCode": "0x45",
+ "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "PublicDescription": "PHOLD cycles.",
"UMask": "0x1",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+ "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
"UMask": "0x4",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+ "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDRAND",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
- "UMask": "0x8",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+ "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDSEED",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "RACU Request",
+ "EventCode": "0x46",
+ "EventName": "UNC_U_RACU_REQUESTS",
+ "PerPkg": "1",
+ "PublicDescription": "Number outstanding register requests within message channel tracker",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
+ "EventCode": "0x2",
+ "EventName": "UPI_DATA_BANDWIDTH_TX",
+ "PerPkg": "1",
+ "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.",
+ "ScaleUnit": "7.11E-06Bytes",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json
index 64301a600ede..8e21dc3eff16 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json
@@ -1,14 +1,13 @@
[
{
"BriefDescription": "pclk Cycles",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -16,7 +15,6 @@
},
{
"BriefDescription": "UNC_P_DEMOTIONS",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS",
"PerPkg": "1",
@@ -24,71 +22,70 @@
},
{
"BriefDescription": "Phase Shed 0 Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent in phase-shedding power state 0",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 1 Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent in phase-shedding power state 1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 2 Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent in phase-shedding power state 2",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 3 Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent in phase-shedding power state 3",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_MCP_PROCHOT_CYCLES",
"PerPkg": "1",
@@ -96,47 +93,46 @@
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
"PerPkg": "1",
@@ -144,55 +140,54 @@
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C3",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json
index dd334b416c57..f59405877ae8 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 1G page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 4K page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@@ -102,8 +82,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@@ -113,8 +91,6 @@
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -123,8 +99,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 1G page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -133,8 +107,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -143,8 +115,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 4K page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -153,8 +123,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -163,8 +131,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4f",
"EventName": "EPT.WALK_PENDING",
"PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
@@ -173,8 +139,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -183,8 +147,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
@@ -193,8 +155,6 @@
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -202,8 +162,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
@@ -213,8 +171,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -223,8 +179,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -233,8 +187,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -243,8 +195,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -253,8 +203,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
@@ -263,8 +211,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -273,8 +219,6 @@
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 28/32] perf vendor events intel: Refresh snowridgex events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (17 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 27/32] perf vendor events intel: Refresh skylakex " Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 29/32] perf vendor events intel: Refresh tigerlake metrics and events Ian Rogers
` (3 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the snowridgex events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed and
descriptions improved. This increases consistency across the json
files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/snowridgex/cache.json | 252 -
.../arch/x86/snowridgex/floating-point.json | 11 -
.../arch/x86/snowridgex/frontend.json | 36 -
.../arch/x86/snowridgex/memory.json | 84 -
.../pmu-events/arch/x86/snowridgex/other.json | 143 -
.../arch/x86/snowridgex/pipeline.json | 213 -
.../arch/x86/snowridgex/uncore-memory.json | 624 +-
.../arch/x86/snowridgex/uncore-other.json | 26334 +++++++---------
.../arch/x86/snowridgex/uncore-power.json | 114 +-
.../arch/x86/snowridgex/virtual-memory.json | 117 -
10 files changed, 11934 insertions(+), 15994 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json b/tools/perf/pmu-events/arch/x86/snowridgex/cache.json
index d674ee88c3a5..0ab90e3bf76b 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/cache.json
@@ -1,1137 +1,885 @@
[
{
"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "DL1.DIRTY_EVICTION",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "L2_REJECT_XQ.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.REJECTS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x4f"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x38"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x7"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a store buffer being full.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of load uops retired that miss in the L1 data cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of load uops retired that miss in the L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of memory uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)",
"SampleAfterValue": "200003",
"UMask": "0x83"
},
{
"BriefDescription": "Counts the number of load uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of load uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x81"
},
{
"BriefDescription": "Counts the number of store uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of store uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x82"
},
{
"BriefDescription": "Counts the number of load uops retired that performed one or more locks.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x21"
},
{
"BriefDescription": "Counts the number of memory uops retired that were splits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x43"
},
{
"BriefDescription": "Counts the number of retired split load uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "Counts the number of retired split store uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x42"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3001F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x401F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x101F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001003C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x201F803C0000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ICACHE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x20"
}
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json
index 2e1b80c714fd..88522244b760 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json
@@ -1,36 +1,25 @@
[
{
"BriefDescription": "Counts the number of cycles the floating point divider is busy.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcd",
"EventName": "CYCLES_DIV_BUSY.FPDIV",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the floating point divider is busy. Does not imply a stall waiting for the divider.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
"SampleAfterValue": "20003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x8"
}
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json b/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json
index 5d938a5dafcf..5ba998e06592 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json
@@ -1,103 +1,67 @@
[
{
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.COND",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of BACLEARS due to an indirect branch.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.INDIRECT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of BACLEARS due to a return branch.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.RETURN",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.UNCOND",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe9",
"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts the number of instruction cache hits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of requests that hit in the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of instruction cache misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json b/tools/perf/pmu-events/arch/x86/snowridgex/memory.json
index 15eba23796e4..18621909d1a9 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/memory.json
@@ -1,441 +1,357 @@
[
{
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.OTHER.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.OTHER.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x402184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x402184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PREFETCHES.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000470",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x102184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x102184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x202184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x202184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/other.json b/tools/perf/pmu-events/arch/x86/snowridgex/other.json
index 4a1b7cc5aa23..00ae180ded25 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/other.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/other.json
@@ -1,674 +1,531 @@
[
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EdgeDetect": "1",
"EventCode": "0x63",
"EventName": "BUS_LOCK.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.BLOCK_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.CYCLES_SELF_BLOCK",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.LOCK_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EdgeDetect": "1",
"EventCode": "0x63",
"EventName": "BUS_LOCK.SELF_LOCKS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "C0_STALLS.LOAD_DRAM_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "C0_STALLS.LOAD_L2_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "C0_STALLS.LOAD_LLC_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of core cycles during which interrupts are masked (disabled).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcb",
"EventName": "HW_INTERRUPTS.MASKED",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcb",
"EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of hardware interrupts received by the processor.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcb",
"EventName": "HW_INTERRUPTS.RECEIVED",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "203",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000044",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3000000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8003000000000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all hardware and software prefetches that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PREFETCHES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10470",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100184000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000100000000000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200000010000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json b/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json
index 09919fdb9a38..9dd8c909facc 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json
@@ -1,662 +1,449 @@
[
{
"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of near CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xf9"
},
{
"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xbf"
},
{
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.JCC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfd"
},
{
"BriefDescription": "Counts the number of near RET branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.RETURN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.JCC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Counts the total number of BTCLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe8",
"EventName": "BTCLEAR.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "34",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcd",
"EventName": "CYCLES_DIV_BUSY.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of cycles the integer divider is busy.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xcd",
"EventName": "CYCLES_DIV_BUSY.IDIV",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the total number of instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.4K_ALIAS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003"
},
{
"BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.PAGE_FAULT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "This event is deprecated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ALL",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.CISC",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.DECODE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ITLB",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.OTHER",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the total number of consumed retirement slots.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "TOPDOWN_RETIRING.ALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of uops issued by the front end every cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the total number of uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of integer divide uops retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.IDIV",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.X87",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x2"
}
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json
index f2c17f19299f..7dc0910694ed 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json
@@ -1,619 +1,545 @@
[
- {
- "BriefDescription": "Pre-charge for reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.RD",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Pre-charge for writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.WR",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "iMC"
- },
{
"BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "LLC_MISSES.MEM_READ",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills.",
"ScaleUnit": "64Bytes",
- "UMask": "0x0f",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "read requests to memory controller",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
"EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD",
+ "EventName": "LLC_MISSES.MEM_WRITE",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
"ScaleUnit": "64Bytes",
- "UMask": "0x0f",
+ "UMask": "0x30",
"Unit": "iMC"
},
{
- "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "LLC_MISSES.MEM_WRITE",
+ "BriefDescription": "DRAM Activate Count : All Activates",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_ACT_COUNT.ALL",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x30",
+ "PublicDescription": "DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "write requests to memory controller",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.WR",
+ "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x30",
+ "PublicDescription": "DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "All DRAM CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
"UMask": "0x3f",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
+ "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills.",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with explicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS.PCH0",
+ "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the total number of DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS.PCH1",
+ "BriefDescription": "DRAM underfill read CAS commands issued",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the total of DRAM Read CAS commands issued due to an underfill",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS.PCH0",
+ "BriefDescription": "All DRAM write CAS commands issued",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
+ "UMask": "0x30",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS.PCH1",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.PGT",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.WR_PRE",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Memory controller clock ticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Clockticks of the integrated memory controller (IMC)",
"Unit": "iMC"
},
{
- "BriefDescription": "Half clockticks for IMC",
- "Counter": "FIXED",
- "CounterType": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_M_HCLOCKTICKS",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
+ "BriefDescription": "Free running counter that increments for the Memory Controller",
+ "EventName": "UNC_M_CLOCKTICKS_FREERUN",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_CLOCKTICKS_FREERUN",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
+ "BriefDescription": "DRAM Precharge All Commands",
+ "EventCode": "0x44",
+ "EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
+ "PublicDescription": "DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent.",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count : All Activates",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M_ACT_COUNT.ALL",
+ "BriefDescription": "Number of DRAM Refreshes Issued",
+ "EventCode": "0x45",
+ "EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
- "UMask": "0x0B",
+ "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.ALL",
+ "BriefDescription": "Number of DRAM Refreshes Issued",
+ "EventCode": "0x45",
+ "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
"PerPkg": "1",
- "UMask": "0x1C",
+ "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M_RDB_INSERTS",
+ "BriefDescription": "Number of DRAM Refreshes Issued",
+ "EventCode": "0x45",
+ "EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
+ "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_REG",
+ "BriefDescription": "Half clockticks for IMC",
+ "EventCode": "0xff",
+ "EventName": "UNC_M_HCLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM underfill read CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "BriefDescription": "UNC_M_PARITY_ERRORS",
+ "EventCode": "0x2c",
+ "EventName": "UNC_M_PARITY_ERRORS",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M_ACT_COUNT.BYP",
+ "BriefDescription": "UNC_M_PCLS.RD",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_PCLS.RD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
+ "BriefDescription": "UNC_M_PCLS.TOTAL",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_PCLS.TOTAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
+ "BriefDescription": "UNC_M_PCLS.WR",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_PCLS.WR",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.WR_PRE",
+ "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
+ "EventCode": "0x85",
+ "EventName": "UNC_M_POWER_CHANNEL_PPD",
+ "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100",
+ "MetricName": "power_channel_ppd",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Cycles Memory is in self refresh power mode",
+ "EventCode": "0x43",
+ "EventName": "UNC_M_POWER_SELF_REFRESH",
+ "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100",
+ "MetricName": "power_self_refresh",
+ "PerPkg": "1",
+ "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x46",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x46",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
+ "BriefDescription": "DRAM Precharge commands.",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x1c",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
+ "BriefDescription": "Pre-charges due to page misses",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests)",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.PGT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
+ "BriefDescription": "Pre-charge for reads",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
+ "BriefDescription": "Pre-charge for writes",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
+ "BriefDescription": "Read Data Buffer Full",
+ "EventCode": "0x19",
+ "EventName": "UNC_M_RDB_FULL",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
+ "BriefDescription": "Read Data Buffer Inserts",
+ "EventCode": "0x17",
+ "EventName": "UNC_M_RDB_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
+ "BriefDescription": "Read Data Buffer Not Empty",
+ "EventCode": "0x18",
+ "EventName": "UNC_M_RDB_NOT_EMPTY",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PCLS.RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M_PCLS.RD",
+ "BriefDescription": "Read Data Buffer Occupancy",
+ "EventCode": "0x1A",
+ "EventName": "UNC_M_RDB_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PCLS.WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M_PCLS.WR",
+ "BriefDescription": "Read Pending Queue Full Cycles",
+ "EventCode": "0x12",
+ "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PCLS.TOTAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M_PCLS.TOTAL",
+ "BriefDescription": "Read Pending Queue Full Cycles",
+ "EventCode": "0x15",
+ "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M_DRAM_PRE_ALL",
+ "BriefDescription": "Read Pending Queue Not Empty",
+ "EventCode": "0x11",
+ "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
"PerPkg": "1",
+ "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PARITY_ERRORS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2c",
- "EventName": "UNC_M_PARITY_ERRORS",
+ "BriefDescription": "Read Pending Queue Not Empty",
+ "EventCode": "0x11",
+ "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
"PerPkg": "1",
+ "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M_POWER_CHANNEL_PPD",
- "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
- "MetricName": "power_channel_ppd %",
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS.PCH0",
"PerPkg": "1",
+ "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles Memory is in self refresh power mode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M_POWER_SELF_REFRESH",
- "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
- "MetricName": "power_self_refresh %",
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS.PCH1",
"PerPkg": "1",
+ "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M_RDB_FULL",
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x80",
+ "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
+ "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M_RDB_NOT_EMPTY",
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x81",
+ "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
+ "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1A",
- "EventName": "UNC_M_RDB_OCCUPANCY",
+ "BriefDescription": "Write Pending Queue Full Cycles",
+ "EventCode": "0x22",
+ "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
"PerPkg": "1",
+ "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
+ "BriefDescription": "Write Pending Queue Full Cycles",
+ "EventCode": "0x16",
+ "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
"PerPkg": "1",
+ "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
+ "BriefDescription": "Write Pending Queue Not Empty",
+ "EventCode": "0x21",
+ "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
"PerPkg": "1",
+ "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
+ "BriefDescription": "Write Pending Queue Not Empty",
+ "EventCode": "0x21",
+ "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
"PerPkg": "1",
+ "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS.PCH0",
"PerPkg": "1",
+ "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS.PCH1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Pre-charges due to page misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x82",
+ "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
- "UMask": "0x0c",
+ "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
"Unit": "iMC"
},
{
- "BriefDescription": "Free running counter that increments for the Memory Controller",
- "Counter": "4",
- "CounterType": "FREERUN",
- "EventName": "UNC_M_CLOCKTICKS_FREERUN",
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x83",
+ "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
+ "PerPkg": "1",
+ "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
+ "PerPkg": "1",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
+ "PerPkg": "1",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x24",
+ "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
+ "PerPkg": "1",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x24",
+ "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
"PerPkg": "1",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x2",
"Unit": "iMC"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json
index 1701db46696d..3b35e08e24d6 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json
@@ -1,25060 +1,21961 @@
[
{
- "BriefDescription": "Uncore cache clock ticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventName": "UNC_CHA_CLOCKTICKS",
+ "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_READ",
+ "Filter": "config1=0x40040e33",
"PerPkg": "1",
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
+ "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_WRITE",
+ "Filter": "config1=0x40041e33",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
+ "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
+ "EventCode": "0x83",
+ "EventName": "LLC_MISSES.PCIE_READ",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "MetricName": "LLC_MISSES.PCIE_READ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized : All Lines Victimized",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
+ "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
+ "EventCode": "0x83",
+ "EventName": "LLC_MISSES.PCIE_WRITE",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "MetricName": "LLC_MISSES.PCIE_WRITE",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS",
+ "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.UNCACHEABLE",
+ "Filter": "config1=0x40e33",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES",
+ "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_FULL",
+ "Filter": "config1=0x41833",
"PerPkg": "1",
- "UMask": "0x0c",
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xc001fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for E-state entries",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
+ "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
+ "Filter": "config1=0x41a33",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xc001fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for M-state entries",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for S-state entries",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0xC001FF01",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0xC001FD01",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0xC80FFD01",
- "UMaskExt": "0xC80FFD",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0xC807FD01",
- "UMaskExt": "0xC807FD",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.UNCACHEABLE",
- "Filter": "config1=0x40e33",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_READ",
- "Filter": "config1=0x40040e33",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x81",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_WRITE",
- "Filter": "config1=0x40041e33",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x81",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_FULL",
- "Filter": "config1=0x41833",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x81",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
- "Filter": "config1=0x41a33",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0xC80FFE01",
- "UMaskExt": "0xC80FFE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0xC807FE01",
- "UMaskExt": "0xC807FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0xC001FF04",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0xC001FD04",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0xC001FE04",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0xC001FF01",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0xC001FD01",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x83",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x83",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0xC80FFE01",
- "UMaskExt": "0xC80FFE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x83",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0xC807FE01",
- "UMaskExt": "0xC807FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0xC001FF04",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0xC001FD04",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0xC001FE04",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0xCC43FE04",
- "UMaskExt": "0xCC43FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0xC88FFD01",
- "UMaskExt": "0xC88FFD",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0xC827FD01",
- "UMaskExt": "0xC827FD",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0xC8A7FD01",
- "UMaskExt": "0xC8A7FD",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x89",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0xC887FD01",
- "UMaskExt": "0xC887FD",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x89",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0xC88FFE01",
- "UMaskExt": "0xC88FFE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x89",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0xC827FE01",
- "UMaskExt": "0xC827FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0xC8A7FE01",
- "UMaskExt": "0xC8A7FE",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0xC887FE01",
- "UMaskExt": "0xC887FE",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0xC827FD01",
- "UMaskExt": "0xC827FD",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0xC8A7FD01",
- "UMaskExt": "0xC8A7FD",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0xC827FE01",
- "UMaskExt": "0xC827FE",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0xCC43FD04",
- "UMaskExt": "0xCC43FD",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0xCC43FF04",
- "UMaskExt": "0xCC43FF",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0xC887FF01",
- "UMaskExt": "0xC887FF",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8B",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0xC807FF01",
- "UMaskExt": "0xC807FF",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8B",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0xC827FF01",
- "UMaskExt": "0xC827FF",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8B",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0xC8A7FF01",
- "UMaskExt": "0xC8A7FF",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0xC80FFF01",
- "UMaskExt": "0xC80FFF",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0xC807FF01",
- "UMaskExt": "0xC807FF",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0xC827FF01",
- "UMaskExt": "0xC827FF",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0xC8A7FF01",
- "UMaskExt": "0xC8A7FF",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0xC80FFF01",
- "UMaskExt": "0xC80FFF",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0xC8C7FF01",
- "UMaskExt": "0xC8C7FF",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0xCD43FF04",
- "UMaskExt": "0xCD43FF",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0xCD43FD04",
- "UMaskExt": "0xCD43FD",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x85",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0xCD43FE04",
- "UMaskExt": "0xCD43FE",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x85",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0xc867fe01",
- "UMaskExt": "0xc867fe",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x85",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0xc86ffe01",
- "UMaskExt": "0xc86ffe",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0xC86FFE01",
- "UMaskExt": "0xC86FFE",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0xC87FDE01",
- "UMaskExt": "0xC87FDE",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0xC877DE01",
- "UMaskExt": "0xC877DE",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0xC8F3FE04",
- "UMaskExt": "0xC8F3FE",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0xc8f3fe04",
- "UMaskExt": "0xc8f3fe",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0xC8F3FD04",
- "UMaskExt": "0xC8F3FD",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0xC8F3FF04",
- "UMaskExt": "0xC8F3FF",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0xC8F3FF04",
- "UMaskExt": "0xC8F3FF",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x87",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0xC867FE01",
- "UMaskExt": "0xC867FE",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x87",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x1BC1FF",
- "UMaskExt": "0x1BC1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_IIO_CLOCKTICKS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x87",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "PortMask": "0x01",
- "ScaleUnit": "4Bytes",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "PortMask": "0x02",
- "ScaleUnit": "4Bytes",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "ScaleUnit": "4Bytes",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "ScaleUnit": "4Bytes",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "LLC_MISSES.PCIE_WRITE",
- "FCMask": "0x07",
- "Filter": "ch_mask=0x1f",
- "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "MetricName": "LLC_MISSES.PCIE_WRITE",
- "PerPkg": "1",
- "PortMask": "0x01",
- "ScaleUnit": "4Bytes",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "ScaleUnit": "4Bytes",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "ScaleUnit": "4Bytes",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "ScaleUnit": "4Bytes",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "ScaleUnit": "4Bytes",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "LLC_MISSES.PCIE_READ",
- "FCMask": "0x07",
- "Filter": "ch_mask=0x1f",
- "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "MetricName": "LLC_MISSES.PCIE_READ",
- "PerPkg": "1",
- "PortMask": "0x01",
- "ScaleUnit": "4Bytes",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number requests PCIe makes of the main die : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x8D",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x8D",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x8D",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8F",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8F",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Free running counter that increments for IIO clocktick",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8F",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
- "FCMask": "0x04",
+ "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
- "FCMask": "0x04",
+ "BriefDescription": "CHA to iMC Bypass : Not Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
- "FCMask": "0x04",
+ "BriefDescription": "CHA to iMC Bypass : Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
- "FCMask": "0x04",
+ "BriefDescription": "Uncore cache clock ticks",
+ "EventName": "UNC_CHA_CLOCKTICKS",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x03",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
- "FCMask": "0x04",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_CHA_CMS_CLOCKTICKS",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x03",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
- "FCMask": "0x04",
+ "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xf2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
- "FCMask": "0x04",
+ "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xf1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
- "FCMask": "0x04",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x42",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
- "FCMask": "0x04",
+ "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x41",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
- "FCMask": "0x04",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x82",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
- "FCMask": "0x04",
+ "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x81",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
- "FCMask": "0x04",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x22",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
- "FCMask": "0x04",
+ "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
- "FCMask": "0x04",
+ "BriefDescription": "Counter 0 Occupancy",
+ "EventCode": "0x1F",
+ "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
- "FCMask": "0x04",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6E",
+ "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
- "FCMask": "0x04",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6E",
+ "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
- "FCMask": "0x04",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6E",
+ "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
"PerPkg": "1",
- "PortMask": "0xff",
- "UMask": "0x03",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
- "FCMask": "0x04",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
"PerPkg": "1",
- "UMask": "0xff",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Lost Forward",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_I_MISC1.LOST_FWD",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "IRP"
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Coherent Ops : WbMtoI",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0f",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound write (fast path) requests received by the IRP",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_I_CLOCKTICKS",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
"PerPkg": "1",
- "Unit": "IRP"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FAF RF full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_I_FAF_FULL",
+ "BriefDescription": "Distress signal asserted : DPT Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_I_FAF_INSERTS",
+ "BriefDescription": "Distress signal asserted : DPT Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Occupancy of the IRP FAF queue",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_I_FAF_OCCUPANCY",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FAF allocation -- sent to ADQ",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_I_FAF_TRANSACTIONS",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x78",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the mesh to memory (M2M)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventName": "UNC_M2M_CLOCKTICKS",
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "EventCode": "0xBA",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M2P_CLOCKTICKS",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xBA",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M2P_CMS_CLOCKTICKS",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
- "Counter": "FIXED",
- "CounterType": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_U_CLOCKTICKS",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "Unit": "UBOX"
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - All Lines",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x200F",
- "UMaskExt": "0x20",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Number of times that an RFO hit in S state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RFO_HIT_S",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x30",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xC001FFff",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC80FFD01",
- "UMaskExt": "0xC80FFD",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xC807FD01",
- "UMaskExt": "0xC807FD",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0xc803fe04",
- "UMaskExt": "0xc803fe",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xc803fe04",
- "UMaskExt": "0xc803fe",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xcc43fe04",
- "UMaskExt": "0xcc43fe",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass : Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass : Not Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+ "BriefDescription": "Horizontal IV Ring in Use : Left",
+ "EventCode": "0xB9",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+ "BriefDescription": "Horizontal IV Ring in Use : Right",
+ "EventCode": "0xB9",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+ "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+ "BriefDescription": "HA to iMC Reads Issued : ISOCH",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
"PerPkg": "1",
- "UMask": "0x81",
+ "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
"PerPkg": "1",
- "UMask": "0xF1",
+ "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
"PerPkg": "1",
- "UMask": "0x22",
+ "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
"PerPkg": "1",
- "UMask": "0x42",
+ "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
"PerPkg": "1",
- "UMask": "0x82",
+ "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
"PerPkg": "1",
- "UMask": "0xF2",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
+ "UMask": "0x1fffff",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
+ "BriefDescription": "Cache Lookups : All Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1bd0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
+ "BriefDescription": "Cache Lookups : Code Reads",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
+ "BriefDescription": "Cache Lookups : CRd Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
+ "BriefDescription": "Cache Lookups : Code Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd001",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
+ "BriefDescription": "Cache Lookups : Local request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1bc1ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x1bc1ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1fc1ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
+ "BriefDescription": "Cache Lookups : Data Read Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions.",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
+ "BriefDescription": "Cache Lookups : Data Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bc101",
"Unit": "CHA"
},
{
- "BriefDescription": "HA to iMC Reads Issued : ISOCH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x841ff",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+ "BriefDescription": "Cache Lookups : E State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.E",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+ "BriefDescription": "Cache Lookups : F State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.F",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+ "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
+ "PerPkg": "1",
+ "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1a44ff",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Lines in M state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+ "BriefDescription": "Cache Lookups : I State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.I",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Lines in E state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+ "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Lines in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+ "BriefDescription": "Cache Lookups : M State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.M",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local Only",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
+ "BriefDescription": "Cache Lookups : All Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1fe001",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - Lines in M State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+ "BriefDescription": "Cache Lookups : Write Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
"PerPkg": "1",
- "UMask": "0x2001",
- "UMaskExt": "0x20",
+ "PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC.",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - Lines in E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+ "BriefDescription": "Cache Lookups : Reads",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ",
"PerPkg": "1",
- "UMask": "0x2002",
- "UMaskExt": "0x20",
+ "PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd9ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - Lines in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
+ "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
"PerPkg": "1",
- "UMask": "0x2004",
- "UMaskExt": "0x20",
+ "PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x9d9ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+ "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x11d9ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : Write Combining Aliasing",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.WC_ALIASING",
+ "BriefDescription": "Cache Lookups : Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd901",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+ "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0xbd901",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+ "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x13d901",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
+ "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x161901",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
+ "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0xa19ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
+ "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd90e",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
+ "BriefDescription": "Cache Lookups : RFO Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
+ "UMask": "0x1bc8ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
+ "BriefDescription": "Cache Lookups : RFO Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
+ "BriefDescription": "Cache Lookups : RFO Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bc801",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "UMask": "0x888ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
+ "BriefDescription": "Cache Lookups : S State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.S",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
+ "BriefDescription": "Cache Lookups : SnoopFilter - E State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
+ "BriefDescription": "Cache Lookups : SnoopFilter - H State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
"PerPkg": "1",
- "UMaskExt": "0x10",
+ "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
+ "BriefDescription": "Cache Lookups : SnoopFilter - S State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
+ "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
"PerPkg": "1",
- "UMaskExt": "0x40",
+ "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.",
+ "UMask": "0x1a42ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
"PerPkg": "1",
- "UMaskExt": "0x80",
+ "UMask": "0x842ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
+ "BriefDescription": "Lines Victimized : All Lines Victimized",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
"PerPkg": "1",
- "UMaskExt": "0x100",
+ "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0xf",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
+ "BriefDescription": "Lines Victimized : Lines in E state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "UMaskExt": "0x200",
+ "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
+ "BriefDescription": "Lines Victimized : Local - All Lines",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
"PerPkg": "1",
- "UMaskExt": "0x800",
+ "PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x200f",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
+ "BriefDescription": "Lines Victimized : Local - Lines in E State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
"PerPkg": "1",
- "UMaskExt": "0x1000",
+ "PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2002",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
+ "BriefDescription": "Lines Victimized : Local - Lines in M State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
"PerPkg": "1",
- "UMaskExt": "0x2000",
+ "PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2001",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
+ "BriefDescription": "Lines Victimized : Local Only",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
"PerPkg": "1",
- "UMaskExt": "0x4000",
+ "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
+ "BriefDescription": "Lines Victimized : Local - Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
"PerPkg": "1",
- "UMaskExt": "0x8000",
+ "PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2004",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
+ "BriefDescription": "Lines Victimized : Lines in M state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
- "UMaskExt": "0x10000",
+ "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
+ "BriefDescription": "Lines Victimized : Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
- "UMaskExt": "0x20000",
+ "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
+ "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
"PerPkg": "1",
- "UMaskExt": "0x40000",
+ "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
+ "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
"PerPkg": "1",
- "UMaskExt": "0x80000",
+ "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
+ "BriefDescription": "Number of times that an RFO hit in S state.",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RFO_HIT_S",
"PerPkg": "1",
- "UMaskExt": "0x100000",
+ "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
+ "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "UMaskExt": "0x200000",
+ "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
+ "BriefDescription": "Cbo Misc : Write Combining Aliasing",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.WC_ALIASING",
"PerPkg": "1",
- "UMaskExt": "0x400000",
+ "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "EventCode": "0xE6",
+ "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "UMaskExt": "0x800000",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "EventCode": "0xE6",
+ "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "UMaskExt": "0x1000000",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
+ "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
"PerPkg": "1",
- "UMaskExt": "0x2000000",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
+ "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
"PerPkg": "1",
- "UMaskExt": "0x4000000",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
+ "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
"PerPkg": "1",
- "UMaskExt": "0x8000000",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
"BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
+ "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
"PerPkg": "1",
- "UMaskExt": "0x10000000",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
"PerPkg": "1",
- "UMaskExt": "0x08",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
"PerPkg": "1",
- "UMaskExt": "0x10",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.",
+ "UMask": "0x8",
"Unit": "CHA"
},
- {
- "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ {
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
"PerPkg": "1",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
"PerPkg": "1",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
"PerPkg": "1",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
"PerPkg": "1",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x30",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .",
+ "UMask": "0x3",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0xc",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+ "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_CHA_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+ "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+ "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "PerPkg": "1",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
"PerPkg": "1",
+ "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
+ "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
+ "BriefDescription": "ISMQ Rejects - Set 1 : HA",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+ "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent : Directed snoops for Local Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+ "BriefDescription": "ISMQ Retries - Set 1 : HA",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+ "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+ "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspIFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+ "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspSFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
+ "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
+ "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspCnflct",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+ "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+ "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
+ "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
+ "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
+ "BriefDescription": "Other Retries - Set 1 : ANY0",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
+ "BriefDescription": "Other Retries - Set 1 : HA",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
+ "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
+ "BriefDescription": "Other Retries - Set 1 : LLC Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI : Pushed to LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+ "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI : Pushed to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+ "BriefDescription": "Other Retries - Set 1 : SF Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
+ "BriefDescription": "Other Retries - Set 1 : Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMaskExt": "0x08",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMaskExt": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Sent (on 0?)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.SENT0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
+ "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Sent (on 1?)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.SENT1",
+ "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
+ "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
"PerPkg": "1",
+ "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.I",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : SnoopFilter - S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : SnoopFilter - E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : SnoopFilter - H State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
+ "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.S",
+ "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.E",
+ "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : M State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.M",
+ "BriefDescription": "Request Queue Retries - Set 1 : HA",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : F State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.F",
+ "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : RFO Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
+ "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x1BC8FF",
- "UMaskExt": "0x1BC8",
+ "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : IRQ - iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
+ "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "PerPkg": "1",
+ "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : SF/LLC Evictions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+ "BriefDescription": "Request Queue Retries - Set 1 : Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PRQ - IOSF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : IRQ - Non iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All from Local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0xC000FF04",
- "UMaskExt": "0xC000FF",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All from Local iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC000FF01",
- "UMaskExt": "0xC000FF",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All from Local iA and IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC000FF05",
- "UMaskExt": "0xC000FF",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just Hits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : MMCFG Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
+ "BriefDescription": "Transgress Ingress Bypass : AK",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just Local Targets",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMaskExt": "0x80",
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMaskExt": "0x200",
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMaskExt": "0x400",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just NearMem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMaskExt": "0x400000",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just NotNearMem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMaskExt": "0x800000",
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just NonCoherent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
- "UMaskExt": "0x1000000",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : Just ISOC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMaskExt": "0x2000000",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : IRQ - iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "BriefDescription": "Transgress Injection Starvation : AK",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : PRQ - IOSF",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : IRQ - Non iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All from Local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0xC000FF04",
- "UMaskExt": "0xC000FF",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All from Local iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
+ "BriefDescription": "Transgress Injection Starvation : IV",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0xC000FF01",
- "UMaskExt": "0xC000FF",
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All from Local iA and IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
"PerPkg": "1",
- "UMask": "0xC000FF05",
- "UMaskExt": "0xC000FF",
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : Just Hits",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : Just Misses",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : MMCFG Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : Just Local Targets",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
+ "BriefDescription": "Transgress Ingress Allocations : AK",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMaskExt": "0x80",
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMaskExt": "0x200",
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMaskExt": "0x400",
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : Just NearMem",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMaskExt": "0x400000",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : Just NotNearMem",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMaskExt": "0x800000",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : Just NonCoherent",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMaskExt": "0x1000000",
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : Just ISOC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMaskExt": "0x2000000",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "CHA"
},
- {
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
+ {
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Transgress Ingress Occupancy : AK",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Snoops Sent : All",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Snoops Sent : Directed snoops for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Snoop Responses Received Local : RspCnflct",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Snoop Responses Received Local : RspFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Snoop Responses Received Local : RspI",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Snoop Responses Received Local : RspIFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Snoop Responses Received Local : RspS",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Snoop Responses Received Local : RspSFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD1",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD1",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD1",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD3",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD3",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD3",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD5",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD5",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD5",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD7",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD7",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD7",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "TOR Inserts : All",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ffff",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "TOR Inserts : DDR4 Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.DDR",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "TOR Inserts : SF/LLC Evictions",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "TOR Inserts : Just Hits",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c7ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8d7ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80fff01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "TOR Inserts; CRd Pref from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88fff01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffd01",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
+ "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc867fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86ffe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc877de01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86ffe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc87fde01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc3fff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc37ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc2fff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc27ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc67ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86fff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
+ "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "TOR Inserts : All requests from IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c3ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc23ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "TOR Inserts : IRQ - iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "TOR Inserts : IRQ - Non iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
"PerPkg": "1",
+ "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
+ "BriefDescription": "TOR Inserts : Just ISOC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
+ "BriefDescription": "TOR Inserts : Just Local Targets",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "TOR Inserts : All from Local iA and IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+ "UMask": "0xc000ff05",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "TOR Inserts : All from Local iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+ "UMask": "0xc000ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "TOR Inserts : All from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+ "UMask": "0xc000ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
+ "BriefDescription": "TOR Inserts : Just Misses",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MISS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AK",
+ "BriefDescription": "TOR Inserts : MMCFG Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
+ "BriefDescription": "TOR Inserts : Just NearMem",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.IV",
+ "BriefDescription": "TOR Inserts : Just NonCoherent",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "TOR Inserts : Just NotNearMem",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
+ "BriefDescription": "TOR Inserts : PRQ - IOSF",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "TOR Occupancy : DDR4 Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
+ "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
+ "BriefDescription": "TOR Occupancy : Just Hits",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
+ "BriefDescription": "TOR Occupancy : All requests from iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
+ "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c7ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8d7ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80fff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88fff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
+ "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AK",
+ "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
+ "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.IV",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
+ "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fd01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
+ "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
+ "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc867fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86ffe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc877de01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86ffe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867fe01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc87fde01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc27ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86fff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "TOR Occupancy : All requests from IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c3ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fd04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fe04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc23ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "TOR Occupancy : IRQ - iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "TOR Occupancy : IRQ - Non iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
"PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "TOR Occupancy : Just ISOC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "TOR Occupancy : Just Local Targets",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "TOR Occupancy : All from Local iA and IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+ "UMask": "0xc000ff05",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "TOR Occupancy : All from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+ "UMask": "0xc000ff01",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "TOR Occupancy : All from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+ "UMask": "0xc000ff04",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "TOR Occupancy : Just Misses",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "TOR Occupancy : MMCFG Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "TOR Occupancy : Just NearMem",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "TOR Occupancy : Just NonCoherent",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "TOR Occupancy : Just NotNearMem",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "TOR Occupancy : PRQ - IOSF",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
"EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
"EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
"EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA6",
"EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
"EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA7",
"EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
"EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
"EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
"EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
"EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
"EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA2",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
"EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
"EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
"EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
"EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
"EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA3",
"EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA1",
"EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
"EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
"EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
"EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
"EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
"EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA4",
"EventName": "UNC_CHA_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
"EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
"EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
"EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
"EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
"EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
"EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
"EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA0",
"EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
"EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
"EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA5",
"EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xA5",
"EventName": "UNC_CHA_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
"EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
"EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
"EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
"EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9C",
"EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9C",
"EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9D",
"EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
"EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
"EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
"EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
"EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9E",
"EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9E",
"EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x94",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x95",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x95",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x96",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x97",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x97",
"EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
"EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
"EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
"EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
"EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
"EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
"EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
"EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x93",
"EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x93",
"EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x98",
"EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
"EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
"EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
"EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x99",
"EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x99",
"EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x90",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x91",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x91",
"EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9A",
"EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
"EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
"EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
"EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
"EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
"EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
"EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9B",
"EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9B",
"EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9B",
"EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
- "PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB0",
"EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB0",
"EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB4",
"EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB4",
"EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB1",
"EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB1",
"EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB2",
"EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB2",
"EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical IV Ring in Use : Down",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB5",
"EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB5",
"EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_CHA_RING_SRC_THRTL",
- "PerPkg": "1",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
- "PerPkg": "1",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
- "PerPkg": "1",
- "UMask": "0x1FFFFF",
- "UMaskExt": "0x1FFF",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x1bc1ff",
- "UMaskExt": "0x1bc1",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x1A44FF",
- "UMaskExt": "0x1A44",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
+ "BriefDescription": "WbPushMtoI : Pushed to LLC",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
"PerPkg": "1",
- "UMask": "0x1bd0ff",
- "UMaskExt": "0x1bd0",
+ "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+ "BriefDescription": "WbPushMtoI : Pushed to Memory",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
"PerPkg": "1",
- "UMask": "0xC88FFD01",
- "UMaskExt": "0xC88FFD",
+ "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
"PerPkg": "1",
- "UMask": "0xC887FD01",
- "UMaskExt": "0xC887FD",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
"PerPkg": "1",
- "UMask": "0xC88FFE01",
- "UMaskExt": "0xC88FFE",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
"PerPkg": "1",
- "UMask": "0xC8A7FE01",
- "UMaskExt": "0xC8A7FE",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
"PerPkg": "1",
- "UMask": "0xC887FE01",
- "UMaskExt": "0xC887FE",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
"PerPkg": "1",
- "UMask": "0xC803FD04",
- "UMaskExt": "0xC803FD",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
"PerPkg": "1",
- "UMask": "0xCC43FD04",
- "UMaskExt": "0xCC43FD",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
"PerPkg": "1",
- "UMask": "0xC803FD04",
- "UMaskExt": "0xC803FD",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
"PerPkg": "1",
- "UMask": "0xC803FF04",
- "UMaskExt": "0xC803FF",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; CRd Pref from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
"PerPkg": "1",
- "UMask": "0xC88FFF01",
- "UMaskExt": "0xC88FFF",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
"PerPkg": "1",
- "UMask": "0xC803FF04",
- "UMaskExt": "0xC803FF",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
"PerPkg": "1",
- "UMask": "0xCC43FF04",
- "UMaskExt": "0xCC43FF",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
"PerPkg": "1",
- "UMask": "0xC887FF01",
- "UMaskExt": "0xC887FF",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
"PerPkg": "1",
- "UMask": "0xC88FFF01",
- "UMaskExt": "0xC88FFF",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
"PerPkg": "1",
- "UMask": "0xC8D7FF01",
- "UMaskExt": "0xC8D7FF",
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
+ "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
"PerPkg": "1",
- "UMask": "0xCC23FF04",
- "UMaskExt": "0xCC23FF",
+ "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
+ "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
"PerPkg": "1",
- "UMask": "0xC8C3FF04",
- "UMaskExt": "0xC8C3FF",
+ "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
+ "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
"PerPkg": "1",
- "UMask": "0xcc27ff01",
- "UMaskExt": "0xcc27ff",
+ "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
+ "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
"PerPkg": "1",
- "UMask": "0xc867fe01",
- "UMaskExt": "0xc867fe",
+ "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
+ "BriefDescription": "XPT Prefetches : Sent (on 0?)",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.SENT0",
"PerPkg": "1",
- "UMask": "0xc86ffe01",
- "UMaskExt": "0xc86ffe",
+ "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : RFO Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
+ "BriefDescription": "XPT Prefetches : Sent (on 1?)",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.SENT1",
"PerPkg": "1",
- "UMaskExt": "0x08",
+ "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
"PerPkg": "1",
- "UMaskExt": "0x800",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : All Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
"PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Data Read Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Write Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : CRd Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
"PerPkg": "1",
- "UMaskExt": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Local request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
"PerPkg": "1",
- "UMaskExt": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : All Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
"PerPkg": "1",
- "UMask": "0x1fe001",
- "UMaskExt": "0x1fe0",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
"PerPkg": "1",
- "UMask": "0x1fc1ff",
- "UMaskExt": "0x1fc1",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Data Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
"PerPkg": "1",
- "UMask": "0x1bc101",
- "UMaskExt": "0x1bc1",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
"PerPkg": "1",
- "UMask": "0x841ff",
- "UMaskExt": "0x841",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
"PerPkg": "1",
- "UMask": "0x842ff",
- "UMaskExt": "0x842",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
"PerPkg": "1",
- "UMask": "0x888ff",
- "UMaskExt": "0x888",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+ "PerPkg": "1",
+ "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
"PerPkg": "1",
- "UMask": "0xC867FF01",
- "UMaskExt": "0xC867FF",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
"PerPkg": "1",
- "UMask": "0xC86FFF01",
- "UMaskExt": "0xC86FFF",
- "Unit": "CHA"
+ "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : DDR4 Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.DDR",
+ "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
+ "EventCode": "0x01",
+ "EventName": "UNC_IIO_CLOCKTICKS",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : DDR4 Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+ "BriefDescription": "Free running counter that increments for IIO clocktick",
+ "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
+ "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC8F3FD04",
- "UMaskExt": "0xC8F3FD",
- "Unit": "CHA"
+ "PortMask": "0xFF",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC867FE01",
- "UMaskExt": "0xC867FE",
- "Unit": "CHA"
+ "PortMask": "0xff",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC86FFE01",
- "UMaskExt": "0xC86FFE",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC8C7FF01",
- "UMaskExt": "0xC8C7FF",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC8D7FF01",
- "UMaskExt": "0xC8D7FF",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xCC27FF01",
- "UMaskExt": "0xCC27FF",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC877DE01",
- "UMaskExt": "0xC877DE",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC87FDE01",
- "UMaskExt": "0xC87FDE",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC867FF01",
- "UMaskExt": "0xC867FF",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC86FFF01",
- "UMaskExt": "0xC86FFF",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xCC23FF04",
- "UMaskExt": "0xCC23FF",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+ "UMask": "0xff",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC8C3FF04",
- "UMaskExt": "0xC8C3FF",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+ "UMask": "0xff",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xCD43FF04",
- "UMaskExt": "0xCD43FF",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xCD43FD04",
- "UMaskExt": "0xCD43FD",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xCD43FE04",
- "UMaskExt": "0xCD43FE",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xcc3fff01",
- "UMaskExt": "0xcc3fff",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC837FE01",
- "UMaskExt": "0xC837FE",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC837FD01",
- "UMaskExt": "0xC837FD",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xC837FF01",
- "UMaskExt": "0xC837FF",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0xcc67ff01",
- "UMaskExt": "0xcc67ff",
- "Unit": "CHA"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xcc37ff01",
- "UMaskExt": "0xcc37ff",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xcc2fff01",
- "UMaskExt": "0xcc2fff",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC837FF01",
- "UMaskExt": "0xC837FF",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC837FD01",
- "UMaskExt": "0xC837FD",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC837FE01",
- "UMaskExt": "0xC837FE",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Code Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1BD001",
- "UMaskExt": "0x1BD0",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : RFO Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1BC801",
- "UMaskExt": "0x1BC8",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1BD9FF",
- "UMaskExt": "0x1BD9",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1BD901",
- "UMaskExt": "0x1BD9",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0BD901",
- "UMaskExt": "0x0BD9",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x13D901",
- "UMaskExt": "0x13D9",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x09D9FF",
- "UMaskExt": "0x09D9",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0A19FF",
- "UMaskExt": "0x0A19",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x11D9FF",
- "UMaskExt": "0x11D9",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1BD90E",
- "UMaskExt": "0x1BD9",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x161901",
- "UMaskExt": "0x1619",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1A42FF",
- "UMaskExt": "0x1A42",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : Code Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1BD0FF",
- "UMaskExt": "0x1BD0",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
- "UMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
- "UMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
- "UMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x20",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x20",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x20",
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x20",
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x20",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x20",
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
"EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB lookups first",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB lookups all",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Hits to a 4K Page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.4K_HITS",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Hits to a 2M Page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.2M_HITS",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Hits to a 1G Page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.1G_HITS",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.MISSES",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Context cache lookups",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Context cache hits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": PageWalk cache lookup",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOMMU memory access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Cycles PWT full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
- "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": ": Interrupt Entry cache lookup",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Interrupt Entry cache hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
- "UMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
- "UMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
- "UMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
- "UMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
- "UMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
- "UMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x40",
- "UMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x80",
- "UMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+ "BriefDescription": "Incoming arbitration requests : Passing data to be written",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+ "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+ "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+ "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
+ "BriefDescription": "Incoming arbitration requests : Request Ownership",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
+ "BriefDescription": "Incoming arbitration requests : Writing line",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
+ "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
+ "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+ "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+ "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+ "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+ "BriefDescription": "Incoming arbitration requests granted : Writing line",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": ": IOTLB Hits to a 1G Page",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.1G_HITS",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
+ "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": ": IOTLB Hits to a 2M Page",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.2M_HITS",
+ "PerPkg": "1",
+ "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": ": IOTLB Hits to a 4K Page",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.4K_HITS",
+ "PerPkg": "1",
+ "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": ": IOTLB lookups all",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
+ "PerPkg": "1",
+ "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": ": Context cache hits",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": ": Context cache lookups",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
+ "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": ": IOTLB lookups first",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
+ "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.MISSES",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
+ "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": ": Cycles PWT full",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
+ "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": ": IOMMU memory access",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
+ "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": ": PWC Hit to a 1G page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
+ "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": ": PWC Hit to a 2M page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
+ "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": ": PWC Hit to a 4K page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
+ "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": ": PWT Hit to a 256T page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
+ "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": ": PageWalk cache fill",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
+ "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": ": PageWalk cache lookup",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
+ "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": ": Interrupt Entry cache hit",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
+ "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": ": Interrupt Entry cache lookup",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
+ "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": ": Device-selective Context cache invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
+ "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": ": Domain-selective Context cache invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
+ "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": ": Context cache global invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
+ "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
+ "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": ": Global IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
+ "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
- "FCMask": "0x07",
+ "BriefDescription": ": Page-selective IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
+ "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
+ "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
+ "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
+ "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
+ "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x10",
+ "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
+ "EventCode": "0x03",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x10",
+ "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+ "EventCode": "0x03",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
+ "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+ "EventCode": "0x03",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
+ "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
+ "EventCode": "0x03",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
+ "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+ "EventCode": "0x03",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
+ "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+ "EventCode": "0x03",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
+ "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Counting disabled",
+ "EventCode": "0x80",
+ "EventName": "UNC_IIO_NOTHING",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
+ "BriefDescription": "Occupancy of outbound request queue : To device",
+ "EventCode": "0xC5",
+ "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
+ "BriefDescription": ": Passing data to be written",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": ": Passing data to be written : Only for posted requests",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": ": Issuing final read or write of line",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x01",
+ "PortMask": "0xFF",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": ": Processing response from IOMMU",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x01",
+ "PortMask": "0xFF",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "BriefDescription": ": Issuing to IOMMU",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x02",
+ "PortMask": "0xFF",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
+ "BriefDescription": ": Request Ownership",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0xFF",
+ "PublicDescription": ": Request Ownership : Only for posted requests",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": ": Writing line",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0xFF",
+ "PublicDescription": ": Writing line : Only for posted requests",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "BriefDescription": "Number requests sent to PCIe from main die : From IRP",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "Number requests sent to PCIe from main die : From ITC",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x08",
+ "PortMask": "0xFF",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
+ "EventCode": "0x85",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x10",
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "BriefDescription": "Number requests PCIe makes of the main die : All",
+ "EventCode": "0x85",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x10",
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "BriefDescription": "Num requests sent by PCIe - by target : Abort",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x20",
+ "PortMask": "0xFF",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x20",
+ "PortMask": "0xFF",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
+ "BriefDescription": "Num requests sent by PCIe - by target : Memory",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x80",
+ "PortMask": "0xFF",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
+ "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x80",
+ "PortMask": "0xFF",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x01",
+ "PortMask": "0xFF",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x01",
+ "PortMask": "0xFF",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
- "FCMask": "0x07",
+ "BriefDescription": "ITC address map 1",
+ "EventCode": "0x8F",
+ "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x02",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
+ "EventCode": "0xD0",
+ "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0xFF",
+ "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
+ "EventCode": "0xD1",
+ "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0xFF",
+ "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
- "FCMask": "0x07",
+ "BriefDescription": "PWT occupancy",
+ "EventCode": "0x42",
+ "EventName": "UNC_IIO_PWT_OCCUPANCY",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x08",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x10",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "BriefDescription": "PCIe Request - cacheline complete : Writing line",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+ "BriefDescription": "PCIe Request complete : Passing data to be written",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+ "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x40",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
+ "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x80",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
+ "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x80",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": "PCIe Request complete : Request Ownership",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x01",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": "PCIe Request complete : Writing line",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x01",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "BriefDescription": "PCIe Request - pass complete : Request Ownership",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "PCIe Request - pass complete : Writing line",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
- "FCMask": "0x07",
+ "BriefDescription": "Symbol Times on Link",
+ "EventCode": "0x82",
+ "EventName": "UNC_IIO_SYMBOL_TIMES",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x08",
+ "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x20",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x20",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
"UMask": "0x40",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x80",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x80",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x01",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x01",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x08",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x40",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x40",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Counting disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_IIO_NOTHING",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "PWT occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_IIO_PWT_OCCUPANCY",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Symbol Times on Link",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_IIO_SYMBOL_TIMES",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "1",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "2",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "3",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "4",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "5",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "6",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "7",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "8",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "9",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "13",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "12",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "11",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "10",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "15",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "14",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "16",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": PWC Hit to a 4K page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": PWC Hit to a 2M page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": PWC Hit to a 1G page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": PWT Hit to a 256T page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": PageWalk cache fill",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": Global IOTLB invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": Page-selective IOTLB invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": Context cache global invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": ": Domain-selective Context cache invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": ": Device-selective Context cache invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x40",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Abort",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x80",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "ITC address map 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": ": Issuing to IOMMU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": ": Processing response from IOMMU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": ": Request Ownership",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": ": Issuing final read or write of line",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": ": Writing line",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": ": Passing data to be written",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Occupancy of outbound request queue : To device",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC5",
- "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request complete : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request complete : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request complete : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request - pass complete : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request - pass complete : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number requests sent to PCIe from main die : From IRP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number requests sent to PCIe from main die : From ITC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
- "FCMask": "0x04",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x03",
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
- "FCMask": "0x04",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xFF",
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses : Hit M",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.RFO",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Total Write Cache Occupancy : Any Source",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0F",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Total Write Cache Occupancy : Snoops",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0F",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Coherent Ops : CLFlush",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.EVICTS",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1e",
- "EventName": "UNC_I_MISC0.FAST_REQ",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.FAST_REJ",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1e",
- "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1e",
- "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.FAST_XFER",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_I",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_S",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_E",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_M",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Misc Events - Set 1 : Received Invalid",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Misc Events - Set 1 : Received Valid",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x40",
- "Unit": "IRP"
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Transactions : P2P reads",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Transactions : P2P Writes",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Transactions : P2P Message",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Transactions : P2P completions",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Transactions : Match if remote only",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Transactions : match if remote and target matches",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Transactions : match if local only",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
"UMask": "0x40",
- "Unit": "IRP"
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Transactions : match if local and target matches",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses : Miss",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.MISS",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses : Hit I",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses : Hit E or S",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses : SnpCode",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses : SnpData",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses : SnpInv",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Inbound Transaction Count : Writes",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Inbound Transaction Count : Atomic",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Inbound Transaction Count : Other",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Inbound Transaction Count : Select Source",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_I_P2P_INSERTS",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "IRP"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "P2P Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_I_P2P_OCCUPANCY",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "IRP"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AK Egress Allocations",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0B",
- "EventName": "UNC_I_TxC_AK_INSERTS",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "IRP"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL DRS Egress Cycles Full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "IRP"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL DRS Egress Inserts",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "IRP"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL DRS Egress Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x08",
- "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "IRP"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL NCB Egress Cycles Full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x06",
- "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "IRP"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL NCB Egress Inserts",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "IRP"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL NCB Egress Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x09",
- "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "IRP"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL NCS Egress Cycles Full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x07",
- "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+ "BriefDescription": "Total Write Cache Occupancy : Any Source",
+ "EventCode": "0x0F",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "BL NCS Egress Inserts",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+ "BriefDescription": "Total Write Cache Occupancy : Snoops",
+ "EventCode": "0x0F",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
"PerPkg": "1",
+ "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+ "UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "BL NCS Egress Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0A",
- "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+ "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
+ "EventCode": "0x0f",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
"PerPkg": "1",
+ "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
+ "EventCode": "0x01",
+ "EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "BriefDescription": "No AD0 Egress Credits Stalls",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1A",
- "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Coherent Ops : CLFlush",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
+ "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x80",
"Unit": "IRP"
},
{
- "BriefDescription": "No AD1 Egress Credits Stalls",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1B",
- "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
+ "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
+ "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+ "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
+ "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0D",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+ "BriefDescription": "Coherent Ops : WbMtoI",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
+ "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0E",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "BriefDescription": "FAF RF full",
+ "EventCode": "0x17",
+ "EventName": "UNC_I_FAF_FULL",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0C",
- "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+ "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+ "EventCode": "0x18",
+ "EventName": "UNC_I_FAF_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
"Unit": "IRP"
},
{
- "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+ "BriefDescription": "Occupancy of the IRP FAF queue.",
+ "EventCode": "0x19",
+ "EventName": "UNC_I_FAF_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x71",
+ "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
"Unit": "IRP"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+ "BriefDescription": "FAF allocation -- sent to ADQ",
+ "EventCode": "0x16",
+ "EventName": "UNC_I_FAF_TRANSACTIONS",
"PerPkg": "1",
- "UMask": "0x7e",
"Unit": "IRP"
},
{
- "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+ "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.EVICTS",
"PerPkg": "1",
- "UMask": "0x74",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+ "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
"PerPkg": "1",
- "UMask": "0x72",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "M2M to iMC Bypass : Not Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
+ "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "IRP"
},
- {
- "BriefDescription": "Number of reads in which direct to core transaction was overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+ {
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
+ "EventCode": "0x1e",
+ "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ALL",
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
+ "EventCode": "0x1e",
+ "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
- "UMask": "0x0704",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.NORMAL",
+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
- "UMask": "0x0701",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.ALL",
+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+ "EventCode": "0x1e",
+ "EventName": "UNC_I_MISC0.FAST_REQ",
"PerPkg": "1",
- "UMask": "0x1C10",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL",
+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
- "UMask": "0x1C01",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+ "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
- "UMask": "0x1C02",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AD Ingress (from CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M2M_RxC_AD_INSERTS",
+ "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AD Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+ "BriefDescription": "Misc Events - Set 1 : Lost Forward",
+ "EventCode": "0x1F",
+ "EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "BL Ingress (from CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M2M_RxC_BL_INSERTS",
+ "BriefDescription": "Misc Events - Set 1 : Received Invalid",
+ "EventCode": "0x1F",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "BL Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x06",
- "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+ "BriefDescription": "Misc Events - Set 1 : Received Valid",
+ "EventCode": "0x1F",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AD Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x09",
- "EventName": "UNC_M2M_TxC_AD_INSERTS",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AD Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0A",
- "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M to iMC Bypass : Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M to iMC Bypass : Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+ "BriefDescription": "P2P Requests",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_P2P_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "P2P Requests : P2P requests from the ITC",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M to iMC Bypass : Not Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+ "BriefDescription": "P2P Occupancy",
+ "EventCode": "0x15",
+ "EventName": "UNC_I_P2P_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
+ "BriefDescription": "P2P Transactions : P2P completions",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
"PerPkg": "1",
- "UMask": "0x0101",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
+ "BriefDescription": "P2P Transactions : match if local only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
"PerPkg": "1",
- "UMask": "0x0102",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
+ "BriefDescription": "P2P Transactions : match if local and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
"PerPkg": "1",
- "UMask": "0x0104",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+ "BriefDescription": "P2P Transactions : P2P Message",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
"PerPkg": "1",
- "UMask": "0x0140",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
+ "BriefDescription": "P2P Transactions : P2P reads",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
"PerPkg": "1",
- "UMask": "0x0201",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
+ "BriefDescription": "P2P Transactions : Match if remote only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
"PerPkg": "1",
- "UMask": "0x0202",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
+ "BriefDescription": "P2P Transactions : match if remote and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
"PerPkg": "1",
- "UMask": "0x0204",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
+ "BriefDescription": "P2P Transactions : P2P Writes",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
"PerPkg": "1",
- "UMask": "0x0240",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
+ "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
"PerPkg": "1",
- "UMask": "0x0401",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
+ "UMask": "0x7e",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
+ "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
"PerPkg": "1",
- "UMask": "0x0402",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
+ "UMask": "0x74",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
+ "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
"PerPkg": "1",
- "UMask": "0x0404",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
+ "UMask": "0x72",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
+ "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
"PerPkg": "1",
- "UMask": "0x0408",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
+ "UMask": "0x78",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
+ "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
"PerPkg": "1",
- "UMask": "0x0410",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
+ "UMask": "0x71",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
+ "BriefDescription": "Snoop Responses : Hit E or S",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
- "UMaskExt": "0x05",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
+ "BriefDescription": "Snoop Responses : Hit I",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
- "UMask": "0x0801",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
+ "BriefDescription": "Snoop Responses : Hit M",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
- "UMask": "0x0802",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
+ "BriefDescription": "Snoop Responses : Miss",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
- "UMask": "0x0804",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
+ "BriefDescription": "Snoop Responses : SnpCode",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
- "UMask": "0x0808",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
+ "BriefDescription": "Snoop Responses : SnpData",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
- "UMask": "0x0810",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
+ "BriefDescription": "Snoop Responses : SnpInv",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
- "UMaskExt": "0x09",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Packet Header Matches : Mesh Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MESH",
+ "BriefDescription": "Inbound Transaction Count : Atomic",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions",
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Number Packet Header Matches : MC Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MC",
+ "BriefDescription": "Inbound Transaction Count : Other",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.",
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
+ "BriefDescription": "Inbound Transaction Count : Writes",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
+ "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
+ "BriefDescription": "AK Egress Allocations",
+ "EventCode": "0x0B",
+ "EventName": "UNC_I_TxC_AK_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
+ "BriefDescription": "BL DRS Egress Cycles Full",
+ "EventCode": "0x05",
+ "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Tracker Cycles Full : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_FULL.CH0",
+ "BriefDescription": "BL DRS Egress Inserts",
+ "EventCode": "0x02",
+ "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Tracker Cycles Full : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_FULL.CH1",
+ "BriefDescription": "BL DRS Egress Occupancy",
+ "EventCode": "0x08",
+ "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Tracker Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "BriefDescription": "BL NCB Egress Cycles Full",
+ "EventCode": "0x06",
+ "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Tracker Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "BriefDescription": "BL NCB Egress Inserts",
+ "EventCode": "0x03",
+ "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_NE.CH0",
+ "BriefDescription": "BL NCB Egress Occupancy",
+ "EventCode": "0x09",
+ "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_NE.CH1",
+ "BriefDescription": "BL NCS Egress Cycles Full",
+ "EventCode": "0x07",
+ "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "BL NCS Egress Inserts",
+ "EventCode": "0x04",
+ "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "BL NCS Egress Occupancy",
+ "EventCode": "0x0A",
+ "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.NDR",
+ "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+ "BriefDescription": "No AD0 Egress Credits Stalls",
+ "EventCode": "0x1A",
+ "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "No AD1 Egress Credits Stalls",
+ "EventCode": "0x1B",
+ "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "No BL Egress Credit Stalls",
"EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+ "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0x0D",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0x0E",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+ "BriefDescription": "Outbound Request Queue Occupancy",
+ "EventCode": "0x0C",
+ "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Outbound Request Queue Occupancy : Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x88",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x90",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0xA0",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Full : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Full : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8B",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8B",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8B",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "WPQ Flush : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "WPQ Flush : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Mirror",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x63",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x63",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x62",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x62",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Occupancy : Mirror",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x8D",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x8D",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x8D",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMaskExt": "0x0C",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
+ "BriefDescription": "M2M to iMC Bypass : Not Taken",
+ "EventCode": "0x22",
+ "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
+ "BriefDescription": "M2M to iMC Bypass : Taken",
+ "EventCode": "0x22",
+ "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
+ "BriefDescription": "M2M to iMC Bypass : Not Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT",
+ "BriefDescription": "M2M to iMC Bypass : Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT",
+ "BriefDescription": "Clockticks of the mesh to memory (M2M)",
+ "EventName": "UNC_M2M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M2M_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT",
+ "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
+ "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "EventCode": "0x60",
+ "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
+ "BriefDescription": "Number of reads in which direct to core transaction was overridden",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
+ "BriefDescription": "Distress signal asserted : DPT Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
+ "BriefDescription": "Distress signal asserted : DPT Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "EventCode": "0xBA",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xBA",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": ": Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": ": Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "BriefDescription": "Horizontal IV Ring in Use : Left",
+ "EventCode": "0xB9",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "BriefDescription": "Horizontal IV Ring in Use : Right",
+ "EventCode": "0xB9",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x704",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
+ "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x104",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+ "PerPkg": "1",
+ "UMask": "0x140",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x102",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
+ "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x101",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
+ "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x204",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x240",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x202",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x201",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x740",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ISOCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x702",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.NORMAL",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x701",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1c10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x410",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x401",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x404",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x402",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x408",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x810",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x801",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x804",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
"PerPkg": "1",
- "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x802",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x808",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1c01",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1c04",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1c02",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1c08",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Write Tracker Inserts",
+ "EventCode": "0x64",
+ "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Write Tracker Occupancy",
+ "EventCode": "0x65",
+ "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "EventCode": "0xE6",
+ "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "EventCode": "0xE6",
+ "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Number Packet Header Matches : MC Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Number Packet Header Matches : Mesh Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MESH",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "EventCode": "0x73",
+ "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x7",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x7",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
+ "EventCode": "0x6f",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x15",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 0",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 1",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels",
+ "UMask": "0x15",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - All Channels",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x15",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 0",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 1",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x15",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - All Channels",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x15",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
"PerPkg": "1",
- "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x15",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Prefetch CAM Occupancy : All Channels",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x7",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
+ "BriefDescription": ": All Channels",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x7",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "BriefDescription": ": Channel 0",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "BriefDescription": ": Channel 1",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+ "EventCode": "0x79",
+ "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
+ "EventCode": "0x78",
+ "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+ "EventCode": "0x77",
+ "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_M2M_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "AD Ingress (from CMS) Full",
+ "EventCode": "0x04",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
+ "BriefDescription": "AD Ingress (from CMS) Not Empty",
+ "EventCode": "0x03",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "AD Ingress (from CMS) Allocations",
+ "EventCode": "0x01",
+ "EventName": "UNC_M2M_RxC_AD_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "AD Ingress (from CMS) Occupancy",
+ "EventCode": "0x02",
+ "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
+ "EventCode": "0x77",
+ "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M2M_RxC_AK_WR_CMP",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "BL Ingress (from CMS) Full",
+ "EventCode": "0x08",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "BL Ingress (from CMS) Not Empty",
+ "EventCode": "0x07",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "BL Ingress (from CMS) Allocations",
+ "EventCode": "0x05",
+ "EventName": "UNC_M2M_RxC_BL_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "BL Ingress (from CMS) Occupancy",
+ "EventCode": "0x06",
+ "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
"EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
"EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
"EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
+ "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
"EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.IV",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
"EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
"EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
"EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
+ "EventName": "UNC_M2M_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
"EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
"EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
"EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : IV",
"EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
+ "PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
"EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
+ "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
"EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.IV",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
"EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
"EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
"EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
+ "EventName": "UNC_M2M_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
"EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
"EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
"EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
"EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Number AD Ingress Credits",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2M_TGR_AD_CREDITS",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Number BL Ingress Credits",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2M_TGR_BL_CREDITS",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Full : Channel 0",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_FULL.CH0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Full : Channel 1",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_FULL.CH1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Inserts : Channel 0",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Inserts : Channel 1",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "PerPkg": "1",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_NE.CH0",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_NE.CH1",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "Tracker Occupancy : Channel 0",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "Tracker Occupancy : Channel 1",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "AD Egress (to CMS) Credit Acquired",
+ "EventCode": "0x0d",
+ "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+ "EventCode": "0x0e",
+ "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "AD Egress (to CMS) Full",
+ "EventCode": "0x0c",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "AD Egress (to CMS) Not Empty",
+ "EventCode": "0x0b",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "AD Egress (to CMS) Allocations",
+ "EventCode": "0x09",
+ "EventName": "UNC_M2M_TxC_AD_INSERTS",
"PerPkg": "1",
- "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+ "EventCode": "0x0f",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "AD Egress (to CMS) Occupancy",
+ "EventCode": "0x0A",
+ "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.NDR",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "AKC Credits",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M2M_TxC_AKC_CREDITS",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "AK Egress (to CMS) Full : All",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x88",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0xa0",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x90",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
+ "BriefDescription": "AK Egress (to CMS) Not Empty : All",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
+ "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
+ "BriefDescription": "AK Egress (to CMS) Not Empty",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
+ "BriefDescription": "AK Egress (to CMS) Not Empty",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
+ "BriefDescription": "AK Egress (to CMS) Not Empty",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "AK Egress (to CMS) Allocations : All",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "AK Egress (to CMS) Occupancy : All",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "BriefDescription": "AK Egress (to CMS) Occupancy",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "BriefDescription": "AK Egress (to CMS) Occupancy",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
+ "BriefDescription": "AK Egress (to CMS) Occupancy",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "BriefDescription": "BL Egress (to CMS) Full : All",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
+ "BriefDescription": "BL Egress (to CMS) Not Empty : All",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
+ "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
+ "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
+ "BriefDescription": "BL Egress (to CMS) Allocations : All",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
+ "BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x64",
- "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Write Tracker Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x65",
- "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x73",
- "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x79",
- "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x78",
- "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x77",
- "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_M2M_RING_SRC_THRTL",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M2M_RxC_AK_WR_CMP",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x08",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "BL Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x07",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Number AD Ingress Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2M_TGR_AD_CREDITS",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Number BL Ingress Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2M_TGR_BL_CREDITS",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Egress (to CMS) Credit Acquired",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0d",
- "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0e",
- "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0c",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0b",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0f",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "AKC Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M2M_TxC_AKC_CREDITS",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ISOCH",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x0702",
- "UMaskExt": "0x07",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x0740",
- "UMaskExt": "0x07",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x1C04",
- "UMaskExt": "0x1C",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x1C08",
- "UMaskExt": "0x1C",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMaskExt": "0x1D",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMaskExt": "0x1C",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x07",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x07",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x15",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x15",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x07",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": ": All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x07",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x15",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x15",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x77",
- "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
+ "BriefDescription": "Vertical IV Ring in Use : Down",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x15",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
+ "BriefDescription": "WPQ Flush : Channel 0",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
"PerPkg": "1",
- "UMask": "0x15",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
+ "BriefDescription": "WPQ Flush : Channel 1",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
+ "BriefDescription": "Write Tracker Cycles Full : Channel 0",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
+ "BriefDescription": "Write Tracker Cycles Full : Channel 1",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
+ "BriefDescription": "Write Tracker Cycles Full : Mirror",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
+ "BriefDescription": "Write Tracker Inserts : Channel 0",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
+ "BriefDescription": "Write Tracker Inserts : Channel 1",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
+ "BriefDescription": "Write Tracker Cycles Not Empty",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
+ "BriefDescription": "Write Tracker Cycles Not Empty",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
"PerPkg": "1",
"UMask": "0x20",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
+ "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
+ "EventCode": "0x63",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
+ "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
+ "EventCode": "0x63",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
+ "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
+ "EventCode": "0x62",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
+ "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
+ "EventCode": "0x62",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
+ "BriefDescription": "Write Tracker Occupancy : Channel 0",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.ALL",
+ "BriefDescription": "Write Tracker Occupancy : Channel 1",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+ "BriefDescription": "Write Tracker Occupancy : Mirror",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+ "BriefDescription": "Write Tracker Occupancy",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+ "BriefDescription": "Write Tracker Occupancy",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+ "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+ "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+ "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+ "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8b",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8b",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8b",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "P2P Credit Occupancy : Local NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "P2P Credit Occupancy : Local NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "P2P Credit Occupancy : Remote NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "P2P Credit Occupancy : Remote NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "P2P Credit Occupancy : All",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Dedicated Credits Received : Local NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Dedicated Credits Received : Local NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Dedicated Credits Received : Remote NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Dedicated Credits Received : Remote NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x8d",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Dedicated Credits Received : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x8d",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Shared Credits Received : Local NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x8d",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Shared Credits Received : Local NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Shared Credits Received : Remote NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Shared Credits Received : Remote NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Shared Credits Received : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8f",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8f",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8f",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
+ "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
+ "EventCode": "0x01",
+ "EventName": "UNC_M2P_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M2P_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
+ "BriefDescription": "Distress signal asserted : DPT Local",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
+ "BriefDescription": "Distress signal asserted : DPT Remote",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x2d",
- "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "EventCode": "0xba",
+ "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xba",
+ "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Horizontal IV Ring in Use : Left",
+ "EventCode": "0xb9",
+ "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Horizontal IV Ring in Use : Right",
+ "EventCode": "0xb9",
+ "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
"PerPkg": "1",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
"PerPkg": "1",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
+ "PerPkg": "1",
+ "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8b",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8b",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8b",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8d",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8d",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8d",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8f",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8f",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8f",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "EventCode": "0xe6",
+ "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xba",
- "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "EventCode": "0xe6",
+ "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xba",
- "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "P2P Credit Occupancy : All",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "P2P Credit Occupancy : Local NCB",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "P2P Credit Occupancy : Local NCS",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "P2P Credit Occupancy : Remote NCB",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "P2P Credit Occupancy : Remote NCS",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Dedicated Credits Received : All",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "BriefDescription": "Dedicated Credits Received : Local NCB",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Dedicated Credits Received : Local NCS",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Dedicated Credits Received : Remote NCB",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Dedicated Credits Received : Remote NCS",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Shared Credits Received : All",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Shared Credits Received : Local NCB",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Shared Credits Received : Local NCS",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Shared Credits Received : Remote NCB",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Shared Credits Received : Remote NCS",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb9",
- "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb9",
- "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe6",
- "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
+ "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe6",
- "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
+ "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xac",
"EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xac",
"EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xac",
"EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xac",
"EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xaa",
"EventName": "UNC_M2P_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xaa",
"EventName": "UNC_M2P_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
"EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
"EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
"EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xad",
"EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xad",
"EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
"EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
"EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
"EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xab",
"EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xab",
"EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
+ "PerPkg": "1",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xab",
"EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
"EventCode": "0xab",
"EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_M2P_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
"EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xe5",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD",
+ "PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xe5",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
+ "PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xe2",
+ "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xe2",
+ "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.IV",
+ "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xe3",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xe3",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : IV",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
+ "PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xe1",
+ "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "EventCode": "0xe1",
+ "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.IV",
+ "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xe0",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "EventCode": "0xe0",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd1",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd1",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd1",
"EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd3",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd3",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd3",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd5",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd5",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd5",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
+ "EventCode": "0x2d",
+ "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd1",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd3",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd3",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd3",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd7",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd7",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xa6",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd7",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "EventCode": "0xa6",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa6",
"EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xa7",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xa7",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xa2",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xa2",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xa3",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xa3",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xa1",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xa1",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xa4",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xa4",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xa0",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xa0",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xa5",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"EventCode": "0x9c",
- "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"EventCode": "0x9c",
- "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9e",
"EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9e",
"EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x95",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x95",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x97",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x97",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
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"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
"EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
"EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
"EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
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"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
"EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
"EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
"EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x93",
"EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x93",
"EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
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"EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
- "PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
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- "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x40",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x99",
"EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x99",
"EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x91",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x91",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb0",
- "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb0",
- "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
- "PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb4",
- "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xb0",
+ "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb4",
- "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xb0",
+ "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb1",
- "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xb4",
+ "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb1",
- "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xb4",
+ "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb2",
- "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xb1",
+ "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb2",
- "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xb1",
+ "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb3",
- "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xb2",
+ "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb3",
- "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xb2",
+ "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical IV Ring in Use : Down",
+ "EventCode": "0xb3",
+ "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xb3",
+ "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb5",
"EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb5",
"EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_M2P_RING_SRC_THRTL",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "EventCode": "0xb5",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "EventCode": "0xb5",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Message Received : VLW",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
- },
- {
- "BriefDescription": "Message Received : MSI",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
- },
- {
- "BriefDescription": "Message Received : IPI",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+ "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+ "EventCode": "0xff",
+ "EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "UBOX"
},
{
"BriefDescription": "Message Received : Doorbell",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Message Received : Interrupt",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.INT_PRIO",
"PerPkg": "1",
+ "PublicDescription": "Message Received : Interrupt : Interrupts",
"UMask": "0x10",
"Unit": "UBOX"
},
{
- "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+ "BriefDescription": "Message Received : IPI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Message Received : IPI : Inter Processor Interrupts",
+ "UMask": "0x4",
"Unit": "UBOX"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDRAND",
+ "BriefDescription": "Message Received : MSI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDSEED",
+ "BriefDescription": "Message Received : VLW",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "BriefDescription": "IDI Lock/SplitLock Cycles",
+ "EventCode": "0x44",
+ "EventName": "UNC_U_LOCK_CYCLES",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
"PerPkg": "1",
@@ -25063,8 +21964,6 @@
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
"PerPkg": "1",
@@ -25072,59 +21971,39 @@
"Unit": "UBOX"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
"EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+ "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
+ "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
"EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+ "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UBOX"
- },
- {
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
- "PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
"PerPkg": "1",
@@ -25133,18 +22012,22 @@
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UBOX"
},
+ {
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "UBOX"
+ },
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
"PerPkg": "1",
@@ -25153,40 +22036,59 @@
},
{
"BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4F",
"EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x4F",
"EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
- "BriefDescription": "IDI Lock/SplitLock Cycles",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_U_LOCK_CYCLES",
+ "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
+ "EventCode": "0x45",
+ "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+ "PerPkg": "1",
+ "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.",
+ "UMask": "0x1",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDRAND",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDSEED",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "RACU Request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
+ "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker",
"Unit": "UBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json
index 281f3605881d..27fc155f1223 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json
@@ -1,16 +1,12 @@
[
{
"BriefDescription": "Clockticks of the power control unit (PCU)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -18,8 +14,6 @@
},
{
"BriefDescription": "UNC_P_DEMOTIONS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS",
"PerPkg": "1",
@@ -27,44 +21,38 @@
},
{
"BriefDescription": "Phase Shed 0 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 1 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 2 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 3 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
"Unit": "PCU"
},
{
"BriefDescription": "AVX256 Frequency Clipping",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x49",
"EventName": "UNC_P_FREQ_CLIP_AVX256",
"PerPkg": "1",
@@ -72,8 +60,6 @@
},
{
"BriefDescription": "AVX512 Frequency Clipping",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x4a",
"EventName": "UNC_P_FREQ_CLIP_AVX512",
"PerPkg": "1",
@@ -81,155 +67,137 @@
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x05",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C3 : Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x06",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
- "BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0A",
- "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+ "BriefDescription": "Number of cores in C-State : C0 and C1",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
+ "PublicDescription": "Number of cores in C-State : C0 and C1 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x09",
- "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+ "BriefDescription": "Number of cores in C-State : C3",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
+ "PublicDescription": "Number of cores in C-State : C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+ "BriefDescription": "Number of cores in C-State : C6 and C7",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
+ "PublicDescription": "Number of cores in C-State : C6 and C7 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_P_VR_HOT_CYCLES",
+ "BriefDescription": "External Prochot",
+ "EventCode": "0x0A",
+ "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State : C0 and C1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+ "BriefDescription": "Internal Prochot",
+ "EventCode": "0x09",
+ "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State : C3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+ "BriefDescription": "Total Core C State Transition Cycles",
+ "EventCode": "0x72",
+ "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State : C6 and C7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+ "BriefDescription": "VR Hot",
+ "EventCode": "0x42",
+ "EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
"Unit": "PCU"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json
index b82f11591f13..cabe29e70e79 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json
@@ -1,363 +1,246 @@
[
{
"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Entry hits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDE_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of Extended Page Directory Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Entry misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Pointer Entry hits.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDPE_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number Extended Page Directory Pointer Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Pointer Entry misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDPE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number Extended Page Directory Pointer Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.WALK_PENDING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "ITLB.FILLS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.PDE_CACHE_MISS",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
- "PDIR_COUNTER": "NA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk).",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DTLB_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x13"
},
{
"BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x11"
},
{
"BriefDescription": "Counts the number of store uops retired that miss in the second level TLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x12"
}
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 29/32] perf vendor events intel: Refresh tigerlake metrics and events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (18 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 28/32] perf vendor events intel: Refresh snowridgex events Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 30/32] perf vendor events intel: Refresh westmereep-dp events Ian Rogers
` (2 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the tigerlake metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
events are updated to version 1.08 and unused json values are
removed. The formatting changes increase consistency across the json
files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
.../pmu-events/arch/x86/tigerlake/cache.json | 210 +------------
.../arch/x86/tigerlake/floating-point.json | 27 --
.../arch/x86/tigerlake/frontend.json | 125 --------
.../pmu-events/arch/x86/tigerlake/memory.json | 77 -----
.../pmu-events/arch/x86/tigerlake/other.json | 13 -
.../arch/x86/tigerlake/pipeline.json | 287 +-----------------
.../arch/x86/tigerlake/tgl-metrics.json | 141 +++++----
.../arch/x86/tigerlake/uncore-other.json | 96 ++++--
.../arch/x86/tigerlake/virtual-memory.json | 60 ----
10 files changed, 157 insertions(+), 881 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index a5de68bcebcd..b9ed4eb0b916 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -26,7 +26,7 @@ GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core
GenuineIntel-6-55-[01234],v1.28,skylakex,core
GenuineIntel-6-86,v1.20,snowridgex,core
-GenuineIntel-6-8[CD],v1.07,tigerlake,core
+GenuineIntel-6-8[CD],v1.08,tigerlake,core
GenuineIntel-6-2C,v2,westmereep-dp,core
GenuineIntel-6-25,v3,westmereep-sp,core
GenuineIntel-6-2F,v3,westmereex,core
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
index 5ccf0edc29ac..738249a6f488 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
@@ -1,747 +1,551 @@
[
{
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
+ "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
- "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
+ "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of L1D misses that are outstanding",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "L2 cache lines filling L2",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xf1",
"EventName": "L2_LINES_IN.ALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003",
"UMask": "0x1f"
},
{
"BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xf2",
"EventName": "L2_LINES_OUT.NON_SILENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xf2",
"EventName": "L2_LINES_OUT.SILENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "L2 code requests",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of L2 code requests.",
"SampleAfterValue": "200003",
"UMask": "0xe4"
},
{
"BriefDescription": "Demand Data Read access L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
"SampleAfterValue": "200003",
"UMask": "0xe1"
},
{
"BriefDescription": "RFO requests to L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
"SampleAfterValue": "200003",
"UMask": "0xe2"
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
"SampleAfterValue": "200003",
"UMask": "0xc4"
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
"SampleAfterValue": "200003",
"UMask": "0x24"
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0xc1"
},
{
"BriefDescription": "Demand Data Read miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
"SampleAfterValue": "200003",
"UMask": "0x21"
},
{
"BriefDescription": "Read requests with true-miss in L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.",
"SampleAfterValue": "200003",
"UMask": "0x3f"
},
{
"BriefDescription": "All accesses to L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.",
"SampleAfterValue": "200003",
"UMask": "0xff"
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0xc2"
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x22"
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
"UMask": "0xc8"
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
"UMask": "0x28"
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L2_WB",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "Cycles when L1D is locked",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
"UMask": "0x41"
},
{
- "BriefDescription": "All retired load instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Retired load instructions.",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.",
+ "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
"SampleAfterValue": "1000003",
"UMask": "0x81"
},
{
- "BriefDescription": "All retired store instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Retired store instructions.",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.",
+ "PublicDescription": "Counts all retired store instructions.",
"SampleAfterValue": "1000003",
"UMask": "0x82"
},
{
"BriefDescription": "All retired memory instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ANY",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired memory instructions - loads and stores.",
"SampleAfterValue": "1000003",
"UMask": "0x83"
},
{
"BriefDescription": "Retired load instructions with locked access.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with locked access.",
"SampleAfterValue": "100007",
"UMask": "0x21"
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x41"
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x11"
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x12"
},
{
"BriefDescription": "Snoop hit a modified(HITM) or clean line(HIT_W_FWD) in another on-pkg core which forwarded the data back due to a retired load instruction.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD).",
"SampleAfterValue": "20011",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Snoop hit without forwarding in another on-pkg core due to a retired load instruction, data was supplied by the L3.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD).",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
{
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
"SampleAfterValue": "100021",
"UMask": "0x10"
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
"SampleAfterValue": "100021",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
"SampleAfterValue": "50021",
"UMask": "0x20"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Demand and prefetch data reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Any memory transaction that reached the SQ.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Demand Data Read transactions pending for off-core. Highly correlated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles the superQ cannot take any more entries.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SQ_FULL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"SampleAfterValue": "100003",
"UMask": "0x4"
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json
index 978b494c7458..655342dadac6 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json
@@ -1,99 +1,72 @@
[
{
"BriefDescription": "Counts all microcode FP assists.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.FP",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all microcode Floating Point assists.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json b/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json
index ccdd8fd99556..23b8528590b3 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json
@@ -1,476 +1,351 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.COUNT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x11",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x14",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x500106",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
"MSRValue": "0x508006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
"MSRValue": "0x501006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x500206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
"MSRValue": "0x510006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x100206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
"MSRValue": "0x502006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
"MSRValue": "0x500406",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
"MSRValue": "0x520006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x504006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
"MSRValue": "0x500806",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x15",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
"SampleAfterValue": "500009",
"UMask": "0x4"
},
{
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles DSB is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Number of switches from DSB or MITE to the MS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"SampleAfterValue": "100003",
"UMask": "0x30"
},
{
"BriefDescription": "Uops delivered to IDQ while MS is busy",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
"SampleAfterValue": "100003",
"UMask": "0x30"
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/memory.json b/tools/perf/pmu-events/arch/x86/tigerlake/memory.json
index 6071794cbd32..8848fcbcc35c 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/memory.json
@@ -1,293 +1,216 @@
[
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
{
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Demand Data Read requests who miss L3 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Demand Data Read requests who miss L3 cache.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Number of times an RTM execution aborted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM abort was triggered.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM commit succeeded.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_READ",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
"SampleAfterValue": "100003",
"UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
index 3ed22dbd0982..55f3048bcfa6 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
@@ -1,47 +1,34 @@
[
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
"SampleAfterValue": "200003",
"UMask": "0x7"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
"UMask": "0x18"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
index 1f273144f8e8..9d43decd75ec 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
@@ -1,675 +1,498 @@
[
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"SampleAfterValue": "1000003",
"UMask": "0x9"
},
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
"SampleAfterValue": "100003",
"UMask": "0x7"
},
{
"BriefDescription": "All branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all branch instructions retired.",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x11"
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts not taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x10"
},
{
"BriefDescription": "Taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x1"
},
{
"BriefDescription": "Far branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts far branch instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Indirect near branch instructions retired (excluding returns)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts both direct and indirect near call instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"BriefDescription": "Return instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts return instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"BriefDescription": "Taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x20"
},
{
"BriefDescription": "All mispredicted branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
"SampleAfterValue": "50021"
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts mispredicted conditional branch instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x11"
},
{
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
"SampleAfterValue": "50021",
"UMask": "0x10"
},
{
- "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x1"
},
{
"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
"SampleAfterValue": "50021",
"UMask": "0x80"
},
{
"BriefDescription": "Mispredicted indirect CALL instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
"SampleAfterValue": "50021",
"UMask": "0x2"
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
"SampleAfterValue": "50021",
"UMask": "0x20"
},
{
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"SampleAfterValue": "25003",
"UMask": "0x2"
},
{
"BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PEBScounters": "34",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
"SampleAfterValue": "25003",
"UMask": "0x1"
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "8",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "12",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0xc"
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "20",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x14"
},
{
"BriefDescription": "Total execution stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.BOUND_ON_LOADS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x21"
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.",
"SampleAfterValue": "1000003",
"UMask": "0x80"
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
"SampleAfterValue": "500009",
"UMask": "0x1"
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003"
},
{
- "BriefDescription": "Number of all retired NOP instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Retired NOP instructions.",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.NOP",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Counts all retired NOP or ENDBR32/64 instructions",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0d",
"EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"SampleAfterValue": "500009",
"UMask": "0x80"
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.RECOVERY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
"SampleAfterValue": "500009",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots where uops got dropped",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.UOP_DROPPING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.COUNT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of machine clears (nukes) of any type.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.LBR_INSERTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.PAUSE_INST",
"PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
@@ -678,391 +501,289 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SB",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SCOREBOARD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5e",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5e",
"EventName": "RS_EVENTS.EMPTY_END",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
"SampleAfterValue": "10000003",
"UMask": "0x2"
},
{
"BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
"SampleAfterValue": "10000003",
"UMask": "0x8"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 3",
"EventName": "TOPDOWN.SLOTS",
- "PEBScounters": "35",
"PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
"SampleAfterValue": "10000003",
"UMask": "0x4"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.SLOTS_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
"SampleAfterValue": "10000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UOPS_DECODED.DEC0",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Uops exclusively fetched by decoder 0",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_0",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 1",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of uops executed on port 2 and 3",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_2_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of uops executed on port 4 and 9",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_4_9",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Number of uops executed on port 5",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_5",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of uops executed on port 6",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_6",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
"SampleAfterValue": "2000003",
"UMask": "0x40"
},
{
"BriefDescription": "Number of uops executed on port 7 and 8",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_7_8",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"BriefDescription": "Number of uops executed on the core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops executed from any thread.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.THREAD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.X87",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of x87 uops executed.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Uops that RAT issues to RS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Retirement slots used.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the retirement slots used each cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts cycles without actually retired uops.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "10",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.",
+ "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
}
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json
index 79b8b101b68f..7e22a9127156 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json
@@ -41,7 +41,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
"MetricName": "tma_mispredicts_resteers",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -49,7 +49,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
- "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+ "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
"MetricName": "tma_clears_resteers",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -143,7 +143,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -159,7 +159,7 @@
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + (5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@) / SLOTS",
+ "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_backend_bound",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
@@ -167,7 +167,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -213,7 +213,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
+ "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -245,7 +245,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + L1D_PEND_MISS.FB_FULL_PERIODS)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l2_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
@@ -261,7 +261,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "((49 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (48 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+ "MetricExpr": "(49 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 48 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -269,7 +269,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "(48 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+ "MetricExpr": "48 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@@ -277,7 +277,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "(17.5 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+ "MetricExpr": "17.5 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -293,7 +293,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)",
+ "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -325,7 +325,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -333,7 +333,7 @@
},
{
"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "(54 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
+ "MetricExpr": "54 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
"MetricName": "tma_false_sharing",
"PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
@@ -395,7 +395,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
+ "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS)",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -508,7 +508,7 @@
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_retiring",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS",
@@ -625,7 +625,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "((tma_retiring * SLOTS) / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "tma_retiring * SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -655,19 +655,19 @@
},
{
"BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "Memory_Bandwidth"
},
{
"BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
"MetricGroup": "Mem;MemoryLat;Offcore",
"MetricName": "Memory_Latency"
},
{
"BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
+ "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
"MetricGroup": "Mem;MemoryTLB;Offcore",
"MetricName": "Memory_Data_TLBs"
},
@@ -697,13 +697,13 @@
},
{
"BriefDescription": "Uops Per Instruction",
- "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
+ "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Ret;Retire",
"MetricName": "UPI"
},
{
"BriefDescription": "Instruction per taken branch",
- "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW",
"MetricName": "UpTB"
},
@@ -727,7 +727,7 @@
},
{
"BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
- "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
+ "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
"MetricGroup": "SMT;tma_L1_group",
"MetricName": "Slots_Utilization"
},
@@ -746,26 +746,26 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "FP_Arith_Utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
- "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
+ "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
"MetricGroup": "Cor;SMT",
"MetricName": "Core_Bound_Likely"
},
@@ -813,13 +813,13 @@
},
{
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
"MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP"
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
"MetricGroup": "Flops;InsType",
"MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@@ -873,7 +873,7 @@
},
{
"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "(tma_retiring * SLOTS) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+ "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
"MetricGroup": "Pipeline;Ret",
"MetricName": "Retire"
},
@@ -927,7 +927,7 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts",
"MetricName": "Branch_Misprediction_Cost"
},
@@ -975,55 +975,55 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI_Load"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem;Offcore",
"MetricName": "L2MPKI_All"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2MPKI_Load"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_All"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_Load"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "FB_HPKI"
},
@@ -1036,25 +1036,25 @@
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "L3_Cache_Access_BW"
},
@@ -1084,19 +1084,19 @@
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -1130,7 +1130,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@@ -1148,7 +1148,7 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+ "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
@@ -1166,56 +1166,65 @@
},
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C8 residency percent per package",
- "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C8_Pkg_Residency"
+ "MetricName": "C8_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C9 residency percent per package",
- "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C9_Pkg_Residency"
+ "MetricName": "C9_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C10 residency percent per package",
- "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C10_Pkg_Residency"
+ "MetricName": "C10_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
index 734b1845c8e2..e2ea5ccfe3bc 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
@@ -1,65 +1,109 @@
[
+ {
+ "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "EventCode": "0x84",
+ "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of coherent read requests sent to memory controller that were issued by any core.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_DAT_REQUESTS.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_REQUESTS.RD",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
{
"BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
- "PublicDescription": "UNC_ARB_TRK_OCCUPANCY.ALL",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "ARB"
},
+ {
+ "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "UNC_CLOCK.SOCKET",
+ "EventCode": "0xff",
+ "EventName": "UNC_CLOCK.SOCKET",
+ "PerPkg": "1",
+ "Unit": "CLOCK"
+ },
{
"BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
- "Counter": "1",
- "CounterType": "FREERUN",
"EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
"PerPkg": "1",
- "PublicDescription": "UNC_MC0_RDCAS_COUNT_FREERUN",
- "Unit": "h_imc"
+ "Unit": "imc"
},
{
"BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
- "CounterType": "FREERUN",
"EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
"PerPkg": "1",
- "PublicDescription": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
- "Unit": "h_imc"
+ "Unit": "imc"
},
{
"BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
- "Counter": "2",
- "CounterType": "FREERUN",
"EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
"PerPkg": "1",
- "PublicDescription": "UNC_MC0_WRCAS_COUNT_FREERUN",
- "Unit": "h_imc"
+ "Unit": "imc"
},
{
"BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
- "Counter": "4",
- "CounterType": "FREERUN",
"EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
"PerPkg": "1",
- "PublicDescription": "UNC_MC1_RDCAS_COUNT_FREERUN",
- "Unit": "h_imc"
+ "Unit": "imc"
},
{
"BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
- "Counter": "3",
- "CounterType": "FREERUN",
"EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
"PerPkg": "1",
- "PublicDescription": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
- "Unit": "h_imc"
+ "Unit": "imc"
},
{
"BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
- "Counter": "5",
- "CounterType": "FREERUN",
"EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
"PerPkg": "1",
- "PublicDescription": "UNC_MC1_WRCAS_COUNT_FREERUN",
- "Unit": "h_imc"
+ "Unit": "imc"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json
index fd364abf8002..adb2f6b3e77c 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json
@@ -1,223 +1,163 @@
[
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
"UMask": "0xe"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xbd",
"EventName": "TLB_FLUSH.DTLB_THREAD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "STLB flush attempts",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xbd",
"EventName": "TLB_FLUSH.STLB_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
"SampleAfterValue": "100007",
"UMask": "0x20"
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 30/32] perf vendor events intel: Refresh westmereep-dp events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (19 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 29/32] perf vendor events intel: Refresh tigerlake metrics and events Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 31/32] perf vendor events intel: Refresh westmereep-sp events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 32/32] perf vendor events intel: Refresh westmereex events Ian Rogers
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the westmereep-dp events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged, unused json values are removed and the
version number bumped to v3 to match the perfmon mapfile.csv. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
.../arch/x86/westmereep-dp/cache.json | 445 ------------------
.../x86/westmereep-dp/floating-point.json | 28 --
.../arch/x86/westmereep-dp/frontend.json | 3 -
.../arch/x86/westmereep-dp/memory.json | 137 ------
.../arch/x86/westmereep-dp/other.json | 22 -
.../arch/x86/westmereep-dp/pipeline.json | 129 +----
.../x86/westmereep-dp/virtual-memory.json | 21 -
8 files changed, 6 insertions(+), 781 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index b9ed4eb0b916..a515d9594ced 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -27,7 +27,7 @@ GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core
GenuineIntel-6-55-[01234],v1.28,skylakex,core
GenuineIntel-6-86,v1.20,snowridgex,core
GenuineIntel-6-8[CD],v1.08,tigerlake,core
-GenuineIntel-6-2C,v2,westmereep-dp,core
+GenuineIntel-6-2C,v3,westmereep-dp,core
GenuineIntel-6-25,v3,westmereep-sp,core
GenuineIntel-6-2F,v3,westmereex,core
AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
index 37ed2742fec6..5c897da3cd6b 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles L1D locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Cycles L1D and L2 locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1D cache lines replaced in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_EVICT",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1D cache lines allocated in the M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_REPL",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1D snoop eviction of cache lines in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_SNOOP_EVICT",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1 data cache lines allocated",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.REPL",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
- "Counter": "0,1",
"EventCode": "0x52",
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "L1D hardware prefetch misses",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.MISS",
"SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.REQUESTS",
"SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests triggered",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.TRIGGERS",
"SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.E_STATE",
"SampleAfterValue": "100000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.I_STATE",
"SampleAfterValue": "100000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "All L1 writebacks to L2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.MESI",
"SampleAfterValue": "100000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.M_STATE",
"SampleAfterValue": "100000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.S_STATE",
"SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "All L2 data requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.ANY",
"SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "L2 data demand loads in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "L2 data demand loads in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
},
{
"BriefDescription": "L2 data demand requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -153,7 +134,6 @@
},
{
"BriefDescription": "L2 data demand loads in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -161,7 +141,6 @@
},
{
"BriefDescription": "L2 data demand loads in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -169,7 +148,6 @@
},
{
"BriefDescription": "L2 data prefetches in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -177,7 +155,6 @@
},
{
"BriefDescription": "L2 data prefetches in the I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
},
{
"BriefDescription": "All L2 data prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
},
{
"BriefDescription": "L2 data prefetches in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
},
{
"BriefDescription": "L2 data prefetches in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -209,7 +183,6 @@
},
{
"BriefDescription": "L2 lines alloacated",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ANY",
"SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
},
{
"BriefDescription": "L2 lines allocated in the E state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E_STATE",
"SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
},
{
"BriefDescription": "L2 lines allocated in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S_STATE",
"SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
},
{
"BriefDescription": "L2 lines evicted",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.ANY",
"SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
},
{
"BriefDescription": "L2 lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100000",
@@ -249,7 +218,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100000",
@@ -257,7 +225,6 @@
},
{
"BriefDescription": "L2 lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
"SampleAfterValue": "100000",
@@ -265,7 +232,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
"SampleAfterValue": "100000",
@@ -273,7 +239,6 @@
},
{
"BriefDescription": "L2 instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCHES",
"SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
},
{
"BriefDescription": "L2 instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_HIT",
"SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
},
{
"BriefDescription": "L2 instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_MISS",
"SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
},
{
"BriefDescription": "L2 load hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_HIT",
"SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
},
{
"BriefDescription": "L2 load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_MISS",
"SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
},
{
"BriefDescription": "L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LOADS",
"SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
},
{
"BriefDescription": "All L2 misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
},
{
"BriefDescription": "All L2 prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCHES",
"SampleAfterValue": "200000",
@@ -337,7 +295,6 @@
},
{
"BriefDescription": "L2 prefetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_HIT",
"SampleAfterValue": "200000",
@@ -345,7 +302,6 @@
},
{
"BriefDescription": "L2 prefetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_MISS",
"SampleAfterValue": "200000",
@@ -353,7 +309,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200000",
@@ -361,7 +316,6 @@
},
{
"BriefDescription": "L2 RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFOS",
"SampleAfterValue": "200000",
@@ -369,7 +323,6 @@
},
{
"BriefDescription": "L2 RFO hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200000",
@@ -377,7 +330,6 @@
},
{
"BriefDescription": "L2 RFO misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200000",
@@ -385,7 +337,6 @@
},
{
"BriefDescription": "All L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.ANY",
"SampleAfterValue": "200000",
@@ -393,7 +344,6 @@
},
{
"BriefDescription": "L2 fill transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.FILL",
"SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
},
{
"BriefDescription": "L2 instruction fetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.IFETCH",
"SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
},
{
"BriefDescription": "L1D writeback to L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.L1D_WB",
"SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
},
{
"BriefDescription": "L2 Load transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.LOAD",
"SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
},
{
"BriefDescription": "L2 prefetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.PREFETCH",
"SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
},
{
"BriefDescription": "L2 RFO transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.RFO",
"SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
},
{
"BriefDescription": "L2 writeback to LLC transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.WB",
"SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.E_STATE",
"SampleAfterValue": "100000",
@@ -457,7 +400,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.HIT",
"SampleAfterValue": "100000",
@@ -465,7 +407,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.I_STATE",
"SampleAfterValue": "100000",
@@ -473,7 +414,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.MESI",
"SampleAfterValue": "100000",
@@ -481,7 +421,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.M_STATE",
"SampleAfterValue": "100000",
@@ -489,7 +428,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.S_STATE",
"SampleAfterValue": "100000",
@@ -497,7 +435,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.HIT",
"SampleAfterValue": "100000",
@@ -505,7 +442,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.I_STATE",
"SampleAfterValue": "100000",
@@ -513,7 +449,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.MESI",
"SampleAfterValue": "100000",
@@ -521,7 +456,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.M_STATE",
"SampleAfterValue": "100000",
@@ -529,7 +463,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.S_STATE",
"SampleAfterValue": "100000",
@@ -537,7 +470,6 @@
},
{
"BriefDescription": "Longest latency cache miss",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100000",
@@ -545,7 +477,6 @@
},
{
"BriefDescription": "Longest latency cache reference",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200000",
@@ -553,18 +484,15 @@
},
{
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
"MSRIndex": "0x3F6",
- "MSRValue": "0x0",
"PEBS": "2",
"SampleAfterValue": "2000000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
"MSRIndex": "0x3F6",
@@ -575,7 +503,6 @@
},
{
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
"MSRIndex": "0x3F6",
@@ -586,7 +513,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
"MSRIndex": "0x3F6",
@@ -597,7 +523,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
"MSRIndex": "0x3F6",
@@ -608,7 +533,6 @@
},
{
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
"MSRIndex": "0x3F6",
@@ -619,7 +543,6 @@
},
{
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
"MSRIndex": "0x3F6",
@@ -630,7 +553,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
"MSRIndex": "0x3F6",
@@ -641,7 +563,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
"MSRIndex": "0x3F6",
@@ -652,7 +573,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
"MSRIndex": "0x3F6",
@@ -663,7 +583,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
"MSRIndex": "0x3F6",
@@ -674,7 +593,6 @@
},
{
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
"MSRIndex": "0x3F6",
@@ -685,7 +603,6 @@
},
{
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
"MSRIndex": "0x3F6",
@@ -696,7 +613,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
"MSRIndex": "0x3F6",
@@ -707,7 +623,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
"MSRIndex": "0x3F6",
@@ -718,7 +633,6 @@
},
{
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LOADS",
"PEBS": "1",
@@ -727,7 +641,6 @@
},
{
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.STORES",
"PEBS": "1",
@@ -736,7 +649,6 @@
},
{
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -745,7 +657,6 @@
},
{
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
"PEBS": "1",
@@ -754,7 +665,6 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
@@ -763,7 +673,6 @@
},
{
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -772,7 +681,6 @@
},
{
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
"PEBS": "1",
@@ -781,7 +689,6 @@
},
{
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
"PEBS": "1",
@@ -790,7 +697,6 @@
},
{
"BriefDescription": "All offcore requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY",
"SampleAfterValue": "100000",
@@ -798,7 +704,6 @@
},
{
"BriefDescription": "Offcore read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY.READ",
"SampleAfterValue": "100000",
@@ -806,7 +711,6 @@
},
{
"BriefDescription": "Offcore RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY.RFO",
"SampleAfterValue": "100000",
@@ -814,7 +718,6 @@
},
{
"BriefDescription": "Offcore demand code read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
"SampleAfterValue": "100000",
@@ -822,7 +725,6 @@
},
{
"BriefDescription": "Offcore demand data read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
"SampleAfterValue": "100000",
@@ -830,7 +732,6 @@
},
{
"BriefDescription": "Offcore demand RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
"SampleAfterValue": "100000",
@@ -838,7 +739,6 @@
},
{
"BriefDescription": "Offcore L1 data cache writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
"SampleAfterValue": "100000",
@@ -906,7 +806,6 @@
},
{
"BriefDescription": "Offcore requests blocked due to Super Queue full",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
"SampleAfterValue": "100000",
@@ -914,1877 +813,1536 @@
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x111",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x211",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x411",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x711",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x144",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x244",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x444",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x744",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x50ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7fff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xffff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x122",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x222",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x422",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x722",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x108",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x208",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x408",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x177",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x277",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x477",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x777",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x133",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x233",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x433",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x733",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x203",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x403",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x101",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x201",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x401",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x701",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x704",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x102",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x202",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x402",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x702",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x180",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x280",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x480",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x780",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f50",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff50",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x150",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x250",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x450",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x750",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x850",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x710",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x140",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x240",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x440",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x740",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x120",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x220",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x420",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x720",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7f70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xff70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x170",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x270",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x470",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x770",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Super Queue LRU hints sent to LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.LRU_HINTS",
"SampleAfterValue": "2000000",
@@ -2792,7 +2350,6 @@
},
{
"BriefDescription": "Super Queue lock splits across a cache line",
- "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "2000000",
@@ -2800,7 +2357,6 @@
},
{
"BriefDescription": "Loads delayed with at-Retirement block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.AT_RET",
"SampleAfterValue": "200000",
@@ -2808,7 +2364,6 @@
},
{
"BriefDescription": "Cacheable loads delayed with L1D block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.L1D_BLOCK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json
index 666e466d351c..c03f8990fa82 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "X87 Floating point assists (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.ALL",
"PEBS": "1",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.INPUT",
"PEBS": "1",
@@ -19,7 +17,6 @@
},
{
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.OUTPUT",
"PEBS": "1",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "MMX Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "SSE2 integer Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "SSE* FP double precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "SSE and SSE2 FP Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "SSE FP packed Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "SSE FP scalar Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "SSE* FP single precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Computational floating-point operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "All Floating Point to and from MMX transitions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Transitions from MMX to Floating Point instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Transitions from Floating Point to MMX instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "128 bit SIMD integer pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "128 bit SIMD integer arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "128 bit SIMD integer logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "128 bit SIMD integer multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "128 bit SIMD integer unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
index c561ac24d91d..f7f28510e3ae 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Macro-fused instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Two Uop instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json
index 7e529b367c21..7085c3307c91 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Misaligned store references",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.STORE",
"SampleAfterValue": "200000",
@@ -9,749 +8,613 @@
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x30ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf8ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x20ff",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf850",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xf870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
index 67bc34984fa8..488274980564 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "ES segment renames",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "I/O transactions",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1I instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1I instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1I Instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "Large ITLB hit",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "Loads that partially overlap an earlier store",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
"SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "All loads dispatched",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "Loads dispatched from the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "Loads dispatched that bypass the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "Loads dispatched from stage 305",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "False dependencies due to partial address aliasing",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "All Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "Segment rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "Snoop code requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.CODE",
"SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "Snoop data requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.DATA",
"SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "Snoop invalidate requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
"SampleAfterValue": "100000",
@@ -190,7 +172,6 @@
},
{
"BriefDescription": "Thread responded HIT to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
@@ -198,7 +179,6 @@
},
{
"BriefDescription": "Thread responded HITE to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
@@ -206,7 +186,6 @@
},
{
"BriefDescription": "Thread responded HITM to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
@@ -214,7 +193,6 @@
},
{
"BriefDescription": "Super Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
index 403fb2b87fc4..a29ed3522779 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles the divider is busy",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Divide Operations executed",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -20,7 +18,6 @@
},
{
"BriefDescription": "Multiply operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.MUL",
"SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "BACLEAR asserted with bad target address",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.BAD_TARGET",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "BACLEAR asserted, regardless of cause",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.CLEAR",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "Instruction queue forced BACLEAR",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "BACLEAR_FORCE_IQ",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "Branch instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ANY",
"SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "Conditional branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.COND",
"SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT",
"SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Unconditional call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "Indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "Indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "Call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NEAR_CALLS",
"SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "All non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NON_CALLS",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "Indirect return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.RETURN_NEAR",
"SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "Taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "Retired branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -173,7 +152,6 @@
},
{
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -182,7 +160,6 @@
},
{
"BriefDescription": "Retired near call instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -191,7 +168,6 @@
},
{
"BriefDescription": "Mispredicted branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ANY",
"SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
},
{
"BriefDescription": "Mispredicted conditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.COND",
"SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
},
{
"BriefDescription": "Mispredicted unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT",
"SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
},
{
"BriefDescription": "Mispredicted indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
},
{
"BriefDescription": "Mispredicted indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
},
{
"BriefDescription": "Mispredicted call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
"SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NON_CALLS",
"SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
},
{
"BriefDescription": "Mispredicted return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
"SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
},
{
"BriefDescription": "Mispredicted taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN",
"SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
},
{
"BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -280,7 +246,6 @@
},
{
"BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -289,7 +254,6 @@
},
{
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -298,15 +262,11 @@
},
{
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 3",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.REF",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_P",
"SampleAfterValue": "100000",
@@ -314,33 +274,25 @@
},
{
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 2",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Total CPU cycles",
- "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
"Invert": "1",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Any Instruction Length Decoder stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.ANY",
"SampleAfterValue": "2000000",
@@ -348,7 +300,6 @@
},
{
"BriefDescription": "Instruction Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@@ -356,7 +307,6 @@
},
{
"BriefDescription": "Length Change Prefix stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000000",
@@ -364,7 +314,6 @@
},
{
"BriefDescription": "Stall cycles due to BPU MRU bypass",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.MRU",
"SampleAfterValue": "2000000",
@@ -372,7 +321,6 @@
},
{
"BriefDescription": "Regen stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.REGEN",
"SampleAfterValue": "2000000",
@@ -380,7 +328,6 @@
},
{
"BriefDescription": "Instructions that must be decoded by decoder 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "INST_DECODED.DEC0",
"SampleAfterValue": "2000000",
@@ -388,7 +335,6 @@
},
{
"BriefDescription": "Instructions written to instruction queue.",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INST_QUEUE_WRITES",
"SampleAfterValue": "2000000",
@@ -396,7 +342,6 @@
},
{
"BriefDescription": "Cycles instructions are written to the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "INST_QUEUE_WRITE_CYCLES",
"SampleAfterValue": "2000000",
@@ -404,15 +349,11 @@
},
{
"BriefDescription": "Instructions retired (fixed counter)",
- "Counter": "Fixed counter 1",
- "EventCode": "0x0",
"EventName": "INST_RETIRED.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@@ -421,7 +362,6 @@
},
{
"BriefDescription": "Retired MMX instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.MMX",
"PEBS": "1",
@@ -430,7 +370,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -441,7 +380,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -452,7 +390,6 @@
},
{
"BriefDescription": "Retired floating-point operations (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PEBS": "1",
@@ -461,7 +398,6 @@
},
{
"BriefDescription": "Load operations conflicting with software prefetches",
- "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE",
"SampleAfterValue": "200000",
@@ -469,7 +405,6 @@
},
{
"BriefDescription": "Cycles when uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.ACTIVE",
@@ -478,7 +413,6 @@
},
{
"BriefDescription": "Cycles no uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.INACTIVE",
@@ -488,7 +422,6 @@
},
{
"BriefDescription": "Loops that can't stream from the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "LSD_OVERFLOW",
"SampleAfterValue": "2000000",
@@ -496,7 +429,6 @@
},
{
"BriefDescription": "Cycles machine clear asserted",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "20000",
@@ -504,7 +436,6 @@
},
{
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEM_ORDER",
"SampleAfterValue": "20000",
@@ -512,7 +443,6 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20000",
@@ -520,7 +450,6 @@
},
{
"BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -528,7 +457,6 @@
},
{
"BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
@@ -536,7 +464,6 @@
},
{
"BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
@@ -544,7 +471,6 @@
},
{
"BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
@@ -552,7 +478,6 @@
},
{
"BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
@@ -560,7 +485,6 @@
},
{
"BriefDescription": "Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -568,7 +492,6 @@
},
{
"BriefDescription": "FPU control word write stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.FPCW",
"SampleAfterValue": "2000000",
@@ -576,7 +499,6 @@
},
{
"BriefDescription": "Load buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LOAD",
"SampleAfterValue": "2000000",
@@ -584,7 +506,6 @@
},
{
"BriefDescription": "MXCSR rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MXCSR",
"SampleAfterValue": "2000000",
@@ -592,7 +513,6 @@
},
{
"BriefDescription": "Other Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OTHER",
"SampleAfterValue": "2000000",
@@ -600,7 +520,6 @@
},
{
"BriefDescription": "ROB full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB_FULL",
"SampleAfterValue": "2000000",
@@ -608,7 +527,6 @@
},
{
"BriefDescription": "Reservation Station full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS_FULL",
"SampleAfterValue": "2000000",
@@ -616,7 +534,6 @@
},
{
"BriefDescription": "Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.STORE",
"SampleAfterValue": "2000000",
@@ -624,7 +541,6 @@
},
{
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
"PEBS": "1",
@@ -633,7 +549,6 @@
},
{
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
"PEBS": "1",
@@ -642,7 +557,6 @@
},
{
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
"PEBS": "1",
@@ -651,7 +565,6 @@
},
{
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
"PEBS": "1",
@@ -660,7 +573,6 @@
},
{
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
"PEBS": "1",
@@ -669,7 +581,6 @@
},
{
"BriefDescription": "Stack pointer instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_FOLDING",
"SampleAfterValue": "2000000",
@@ -677,7 +588,6 @@
},
{
"BriefDescription": "Stack pointer sync operations",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_SYNC",
"SampleAfterValue": "2000000",
@@ -685,7 +595,6 @@
},
{
"BriefDescription": "Uops decoded by Microcode Sequencer",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -694,7 +603,6 @@
},
{
"BriefDescription": "Cycles no Uops are decoded",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -705,7 +613,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -715,7 +622,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -725,7 +631,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -737,7 +642,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -749,7 +653,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -760,7 +663,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -770,7 +672,6 @@
},
{
"BriefDescription": "Uops executed on port 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT0",
"SampleAfterValue": "2000000",
@@ -778,7 +679,6 @@
},
{
"BriefDescription": "Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015",
"SampleAfterValue": "2000000",
@@ -786,7 +686,6 @@
},
{
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -796,7 +695,6 @@
},
{
"BriefDescription": "Uops executed on port 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT1",
"SampleAfterValue": "2000000",
@@ -805,7 +703,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops issued on ports 2, 3 or 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT234_CORE",
"SampleAfterValue": "2000000",
@@ -814,7 +711,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 2 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT2_CORE",
"SampleAfterValue": "2000000",
@@ -823,7 +719,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 3 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT3_CORE",
"SampleAfterValue": "2000000",
@@ -832,7 +727,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 4 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT4_CORE",
"SampleAfterValue": "2000000",
@@ -840,7 +734,6 @@
},
{
"BriefDescription": "Uops executed on port 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT5",
"SampleAfterValue": "2000000",
@@ -848,7 +741,6 @@
},
{
"BriefDescription": "Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000000",
@@ -857,7 +749,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops were issued on any thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -868,7 +759,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops were issued on either thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -877,7 +767,6 @@
},
{
"BriefDescription": "Fused Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.FUSED",
"SampleAfterValue": "2000000",
@@ -885,7 +774,6 @@
},
{
"BriefDescription": "Cycles no Uops were issued",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -895,7 +783,6 @@
},
{
"BriefDescription": "Cycles Uops are being retired",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -905,7 +792,6 @@
},
{
"BriefDescription": "Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "1",
@@ -914,7 +800,6 @@
},
{
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PEBS": "1",
@@ -923,7 +808,6 @@
},
{
"BriefDescription": "Retirement slots used (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -932,7 +816,6 @@
},
{
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -943,7 +826,6 @@
},
{
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -954,7 +836,6 @@
},
{
"BriefDescription": "Uop unfusions due to FP exceptions",
- "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UOP_UNFUSION",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
index 8099e6700e31..ef635bff1522 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "DTLB load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "DTLB load miss large page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "DTLB load miss caused by low part of address",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "DTLB second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "DTLB load miss page walks complete",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "DTLB load miss page walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
"SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "DTLB misses",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "DTLB miss large page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "DTLB misses casued by low part of address",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "DTLB first level misses but second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "DTLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "DTLB miss page walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "Extended Page Table walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "ITLB flushes",
- "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "ITLB miss",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "ITLB miss large page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "ITLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "ITLB miss page walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
@@ -145,7 +127,6 @@
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
@@ -154,7 +135,6 @@
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
@@ -163,7 +143,6 @@
},
{
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 31/32] perf vendor events intel: Refresh westmereep-sp events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (20 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 30/32] perf vendor events intel: Refresh westmereep-dp events Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
2022-12-15 6:55 ` [PATCH v1 32/32] perf vendor events intel: Refresh westmereex events Ian Rogers
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the westmereep-sp events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/westmereep-sp/cache.json | 517 ------------------
.../x86/westmereep-sp/floating-point.json | 28 -
.../arch/x86/westmereep-sp/frontend.json | 3 -
.../arch/x86/westmereep-sp/memory.json | 134 -----
.../arch/x86/westmereep-sp/other.json | 22 -
.../arch/x86/westmereep-sp/pipeline.json | 129 +----
.../x86/westmereep-sp/virtual-memory.json | 18 -
7 files changed, 5 insertions(+), 846 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
index c5f33fe2a3ce..e00c301640f3 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles L1D locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Cycles L1D and L2 locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1D cache lines replaced in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_EVICT",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1D cache lines allocated in the M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_REPL",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1D snoop eviction of cache lines in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_SNOOP_EVICT",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1 data cache lines allocated",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.REPL",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
- "Counter": "0,1",
"EventCode": "0x52",
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "L1D hardware prefetch misses",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.MISS",
"SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.REQUESTS",
"SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests triggered",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.TRIGGERS",
"SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.E_STATE",
"SampleAfterValue": "100000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.I_STATE",
"SampleAfterValue": "100000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "All L1 writebacks to L2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.MESI",
"SampleAfterValue": "100000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.M_STATE",
"SampleAfterValue": "100000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.S_STATE",
"SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "All L2 data requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.ANY",
"SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "L2 data demand loads in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "L2 data demand loads in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
},
{
"BriefDescription": "L2 data demand requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -153,7 +134,6 @@
},
{
"BriefDescription": "L2 data demand loads in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -161,7 +141,6 @@
},
{
"BriefDescription": "L2 data demand loads in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -169,7 +148,6 @@
},
{
"BriefDescription": "L2 data prefetches in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -177,7 +155,6 @@
},
{
"BriefDescription": "L2 data prefetches in the I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
},
{
"BriefDescription": "All L2 data prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
},
{
"BriefDescription": "L2 data prefetches in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
},
{
"BriefDescription": "L2 data prefetches in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -209,7 +183,6 @@
},
{
"BriefDescription": "L2 lines alloacated",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ANY",
"SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
},
{
"BriefDescription": "L2 lines allocated in the E state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E_STATE",
"SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
},
{
"BriefDescription": "L2 lines allocated in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S_STATE",
"SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
},
{
"BriefDescription": "L2 lines evicted",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.ANY",
"SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
},
{
"BriefDescription": "L2 lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100000",
@@ -249,7 +218,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100000",
@@ -257,7 +225,6 @@
},
{
"BriefDescription": "L2 lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
"SampleAfterValue": "100000",
@@ -265,7 +232,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
"SampleAfterValue": "100000",
@@ -273,7 +239,6 @@
},
{
"BriefDescription": "L2 instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCHES",
"SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
},
{
"BriefDescription": "L2 instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_HIT",
"SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
},
{
"BriefDescription": "L2 instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_MISS",
"SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
},
{
"BriefDescription": "L2 load hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_HIT",
"SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
},
{
"BriefDescription": "L2 load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_MISS",
"SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
},
{
"BriefDescription": "L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LOADS",
"SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
},
{
"BriefDescription": "All L2 misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
},
{
"BriefDescription": "All L2 prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCHES",
"SampleAfterValue": "200000",
@@ -337,7 +295,6 @@
},
{
"BriefDescription": "L2 prefetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_HIT",
"SampleAfterValue": "200000",
@@ -345,7 +302,6 @@
},
{
"BriefDescription": "L2 prefetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_MISS",
"SampleAfterValue": "200000",
@@ -353,7 +309,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200000",
@@ -361,7 +316,6 @@
},
{
"BriefDescription": "L2 RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFOS",
"SampleAfterValue": "200000",
@@ -369,7 +323,6 @@
},
{
"BriefDescription": "L2 RFO hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200000",
@@ -377,7 +330,6 @@
},
{
"BriefDescription": "L2 RFO misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200000",
@@ -385,7 +337,6 @@
},
{
"BriefDescription": "All L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.ANY",
"SampleAfterValue": "200000",
@@ -393,7 +344,6 @@
},
{
"BriefDescription": "L2 fill transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.FILL",
"SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
},
{
"BriefDescription": "L2 instruction fetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.IFETCH",
"SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
},
{
"BriefDescription": "L1D writeback to L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.L1D_WB",
"SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
},
{
"BriefDescription": "L2 Load transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.LOAD",
"SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
},
{
"BriefDescription": "L2 prefetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.PREFETCH",
"SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
},
{
"BriefDescription": "L2 RFO transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.RFO",
"SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
},
{
"BriefDescription": "L2 writeback to LLC transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.WB",
"SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.E_STATE",
"SampleAfterValue": "100000",
@@ -457,7 +400,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.HIT",
"SampleAfterValue": "100000",
@@ -465,7 +407,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.I_STATE",
"SampleAfterValue": "100000",
@@ -473,7 +414,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.MESI",
"SampleAfterValue": "100000",
@@ -481,7 +421,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.M_STATE",
"SampleAfterValue": "100000",
@@ -489,7 +428,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.S_STATE",
"SampleAfterValue": "100000",
@@ -497,7 +435,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.HIT",
"SampleAfterValue": "100000",
@@ -505,7 +442,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.I_STATE",
"SampleAfterValue": "100000",
@@ -513,7 +449,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.MESI",
"SampleAfterValue": "100000",
@@ -521,7 +456,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.M_STATE",
"SampleAfterValue": "100000",
@@ -529,7 +463,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.S_STATE",
"SampleAfterValue": "100000",
@@ -537,7 +470,6 @@
},
{
"BriefDescription": "Longest latency cache miss",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100000",
@@ -545,7 +477,6 @@
},
{
"BriefDescription": "Longest latency cache reference",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200000",
@@ -553,18 +484,15 @@
},
{
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
"MSRIndex": "0x3F6",
- "MSRValue": "0x0",
"PEBS": "2",
"SampleAfterValue": "2000000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
"MSRIndex": "0x3F6",
@@ -575,7 +503,6 @@
},
{
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
"MSRIndex": "0x3F6",
@@ -586,7 +513,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
"MSRIndex": "0x3F6",
@@ -597,7 +523,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
"MSRIndex": "0x3F6",
@@ -608,7 +533,6 @@
},
{
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
"MSRIndex": "0x3F6",
@@ -619,7 +543,6 @@
},
{
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
"MSRIndex": "0x3F6",
@@ -630,7 +553,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
"MSRIndex": "0x3F6",
@@ -641,7 +563,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
"MSRIndex": "0x3F6",
@@ -652,7 +573,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
"MSRIndex": "0x3F6",
@@ -663,7 +583,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
"MSRIndex": "0x3F6",
@@ -674,7 +593,6 @@
},
{
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
"MSRIndex": "0x3F6",
@@ -685,7 +603,6 @@
},
{
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
"MSRIndex": "0x3F6",
@@ -696,7 +613,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
"MSRIndex": "0x3F6",
@@ -707,7 +623,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
"MSRIndex": "0x3F6",
@@ -718,7 +633,6 @@
},
{
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LOADS",
"PEBS": "1",
@@ -727,7 +641,6 @@
},
{
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.STORES",
"PEBS": "1",
@@ -736,7 +649,6 @@
},
{
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -745,7 +657,6 @@
},
{
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
"PEBS": "1",
@@ -754,7 +665,6 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
@@ -763,7 +673,6 @@
},
{
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -772,7 +681,6 @@
},
{
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
"PEBS": "1",
@@ -781,7 +689,6 @@
},
{
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
"PEBS": "1",
@@ -790,7 +697,6 @@
},
{
"BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
"PEBS": "1",
@@ -799,7 +705,6 @@
},
{
"BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
"PEBS": "1",
@@ -808,7 +713,6 @@
},
{
"BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
"PEBS": "1",
@@ -817,7 +721,6 @@
},
{
"BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
"PEBS": "1",
@@ -826,7 +729,6 @@
},
{
"BriefDescription": "Load instructions retired IO (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
"PEBS": "1",
@@ -835,7 +737,6 @@
},
{
"BriefDescription": "All offcore requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY",
"SampleAfterValue": "100000",
@@ -843,7 +744,6 @@
},
{
"BriefDescription": "Offcore read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY.READ",
"SampleAfterValue": "100000",
@@ -851,7 +751,6 @@
},
{
"BriefDescription": "Offcore RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY.RFO",
"SampleAfterValue": "100000",
@@ -859,7 +758,6 @@
},
{
"BriefDescription": "Offcore demand code read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
"SampleAfterValue": "100000",
@@ -867,7 +765,6 @@
},
{
"BriefDescription": "Offcore demand data read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
"SampleAfterValue": "100000",
@@ -875,7 +772,6 @@
},
{
"BriefDescription": "Offcore demand RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
"SampleAfterValue": "100000",
@@ -883,7 +779,6 @@
},
{
"BriefDescription": "Offcore L1 data cache writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
"SampleAfterValue": "100000",
@@ -891,7 +786,6 @@
},
{
"BriefDescription": "Offcore uncached memory accesses",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.UNCACHED_MEM",
"SampleAfterValue": "100000",
@@ -959,7 +853,6 @@
},
{
"BriefDescription": "Offcore requests blocked due to Super Queue full",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
"SampleAfterValue": "100000",
@@ -967,2240 +860,1833 @@
},
{
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore data reads",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x111",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x211",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x411",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x711",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2711",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code reads",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x144",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x244",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x444",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x744",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2744",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7FFF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFFFF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x27FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x58FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x122",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x222",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x422",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x722",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2722",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x108",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x408",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2708",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code or data read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x177",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x277",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x477",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x777",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2777",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any cache_dram",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any location",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x133",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x233",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x433",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x733",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache or dram",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2733",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x203",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x403",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2703",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data reads",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x101",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x201",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x401",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x701",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2701",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand code reads",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x704",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2704",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x102",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x202",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x402",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x702",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2702",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore other requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x180",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x280",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x480",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x780",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2780",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F50",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch data requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF50",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x150",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x250",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x450",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x750",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2750",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1850",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5850",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x850",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch data reads",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x710",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2710",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch code reads",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x140",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x240",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x440",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x740",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2740",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x120",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x220",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x420",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x720",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2720",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7F70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x170",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x270",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x470",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x770",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2770",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x5870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Super Queue LRU hints sent to LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.LRU_HINTS",
"SampleAfterValue": "2000000",
@@ -3208,7 +2694,6 @@
},
{
"BriefDescription": "Super Queue lock splits across a cache line",
- "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "2000000",
@@ -3216,7 +2701,6 @@
},
{
"BriefDescription": "Loads delayed with at-Retirement block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.AT_RET",
"SampleAfterValue": "200000",
@@ -3224,7 +2708,6 @@
},
{
"BriefDescription": "Cacheable loads delayed with L1D block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.L1D_BLOCK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json
index 666e466d351c..c03f8990fa82 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "X87 Floating point assists (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.ALL",
"PEBS": "1",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.INPUT",
"PEBS": "1",
@@ -19,7 +17,6 @@
},
{
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.OUTPUT",
"PEBS": "1",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "MMX Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "SSE2 integer Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "SSE* FP double precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "SSE and SSE2 FP Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "SSE FP packed Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "SSE FP scalar Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "SSE* FP single precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Computational floating-point operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "All Floating Point to and from MMX transitions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Transitions from MMX to Floating Point instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Transitions from Floating Point to MMX instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "128 bit SIMD integer pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "128 bit SIMD integer arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "128 bit SIMD integer logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "128 bit SIMD integer multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "128 bit SIMD integer unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json
index c561ac24d91d..f7f28510e3ae 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Macro-fused instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Two Uop instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json
index f14e760a9ddc..b65c5294bcf1 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json
@@ -1,738 +1,604 @@
[
{
"BriefDescription": "Offcore data reads satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x60FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF8FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x20FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x40FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any LLC miss",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF850",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4050",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that missed the LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xF870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
index 67bc34984fa8..488274980564 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "ES segment renames",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "I/O transactions",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1I instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1I instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1I Instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "Large ITLB hit",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "Loads that partially overlap an earlier store",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
"SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "All loads dispatched",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "Loads dispatched from the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "Loads dispatched that bypass the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "Loads dispatched from stage 305",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "False dependencies due to partial address aliasing",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "All Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "Segment rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "Snoop code requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.CODE",
"SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "Snoop data requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.DATA",
"SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "Snoop invalidate requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
"SampleAfterValue": "100000",
@@ -190,7 +172,6 @@
},
{
"BriefDescription": "Thread responded HIT to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
@@ -198,7 +179,6 @@
},
{
"BriefDescription": "Thread responded HITE to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
@@ -206,7 +186,6 @@
},
{
"BriefDescription": "Thread responded HITM to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
@@ -214,7 +193,6 @@
},
{
"BriefDescription": "Super Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
index 403fb2b87fc4..a29ed3522779 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles the divider is busy",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Divide Operations executed",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -20,7 +18,6 @@
},
{
"BriefDescription": "Multiply operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.MUL",
"SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "BACLEAR asserted with bad target address",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.BAD_TARGET",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "BACLEAR asserted, regardless of cause",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.CLEAR",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "Instruction queue forced BACLEAR",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "BACLEAR_FORCE_IQ",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "Branch instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ANY",
"SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "Conditional branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.COND",
"SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT",
"SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Unconditional call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "Indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "Indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "Call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NEAR_CALLS",
"SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "All non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NON_CALLS",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "Indirect return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.RETURN_NEAR",
"SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "Taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "Retired branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -173,7 +152,6 @@
},
{
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -182,7 +160,6 @@
},
{
"BriefDescription": "Retired near call instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -191,7 +168,6 @@
},
{
"BriefDescription": "Mispredicted branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ANY",
"SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
},
{
"BriefDescription": "Mispredicted conditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.COND",
"SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
},
{
"BriefDescription": "Mispredicted unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT",
"SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
},
{
"BriefDescription": "Mispredicted indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
},
{
"BriefDescription": "Mispredicted indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
},
{
"BriefDescription": "Mispredicted call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
"SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NON_CALLS",
"SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
},
{
"BriefDescription": "Mispredicted return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
"SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
},
{
"BriefDescription": "Mispredicted taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN",
"SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
},
{
"BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -280,7 +246,6 @@
},
{
"BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -289,7 +254,6 @@
},
{
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -298,15 +262,11 @@
},
{
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 3",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.REF",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_P",
"SampleAfterValue": "100000",
@@ -314,33 +274,25 @@
},
{
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 2",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Total CPU cycles",
- "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
"Invert": "1",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Any Instruction Length Decoder stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.ANY",
"SampleAfterValue": "2000000",
@@ -348,7 +300,6 @@
},
{
"BriefDescription": "Instruction Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@@ -356,7 +307,6 @@
},
{
"BriefDescription": "Length Change Prefix stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000000",
@@ -364,7 +314,6 @@
},
{
"BriefDescription": "Stall cycles due to BPU MRU bypass",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.MRU",
"SampleAfterValue": "2000000",
@@ -372,7 +321,6 @@
},
{
"BriefDescription": "Regen stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.REGEN",
"SampleAfterValue": "2000000",
@@ -380,7 +328,6 @@
},
{
"BriefDescription": "Instructions that must be decoded by decoder 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "INST_DECODED.DEC0",
"SampleAfterValue": "2000000",
@@ -388,7 +335,6 @@
},
{
"BriefDescription": "Instructions written to instruction queue.",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INST_QUEUE_WRITES",
"SampleAfterValue": "2000000",
@@ -396,7 +342,6 @@
},
{
"BriefDescription": "Cycles instructions are written to the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "INST_QUEUE_WRITE_CYCLES",
"SampleAfterValue": "2000000",
@@ -404,15 +349,11 @@
},
{
"BriefDescription": "Instructions retired (fixed counter)",
- "Counter": "Fixed counter 1",
- "EventCode": "0x0",
"EventName": "INST_RETIRED.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@@ -421,7 +362,6 @@
},
{
"BriefDescription": "Retired MMX instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.MMX",
"PEBS": "1",
@@ -430,7 +370,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -441,7 +380,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -452,7 +390,6 @@
},
{
"BriefDescription": "Retired floating-point operations (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PEBS": "1",
@@ -461,7 +398,6 @@
},
{
"BriefDescription": "Load operations conflicting with software prefetches",
- "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE",
"SampleAfterValue": "200000",
@@ -469,7 +405,6 @@
},
{
"BriefDescription": "Cycles when uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.ACTIVE",
@@ -478,7 +413,6 @@
},
{
"BriefDescription": "Cycles no uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.INACTIVE",
@@ -488,7 +422,6 @@
},
{
"BriefDescription": "Loops that can't stream from the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "LSD_OVERFLOW",
"SampleAfterValue": "2000000",
@@ -496,7 +429,6 @@
},
{
"BriefDescription": "Cycles machine clear asserted",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "20000",
@@ -504,7 +436,6 @@
},
{
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEM_ORDER",
"SampleAfterValue": "20000",
@@ -512,7 +443,6 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20000",
@@ -520,7 +450,6 @@
},
{
"BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -528,7 +457,6 @@
},
{
"BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
@@ -536,7 +464,6 @@
},
{
"BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
@@ -544,7 +471,6 @@
},
{
"BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
@@ -552,7 +478,6 @@
},
{
"BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
@@ -560,7 +485,6 @@
},
{
"BriefDescription": "Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -568,7 +492,6 @@
},
{
"BriefDescription": "FPU control word write stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.FPCW",
"SampleAfterValue": "2000000",
@@ -576,7 +499,6 @@
},
{
"BriefDescription": "Load buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LOAD",
"SampleAfterValue": "2000000",
@@ -584,7 +506,6 @@
},
{
"BriefDescription": "MXCSR rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MXCSR",
"SampleAfterValue": "2000000",
@@ -592,7 +513,6 @@
},
{
"BriefDescription": "Other Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OTHER",
"SampleAfterValue": "2000000",
@@ -600,7 +520,6 @@
},
{
"BriefDescription": "ROB full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB_FULL",
"SampleAfterValue": "2000000",
@@ -608,7 +527,6 @@
},
{
"BriefDescription": "Reservation Station full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS_FULL",
"SampleAfterValue": "2000000",
@@ -616,7 +534,6 @@
},
{
"BriefDescription": "Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.STORE",
"SampleAfterValue": "2000000",
@@ -624,7 +541,6 @@
},
{
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
"PEBS": "1",
@@ -633,7 +549,6 @@
},
{
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
"PEBS": "1",
@@ -642,7 +557,6 @@
},
{
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
"PEBS": "1",
@@ -651,7 +565,6 @@
},
{
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
"PEBS": "1",
@@ -660,7 +573,6 @@
},
{
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
"PEBS": "1",
@@ -669,7 +581,6 @@
},
{
"BriefDescription": "Stack pointer instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_FOLDING",
"SampleAfterValue": "2000000",
@@ -677,7 +588,6 @@
},
{
"BriefDescription": "Stack pointer sync operations",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_SYNC",
"SampleAfterValue": "2000000",
@@ -685,7 +595,6 @@
},
{
"BriefDescription": "Uops decoded by Microcode Sequencer",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -694,7 +603,6 @@
},
{
"BriefDescription": "Cycles no Uops are decoded",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -705,7 +613,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -715,7 +622,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -725,7 +631,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -737,7 +642,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -749,7 +653,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -760,7 +663,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -770,7 +672,6 @@
},
{
"BriefDescription": "Uops executed on port 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT0",
"SampleAfterValue": "2000000",
@@ -778,7 +679,6 @@
},
{
"BriefDescription": "Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015",
"SampleAfterValue": "2000000",
@@ -786,7 +686,6 @@
},
{
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -796,7 +695,6 @@
},
{
"BriefDescription": "Uops executed on port 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT1",
"SampleAfterValue": "2000000",
@@ -805,7 +703,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops issued on ports 2, 3 or 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT234_CORE",
"SampleAfterValue": "2000000",
@@ -814,7 +711,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 2 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT2_CORE",
"SampleAfterValue": "2000000",
@@ -823,7 +719,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 3 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT3_CORE",
"SampleAfterValue": "2000000",
@@ -832,7 +727,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 4 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT4_CORE",
"SampleAfterValue": "2000000",
@@ -840,7 +734,6 @@
},
{
"BriefDescription": "Uops executed on port 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT5",
"SampleAfterValue": "2000000",
@@ -848,7 +741,6 @@
},
{
"BriefDescription": "Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000000",
@@ -857,7 +749,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops were issued on any thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -868,7 +759,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops were issued on either thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -877,7 +767,6 @@
},
{
"BriefDescription": "Fused Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.FUSED",
"SampleAfterValue": "2000000",
@@ -885,7 +774,6 @@
},
{
"BriefDescription": "Cycles no Uops were issued",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -895,7 +783,6 @@
},
{
"BriefDescription": "Cycles Uops are being retired",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -905,7 +792,6 @@
},
{
"BriefDescription": "Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "1",
@@ -914,7 +800,6 @@
},
{
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PEBS": "1",
@@ -923,7 +808,6 @@
},
{
"BriefDescription": "Retirement slots used (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -932,7 +816,6 @@
},
{
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -943,7 +826,6 @@
},
{
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -954,7 +836,6 @@
},
{
"BriefDescription": "Uop unfusions due to FP exceptions",
- "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UOP_UNFUSION",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
index e7affdf7f41b..80efcfd48239 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "DTLB load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "DTLB load miss caused by low part of address",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "DTLB second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "DTLB load miss page walks complete",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "DTLB load miss page walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
"SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "DTLB misses",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "DTLB miss large page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "DTLB first level misses but second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "DTLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "DTLB miss page walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "Extended Page Table walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "ITLB flushes",
- "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "ITLB miss",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "ITLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "ITLB miss page walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
@@ -130,7 +114,6 @@
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
@@ -139,7 +122,6 @@
},
{
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v1 32/32] perf vendor events intel: Refresh westmereex events
2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
` (21 preceding siblings ...)
2022-12-15 6:55 ` [PATCH v1 31/32] perf vendor events intel: Refresh westmereep-sp events Ian Rogers
@ 2022-12-15 6:55 ` Ian Rogers
22 siblings, 0 replies; 24+ messages in thread
From: Ian Rogers @ 2022-12-15 6:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the westmereex events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/westmereex/cache.json | 516 ------------------
.../arch/x86/westmereex/floating-point.json | 28 -
.../arch/x86/westmereex/frontend.json | 3 -
.../arch/x86/westmereex/memory.json | 135 -----
.../pmu-events/arch/x86/westmereex/other.json | 22 -
.../arch/x86/westmereex/pipeline.json | 129 +----
.../arch/x86/westmereex/virtual-memory.json | 21 -
7 files changed, 5 insertions(+), 849 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/cache.json b/tools/perf/pmu-events/arch/x86/westmereex/cache.json
index d6243d008bfe..6c7c52733dda 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/cache.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles L1D locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Cycles L1D and L2 locked",
- "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1D cache lines replaced in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_EVICT",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1D cache lines allocated in the M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_REPL",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1D snoop eviction of cache lines in M state",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_SNOOP_EVICT",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1 data cache lines allocated",
- "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.REPL",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
- "Counter": "0,1",
"EventCode": "0x52",
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "L1D hardware prefetch misses",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.MISS",
"SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.REQUESTS",
"SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "L1D hardware prefetch requests triggered",
- "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.TRIGGERS",
"SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.E_STATE",
"SampleAfterValue": "100000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.I_STATE",
"SampleAfterValue": "100000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "All L1 writebacks to L2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.MESI",
"SampleAfterValue": "100000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.M_STATE",
"SampleAfterValue": "100000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "L1 writebacks to L2 in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.S_STATE",
"SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "All L2 data requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.ANY",
"SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "L2 data demand loads in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "L2 data demand loads in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
},
{
"BriefDescription": "L2 data demand requests",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -153,7 +134,6 @@
},
{
"BriefDescription": "L2 data demand loads in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -161,7 +141,6 @@
},
{
"BriefDescription": "L2 data demand loads in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -169,7 +148,6 @@
},
{
"BriefDescription": "L2 data prefetches in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -177,7 +155,6 @@
},
{
"BriefDescription": "L2 data prefetches in the I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
},
{
"BriefDescription": "All L2 data prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
},
{
"BriefDescription": "L2 data prefetches in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
},
{
"BriefDescription": "L2 data prefetches in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -209,7 +183,6 @@
},
{
"BriefDescription": "L2 lines alloacated",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ANY",
"SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
},
{
"BriefDescription": "L2 lines allocated in the E state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E_STATE",
"SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
},
{
"BriefDescription": "L2 lines allocated in the S state",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S_STATE",
"SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
},
{
"BriefDescription": "L2 lines evicted",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.ANY",
"SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
},
{
"BriefDescription": "L2 lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100000",
@@ -249,7 +218,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a demand request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100000",
@@ -257,7 +225,6 @@
},
{
"BriefDescription": "L2 lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
"SampleAfterValue": "100000",
@@ -265,7 +232,6 @@
},
{
"BriefDescription": "L2 modified lines evicted by a prefetch request",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
"SampleAfterValue": "100000",
@@ -273,7 +239,6 @@
},
{
"BriefDescription": "L2 instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCHES",
"SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
},
{
"BriefDescription": "L2 instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_HIT",
"SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
},
{
"BriefDescription": "L2 instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_MISS",
"SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
},
{
"BriefDescription": "L2 load hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_HIT",
"SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
},
{
"BriefDescription": "L2 load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_MISS",
"SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
},
{
"BriefDescription": "L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LOADS",
"SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
},
{
"BriefDescription": "All L2 misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
},
{
"BriefDescription": "All L2 prefetches",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCHES",
"SampleAfterValue": "200000",
@@ -337,7 +295,6 @@
},
{
"BriefDescription": "L2 prefetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_HIT",
"SampleAfterValue": "200000",
@@ -345,7 +302,6 @@
},
{
"BriefDescription": "L2 prefetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_MISS",
"SampleAfterValue": "200000",
@@ -353,7 +309,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200000",
@@ -361,7 +316,6 @@
},
{
"BriefDescription": "L2 RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFOS",
"SampleAfterValue": "200000",
@@ -369,7 +323,6 @@
},
{
"BriefDescription": "L2 RFO hits",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200000",
@@ -377,7 +330,6 @@
},
{
"BriefDescription": "L2 RFO misses",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200000",
@@ -385,7 +337,6 @@
},
{
"BriefDescription": "All L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.ANY",
"SampleAfterValue": "200000",
@@ -393,7 +344,6 @@
},
{
"BriefDescription": "L2 fill transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.FILL",
"SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
},
{
"BriefDescription": "L2 instruction fetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.IFETCH",
"SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
},
{
"BriefDescription": "L1D writeback to L2 transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.L1D_WB",
"SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
},
{
"BriefDescription": "L2 Load transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.LOAD",
"SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
},
{
"BriefDescription": "L2 prefetch transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.PREFETCH",
"SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
},
{
"BriefDescription": "L2 RFO transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.RFO",
"SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
},
{
"BriefDescription": "L2 writeback to LLC transactions",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.WB",
"SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.E_STATE",
"SampleAfterValue": "100000",
@@ -457,7 +400,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.HIT",
"SampleAfterValue": "100000",
@@ -465,7 +407,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.I_STATE",
"SampleAfterValue": "100000",
@@ -473,7 +414,6 @@
},
{
"BriefDescription": "All demand L2 lock RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.MESI",
"SampleAfterValue": "100000",
@@ -481,7 +421,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.M_STATE",
"SampleAfterValue": "100000",
@@ -489,7 +428,6 @@
},
{
"BriefDescription": "L2 demand lock RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.S_STATE",
"SampleAfterValue": "100000",
@@ -497,7 +435,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs that hit the cache",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.HIT",
"SampleAfterValue": "100000",
@@ -505,7 +442,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in I state (misses)",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.I_STATE",
"SampleAfterValue": "100000",
@@ -513,7 +449,6 @@
},
{
"BriefDescription": "All L2 demand store RFOs",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.MESI",
"SampleAfterValue": "100000",
@@ -521,7 +456,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.M_STATE",
"SampleAfterValue": "100000",
@@ -529,7 +463,6 @@
},
{
"BriefDescription": "L2 demand store RFOs in S state",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.S_STATE",
"SampleAfterValue": "100000",
@@ -537,7 +470,6 @@
},
{
"BriefDescription": "Longest latency cache miss",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100000",
@@ -545,7 +477,6 @@
},
{
"BriefDescription": "Longest latency cache reference",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200000",
@@ -553,18 +484,15 @@
},
{
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
"MSRIndex": "0x3F6",
- "MSRValue": "0x0",
"PEBS": "2",
"SampleAfterValue": "2000000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
"MSRIndex": "0x3F6",
@@ -575,7 +503,6 @@
},
{
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
"MSRIndex": "0x3F6",
@@ -586,7 +513,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
"MSRIndex": "0x3F6",
@@ -597,7 +523,6 @@
},
{
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
"MSRIndex": "0x3F6",
@@ -608,7 +533,6 @@
},
{
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
"MSRIndex": "0x3F6",
@@ -619,7 +543,6 @@
},
{
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
"MSRIndex": "0x3F6",
@@ -630,7 +553,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
"MSRIndex": "0x3F6",
@@ -641,7 +563,6 @@
},
{
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
"MSRIndex": "0x3F6",
@@ -652,7 +573,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
"MSRIndex": "0x3F6",
@@ -663,7 +583,6 @@
},
{
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
"MSRIndex": "0x3F6",
@@ -674,7 +593,6 @@
},
{
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
"MSRIndex": "0x3F6",
@@ -685,7 +603,6 @@
},
{
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
"MSRIndex": "0x3F6",
@@ -696,7 +613,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
"MSRIndex": "0x3F6",
@@ -707,7 +623,6 @@
},
{
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
- "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
"MSRIndex": "0x3F6",
@@ -718,7 +633,6 @@
},
{
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LOADS",
"PEBS": "1",
@@ -727,7 +641,6 @@
},
{
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.STORES",
"PEBS": "1",
@@ -736,7 +649,6 @@
},
{
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -745,7 +657,6 @@
},
{
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
"PEBS": "1",
@@ -754,7 +665,6 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
@@ -763,7 +673,6 @@
},
{
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -772,7 +681,6 @@
},
{
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
"PEBS": "1",
@@ -781,7 +689,6 @@
},
{
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
"PEBS": "1",
@@ -790,7 +697,6 @@
},
{
"BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"PEBS": "1",
@@ -799,7 +705,6 @@
},
{
"BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM",
"PEBS": "1",
@@ -808,7 +713,6 @@
},
{
"BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
"PEBS": "1",
@@ -817,7 +721,6 @@
},
{
"BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM",
"PEBS": "1",
@@ -826,7 +729,6 @@
},
{
"BriefDescription": "Load instructions retired IO (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
"PEBS": "1",
@@ -835,7 +737,6 @@
},
{
"BriefDescription": "All offcore requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY",
"SampleAfterValue": "100000",
@@ -843,7 +744,6 @@
},
{
"BriefDescription": "Offcore read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY.READ",
"SampleAfterValue": "100000",
@@ -851,7 +751,6 @@
},
{
"BriefDescription": "Offcore RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY.RFO",
"SampleAfterValue": "100000",
@@ -859,7 +758,6 @@
},
{
"BriefDescription": "Offcore demand code read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
"SampleAfterValue": "100000",
@@ -867,7 +765,6 @@
},
{
"BriefDescription": "Offcore demand data read requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
"SampleAfterValue": "100000",
@@ -875,7 +772,6 @@
},
{
"BriefDescription": "Offcore demand RFO requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
"SampleAfterValue": "100000",
@@ -883,7 +779,6 @@
},
{
"BriefDescription": "Offcore L1 data cache writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
"SampleAfterValue": "100000",
@@ -951,7 +846,6 @@
},
{
"BriefDescription": "Offcore requests blocked due to Super Queue full",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
"SampleAfterValue": "100000",
@@ -959,2240 +853,1833 @@
},
{
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore data reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF11",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x111",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x211",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x411",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x711",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4711",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF44",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x144",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x244",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x444",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x744",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4744",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7FFF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFFFF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x80FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x2FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x7FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x47FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x18FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x38FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x10FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x8FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore RFO requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF22",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x122",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x222",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x422",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x722",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4722",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore writebacks",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF08",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x108",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x408",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x708",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4708",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code or data read requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF77",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x177",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x277",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x477",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x777",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4777",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any cache_dram",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any location",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF33",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x133",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x233",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x433",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x733",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache or dram",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4733",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF03",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x103",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x203",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x403",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x703",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4703",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF01",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x101",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x201",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x401",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x701",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4701",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand code reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF04",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x104",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x204",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x404",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x704",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4704",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand RFO requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF02",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x102",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x202",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x402",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x702",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4702",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore other requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF80",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x180",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x280",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x480",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x780",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4780",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F30",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch data requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF30",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x130",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x230",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x430",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x730",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4730",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch data reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF10",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x110",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x210",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x410",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x710",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4710",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch code reads",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF40",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x140",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x240",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x440",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x740",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4740",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch RFO requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF20",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x120",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x220",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x420",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x720",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4720",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore prefetch requests",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF70",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x170",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x270",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x470",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x770",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4770",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Super Queue LRU hints sent to LLC",
- "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.LRU_HINTS",
"SampleAfterValue": "2000000",
@@ -3200,7 +2687,6 @@
},
{
"BriefDescription": "Super Queue lock splits across a cache line",
- "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "2000000",
@@ -3208,7 +2694,6 @@
},
{
"BriefDescription": "Loads delayed with at-Retirement block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.AT_RET",
"SampleAfterValue": "200000",
@@ -3216,7 +2701,6 @@
},
{
"BriefDescription": "Cacheable loads delayed with L1D block code",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.L1D_BLOCK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
index 666e466d351c..c03f8990fa82 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "X87 Floating point assists (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.ALL",
"PEBS": "1",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.INPUT",
"PEBS": "1",
@@ -19,7 +17,6 @@
},
{
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.OUTPUT",
"PEBS": "1",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "MMX Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "SSE2 integer Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "SSE* FP double precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "SSE and SSE2 FP Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "SSE FP packed Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "SSE FP scalar Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "SSE* FP single precision Uops",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Computational floating-point operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "All Floating Point to and from MMX transitions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Transitions from MMX to Floating Point instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Transitions from Floating Point to MMX instructions",
- "Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "128 bit SIMD integer pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "128 bit SIMD integer arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "128 bit SIMD integer logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "128 bit SIMD integer multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "128 bit SIMD integer unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit pack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit logical operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shift operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
},
{
"BriefDescription": "SIMD integer 64 bit unpack operations",
- "Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json
index c561ac24d91d..f7f28510e3ae 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Macro-fused instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Two Uop instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/memory.json b/tools/perf/pmu-events/arch/x86/westmereex/memory.json
index 1f8cfabe08c0..f3c0d2d4bc6a 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Misaligned store references",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.STORE",
"SampleAfterValue": "200000",
@@ -9,738 +8,604 @@
},
{
"BriefDescription": "Offcore data reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF811",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2011",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF844",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2044",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x60FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF8FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x40FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x20FF",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF822",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2022",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF808",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2008",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF877",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2077",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any LLC miss",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF833",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2033",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF803",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2003",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF801",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2001",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF804",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2004",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF802",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2002",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF880",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2080",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF830",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2030",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF810",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2010",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF840",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2040",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF820",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2020",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x6070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests that missed the LLC",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
"MSRValue": "0xF870",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
- "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x2070",
- "Offcore": "1",
"SampleAfterValue": "100000",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/perf/pmu-events/arch/x86/westmereex/other.json
index 67bc34984fa8..488274980564 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "ES segment renames",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "I/O transactions",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1I instruction fetch hits",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1I instruction fetch misses",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "L1I Instruction fetches",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "Large ITLB hit",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "Loads that partially overlap an earlier store",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
"SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "All loads dispatched",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "Loads dispatched from the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "Loads dispatched that bypass the MOB",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "Loads dispatched from stage 305",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "False dependencies due to partial address aliasing",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "All Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "Segment rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "Snoop code requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.CODE",
"SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "Snoop data requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.DATA",
"SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "Snoop invalidate requests",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
"SampleAfterValue": "100000",
@@ -190,7 +172,6 @@
},
{
"BriefDescription": "Thread responded HIT to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
@@ -198,7 +179,6 @@
},
{
"BriefDescription": "Thread responded HITE to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
@@ -206,7 +186,6 @@
},
{
"BriefDescription": "Thread responded HITM to snoop",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
@@ -214,7 +193,6 @@
},
{
"BriefDescription": "Super Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
index 7d6c2c1e0db0..1c61d18a4b5f 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Cycles the divider is busy",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Divide Operations executed",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -20,7 +18,6 @@
},
{
"BriefDescription": "Multiply operations executed",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.MUL",
"SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "BACLEAR asserted with bad target address",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.BAD_TARGET",
"SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "BACLEAR asserted, regardless of cause",
- "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.CLEAR",
"SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "Instruction queue forced BACLEAR",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "BACLEAR_FORCE_IQ",
"SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
},
{
"BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
},
{
"BriefDescription": "Branch instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
},
{
"BriefDescription": "Branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ANY",
"SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
},
{
"BriefDescription": "Conditional branch instructions executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.COND",
"SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
},
{
"BriefDescription": "Unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT",
"SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
},
{
"BriefDescription": "Unconditional call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
},
{
"BriefDescription": "Indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
},
{
"BriefDescription": "Indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
},
{
"BriefDescription": "Call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NEAR_CALLS",
"SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
},
{
"BriefDescription": "All non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NON_CALLS",
"SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
},
{
"BriefDescription": "Indirect return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.RETURN_NEAR",
"SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
},
{
"BriefDescription": "Taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN",
"SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
},
{
"BriefDescription": "Retired branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -173,7 +152,6 @@
},
{
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -182,7 +160,6 @@
},
{
"BriefDescription": "Retired near call instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -191,7 +168,6 @@
},
{
"BriefDescription": "Mispredicted branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ANY",
"SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
},
{
"BriefDescription": "Mispredicted conditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.COND",
"SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
},
{
"BriefDescription": "Mispredicted unconditional branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT",
"SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
},
{
"BriefDescription": "Mispredicted indirect call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
},
{
"BriefDescription": "Mispredicted indirect non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
},
{
"BriefDescription": "Mispredicted call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
"SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NON_CALLS",
"SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
},
{
"BriefDescription": "Mispredicted return branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
"SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
},
{
"BriefDescription": "Mispredicted taken branches executed",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN",
"SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
},
{
"BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -280,7 +246,6 @@
},
{
"BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -289,7 +254,6 @@
},
{
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -298,15 +262,11 @@
},
{
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 3",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.REF",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_P",
"SampleAfterValue": "100000",
@@ -314,33 +274,25 @@
},
{
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
- "Counter": "Fixed counter 2",
- "EventCode": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Total CPU cycles",
- "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
"Invert": "1",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Any Instruction Length Decoder stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.ANY",
"SampleAfterValue": "2000000",
@@ -348,7 +300,6 @@
},
{
"BriefDescription": "Instruction Queue full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@@ -356,7 +307,6 @@
},
{
"BriefDescription": "Length Change Prefix stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000000",
@@ -364,7 +314,6 @@
},
{
"BriefDescription": "Stall cycles due to BPU MRU bypass",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.MRU",
"SampleAfterValue": "2000000",
@@ -372,7 +321,6 @@
},
{
"BriefDescription": "Regen stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.REGEN",
"SampleAfterValue": "2000000",
@@ -380,7 +328,6 @@
},
{
"BriefDescription": "Instructions that must be decoded by decoder 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "INST_DECODED.DEC0",
"SampleAfterValue": "2000000",
@@ -388,7 +335,6 @@
},
{
"BriefDescription": "Instructions written to instruction queue.",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INST_QUEUE_WRITES",
"SampleAfterValue": "2000000",
@@ -396,7 +342,6 @@
},
{
"BriefDescription": "Cycles instructions are written to the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "INST_QUEUE_WRITE_CYCLES",
"SampleAfterValue": "2000000",
@@ -404,15 +349,11 @@
},
{
"BriefDescription": "Instructions retired (fixed counter)",
- "Counter": "Fixed counter 1",
- "EventCode": "0x0",
"EventName": "INST_RETIRED.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0x0"
+ "SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@@ -421,7 +362,6 @@
},
{
"BriefDescription": "Retired MMX instructions (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.MMX",
"PEBS": "1",
@@ -430,7 +370,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -441,7 +380,6 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -452,7 +390,6 @@
},
{
"BriefDescription": "Retired floating-point operations (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PEBS": "1",
@@ -461,7 +398,6 @@
},
{
"BriefDescription": "Load operations conflicting with software prefetches",
- "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE",
"SampleAfterValue": "200000",
@@ -469,7 +405,6 @@
},
{
"BriefDescription": "Cycles when uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.ACTIVE",
@@ -478,7 +413,6 @@
},
{
"BriefDescription": "Cycles no uops were delivered by the LSD",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.INACTIVE",
@@ -488,7 +422,6 @@
},
{
"BriefDescription": "Loops that can't stream from the instruction queue",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "LSD_OVERFLOW",
"SampleAfterValue": "2000000",
@@ -496,7 +429,6 @@
},
{
"BriefDescription": "Cycles machine clear asserted",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "20000",
@@ -504,7 +436,6 @@
},
{
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEM_ORDER",
"SampleAfterValue": "20000",
@@ -512,7 +443,6 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
- "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20000",
@@ -520,7 +450,6 @@
},
{
"BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -528,7 +457,6 @@
},
{
"BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
@@ -536,7 +464,6 @@
},
{
"BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
@@ -544,7 +471,6 @@
},
{
"BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
@@ -552,7 +478,6 @@
},
{
"BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
@@ -560,7 +485,6 @@
},
{
"BriefDescription": "Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000000",
@@ -568,7 +492,6 @@
},
{
"BriefDescription": "FPU control word write stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.FPCW",
"SampleAfterValue": "2000000",
@@ -576,7 +499,6 @@
},
{
"BriefDescription": "Load buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LOAD",
"SampleAfterValue": "2000000",
@@ -584,7 +506,6 @@
},
{
"BriefDescription": "MXCSR rename stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MXCSR",
"SampleAfterValue": "2000000",
@@ -592,7 +513,6 @@
},
{
"BriefDescription": "Other Resource related stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OTHER",
"SampleAfterValue": "2000000",
@@ -600,7 +520,6 @@
},
{
"BriefDescription": "ROB full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB_FULL",
"SampleAfterValue": "2000000",
@@ -608,7 +527,6 @@
},
{
"BriefDescription": "Reservation Station full stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS_FULL",
"SampleAfterValue": "2000000",
@@ -616,7 +534,6 @@
},
{
"BriefDescription": "Store buffer stall cycles",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.STORE",
"SampleAfterValue": "2000000",
@@ -624,7 +541,6 @@
},
{
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
"PEBS": "1",
@@ -633,7 +549,6 @@
},
{
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
"PEBS": "1",
@@ -642,7 +557,6 @@
},
{
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
"PEBS": "1",
@@ -651,7 +565,6 @@
},
{
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
"PEBS": "1",
@@ -660,7 +573,6 @@
},
{
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
"PEBS": "1",
@@ -669,7 +581,6 @@
},
{
"BriefDescription": "Stack pointer instructions decoded",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_FOLDING",
"SampleAfterValue": "2000000",
@@ -677,7 +588,6 @@
},
{
"BriefDescription": "Stack pointer sync operations",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_SYNC",
"SampleAfterValue": "2000000",
@@ -685,7 +595,6 @@
},
{
"BriefDescription": "Uops decoded by Microcode Sequencer",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -694,7 +603,6 @@
},
{
"BriefDescription": "Cycles no Uops are decoded",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -705,7 +613,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -715,7 +622,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -724,7 +630,6 @@
},
{
"BriefDescription": "Uops executed on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -735,7 +640,6 @@
},
{
"BriefDescription": "Uops executed on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@@ -747,7 +651,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on any port (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -758,7 +661,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -768,7 +670,6 @@
},
{
"BriefDescription": "Uops executed on port 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT0",
"SampleAfterValue": "2000000",
@@ -776,7 +677,6 @@
},
{
"BriefDescription": "Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015",
"SampleAfterValue": "2000000",
@@ -784,7 +684,6 @@
},
{
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -794,7 +693,6 @@
},
{
"BriefDescription": "Uops executed on port 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT1",
"SampleAfterValue": "2000000",
@@ -803,7 +701,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops issued on ports 2, 3 or 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT234_CORE",
"SampleAfterValue": "2000000",
@@ -812,7 +709,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 2 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT2_CORE",
"SampleAfterValue": "2000000",
@@ -821,7 +717,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 3 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT3_CORE",
"SampleAfterValue": "2000000",
@@ -830,7 +725,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 4 (core count)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT4_CORE",
"SampleAfterValue": "2000000",
@@ -838,7 +732,6 @@
},
{
"BriefDescription": "Uops executed on port 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT5",
"SampleAfterValue": "2000000",
@@ -846,7 +739,6 @@
},
{
"BriefDescription": "Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000000",
@@ -855,7 +747,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops were issued on any thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -866,7 +757,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops were issued on either thread",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -875,7 +765,6 @@
},
{
"BriefDescription": "Fused Uops issued",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.FUSED",
"SampleAfterValue": "2000000",
@@ -883,7 +772,6 @@
},
{
"BriefDescription": "Cycles no Uops were issued",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -893,7 +781,6 @@
},
{
"BriefDescription": "Cycles Uops are being retired",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -903,7 +790,6 @@
},
{
"BriefDescription": "Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "1",
@@ -912,7 +798,6 @@
},
{
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PEBS": "1",
@@ -921,7 +806,6 @@
},
{
"BriefDescription": "Retirement slots used (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -930,7 +814,6 @@
},
{
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -941,7 +824,6 @@
},
{
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
- "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -952,7 +834,6 @@
},
{
"BriefDescription": "Uop unfusions due to FP exceptions",
- "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UOP_UNFUSION",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
index 0c3501e6e5a3..6c92b2be2d06 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "DTLB load misses",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "DTLB load miss large page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "DTLB load miss caused by low part of address",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "DTLB second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "DTLB load miss page walks complete",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "DTLB load miss page walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
"SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "DTLB misses",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
},
{
"BriefDescription": "DTLB miss large page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
},
{
"BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
},
{
"BriefDescription": "DTLB first level misses but second level hit",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
},
{
"BriefDescription": "DTLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -89,7 +78,6 @@
},
{
"BriefDescription": "DTLB miss page walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
},
{
"BriefDescription": "Extended Page Table walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000000",
@@ -105,7 +92,6 @@
},
{
"BriefDescription": "ITLB flushes",
- "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
},
{
"BriefDescription": "ITLB miss",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
@@ -121,7 +106,6 @@
},
{
"BriefDescription": "ITLB miss large page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
},
{
"BriefDescription": "ITLB miss page walks",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
},
{
"BriefDescription": "ITLB miss page walk cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
@@ -145,7 +127,6 @@
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
@@ -154,7 +135,6 @@
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
@@ -163,7 +143,6 @@
},
{
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 24+ messages in thread
end of thread, other threads:[~2022-12-15 7:04 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
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2022-12-15 6:54 [PATCH v1 09/32] perf vendor events intel: Refresh elkhartlake events Ian Rogers
2022-12-15 6:54 ` [PATCH v1 10/32] perf vendor events intel: Refresh goldmont events Ian Rogers
2022-12-15 6:54 ` [PATCH v1 11/32] perf vendor events intel: Refresh goldmontplus events Ian Rogers
2022-12-15 6:54 ` [PATCH v1 12/32] perf vendor events intel: Refresh haswell metrics and events Ian Rogers
2022-12-15 6:54 ` [PATCH v1 13/32] perf vendor events intel: Refresh haswellx " Ian Rogers
2022-12-15 6:54 ` [PATCH v1 14/32] perf vendor events intel: Refresh icelake " Ian Rogers
2022-12-15 6:54 ` [PATCH v1 15/32] perf vendor events intel: Refresh icelakex " Ian Rogers
2022-12-15 6:54 ` [PATCH v1 16/32] perf vendor events intel: Refresh ivybridge " Ian Rogers
2022-12-15 6:54 ` [PATCH v1 17/32] perf vendor events intel: Refresh ivytown " Ian Rogers
2022-12-15 6:54 ` [PATCH v1 18/32] perf vendor events intel: Refresh jaketown " Ian Rogers
2022-12-15 6:54 ` [PATCH v1 19/32] perf vendor events intel: Refresh knightslanding events Ian Rogers
2022-12-15 6:54 ` [PATCH v1 20/32] perf vendor events intel: Refresh meteorlake events Ian Rogers
2022-12-15 6:54 ` [PATCH v1 21/32] perf vendor events intel: Refresh nehalemep events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 22/32] perf vendor events intel: Refresh nehalemex events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 23/32] perf vendor events intel: Refresh sandybridge metrics and events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 24/32] perf vendor events intel: Refresh sapphirerapids " Ian Rogers
2022-12-15 6:55 ` [PATCH v1 25/32] perf vendor events intel: Refresh silvermont events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 26/32] perf vendor events intel: Refresh skylake metrics and events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 27/32] perf vendor events intel: Refresh skylakex " Ian Rogers
2022-12-15 6:55 ` [PATCH v1 28/32] perf vendor events intel: Refresh snowridgex events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 29/32] perf vendor events intel: Refresh tigerlake metrics and events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 30/32] perf vendor events intel: Refresh westmereep-dp events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 31/32] perf vendor events intel: Refresh westmereep-sp events Ian Rogers
2022-12-15 6:55 ` [PATCH v1 32/32] perf vendor events intel: Refresh westmereex events Ian Rogers
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